133 	struct ena_com_aenq *aenq = &ena_dev->aenq;  in ena_com_admin_init_aenq()  local
137 	ena_dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;  in ena_com_admin_init_aenq()
139 	aenq->entries = dma_alloc_coherent(ena_dev->dmadev, size,  in ena_com_admin_init_aenq()
140 					   &aenq->dma_addr, GFP_KERNEL);  in ena_com_admin_init_aenq()
142 	if (!aenq->entries) {  in ena_com_admin_init_aenq()
147 	aenq->head = aenq->q_depth;  in ena_com_admin_init_aenq()
148 	aenq->phase = 1;  in ena_com_admin_init_aenq()
150 	addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);  in ena_com_admin_init_aenq()
151 	addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);  in ena_com_admin_init_aenq()
157 	aenq_caps |= ena_dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;  in ena_com_admin_init_aenq()
169 	aenq->aenq_handlers = aenq_handlers;  in ena_com_admin_init_aenq()
1545 	u16 depth = ena_dev->aenq.q_depth;  in ena_com_admin_aenq_enable()
1547 	WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");  in ena_com_admin_aenq_enable()
1569 	if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {  in ena_com_set_aenq_config()
1572 			    get_resp.u.aenq.supported_groups, groups_flag);  in ena_com_set_aenq_config()
1582 	cmd.u.aenq.enabled_groups = groups_flag;  in ena_com_set_aenq_config()
1690 	struct ena_com_aenq *aenq = &ena_dev->aenq;  in ena_com_admin_destroy()  local
1707 	size = ADMIN_AENQ_SIZE(aenq->q_depth);  in ena_com_admin_destroy()
1708 	if (ena_dev->aenq.entries)  in ena_com_admin_destroy()
1709 		dma_free_coherent(ena_dev->dmadev, size, aenq->entries,  in ena_com_admin_destroy()
1710 				  aenq->dma_addr);  in ena_com_admin_destroy()
1711 	aenq->entries = NULL;  in ena_com_admin_destroy()
2010 	memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,  in ena_com_get_dev_attr_feat()
2011 	       sizeof(get_resp.u.aenq));  in ena_com_get_dev_attr_feat()
2058 	struct ena_aenq_handlers *aenq_handlers = ena_dev->aenq.aenq_handlers;  in ena_com_get_specific_aenq_cb()
2074 	struct ena_com_aenq *aenq  = &ena_dev->aenq;  in ena_com_aenq_intr_handler()  local
2080 	masked_head = aenq->head & (aenq->q_depth - 1);  in ena_com_aenq_intr_handler()
2081 	phase = aenq->phase;  in ena_com_aenq_intr_handler()
2082 	aenq_e = &aenq->entries[masked_head]; /* Get first entry */  in ena_com_aenq_intr_handler()
2109 		if (unlikely(masked_head == aenq->q_depth)) {  in ena_com_aenq_intr_handler()
2113 		aenq_e = &aenq->entries[masked_head];  in ena_com_aenq_intr_handler()
2117 	aenq->head += processed;  in ena_com_aenq_intr_handler()
2118 	aenq->phase = phase;  in ena_com_aenq_intr_handler()
2126 	writel_relaxed((u32)aenq->head,  in ena_com_aenq_intr_handler()