53 	bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,  in bgmac_dma_tx_reset()
71 	bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);  in bgmac_dma_tx_reset()
107 	bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);  in bgmac_dma_tx_enable()
200 	bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,  in bgmac_dma_tx_add()
297 	bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);  in bgmac_dma_rx_reset()
330 	bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);  in bgmac_dma_rx_enable()
372 	bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,  in bgmac_dma_rx_update_index()
510 		bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,  in bgmac_dma_unaligned()
516 		bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,  in bgmac_dma_unaligned()
696 		bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,  in bgmac_dma_init()
698 		bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,  in bgmac_dma_init()
714 		bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,  in bgmac_dma_init()
716 		bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,  in bgmac_dma_init()
1035 	bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);  in bgmac_chip_intrs_on()
1040 	bgmac_write(bgmac, BGMAC_INT_MASK, 0);  in bgmac_chip_intrs_off()
1080 		bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);  in bgmac_enable()
1094 		bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);  in bgmac_enable()
1102 	bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);  in bgmac_chip_init()
1105 	bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);  in bgmac_chip_init()
1154 	bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);  in bgmac_poll()