Lines Matching refs:regs
70 adapter->regs + A_ESPI_CMD_ADDR); in tricn_write()
71 writel(0, adapter->regs + A_ESPI_GOSTAT); in tricn_write()
74 busy = readl(adapter->regs + A_ESPI_GOSTAT) & F_ESPI_CMD_BUSY; in tricn_write()
87 if (!(readl(adapter->regs + A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) { in tricn_init()
92 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET); in tricn_init()
112 adapter->regs + A_ESPI_RX_RESET); in tricn_init()
119 u32 enable, pl_intr = readl(espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_enable()
129 writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_enable()
130 writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_enable()
135 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT); in t1_espi_intr_clear()
136 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_clear()
137 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE); in t1_espi_intr_clear()
142 u32 pl_intr = readl(espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_disable()
144 writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_disable()
145 writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_disable()
150 u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_handler()
169 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT); in t1_espi_intr_handler()
178 writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_handler()
191 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0); in espi_setup_for_pm3393()
192 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN1); in espi_setup_for_pm3393()
193 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2); in espi_setup_for_pm3393()
194 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN3); in espi_setup_for_pm3393()
195 writel(0x100, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_pm3393()
196 writel(wmark, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_pm3393()
197 writel(3, adapter->regs + A_ESPI_CALENDAR_LENGTH); in espi_setup_for_pm3393()
198 writel(0x08000008, adapter->regs + A_ESPI_TRAIN); in espi_setup_for_pm3393()
199 writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG); in espi_setup_for_pm3393()
204 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0); in espi_setup_for_vsc7321()
205 writel(0x1f401f4, adapter->regs + A_ESPI_SCH_TOKEN1); in espi_setup_for_vsc7321()
206 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2); in espi_setup_for_vsc7321()
207 writel(0xa00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_vsc7321()
208 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_vsc7321()
209 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH); in espi_setup_for_vsc7321()
210 writel(V_RX_NPORTS(4) | V_TX_NPORTS(4), adapter->regs + A_PORT_CONFIG); in espi_setup_for_vsc7321()
212 writel(0x08000008, adapter->regs + A_ESPI_TRAIN); in espi_setup_for_vsc7321()
220 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH); in espi_setup_for_ixf1010()
223 writel(0xf00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_ixf1010()
224 writel(0x3c0, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_ixf1010()
226 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_ixf1010()
227 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_ixf1010()
230 writel(0x1fff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_ixf1010()
231 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_ixf1010()
233 writel(V_RX_NPORTS(nports) | V_TX_NPORTS(nports), adapter->regs + A_PORT_CONFIG); in espi_setup_for_ixf1010()
243 writel(0, adapter->regs + A_ESPI_TRAIN); in t1_espi_init()
248 V_DIP4_THRES(1), adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_init()
250 adapter->regs + A_ESPI_MAXBURST1_MAXBURST2); in t1_espi_init()
252 writel(0x800100, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2); in t1_espi_init()
265 adapter->regs + A_ESPI_FIFO_STATUS_ENABLE); in t1_espi_init()
273 espi->misc_ctrl = readl(adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_init()
278 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_init()
309 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
331 adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon()
332 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); in t1_espi_get_mon()
333 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon()
335 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); in t1_espi_get_mon()
359 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon_t204()
364 adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon_t204()
366 *valp = readl(adapter->regs + A_ESPI_SCH_TOKEN3); in t1_espi_get_mon_t204()
369 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon_t204()