788 	if (vsi->tc_cfg.numtc) {  in ice_vsi_setup_q_map()
789 		if (!(vsi->tc_cfg.ena_tc & BIT(0)))  in ice_vsi_setup_q_map()
796 		vsi->tc_cfg.numtc++;  in ice_vsi_setup_q_map()
797 		vsi->tc_cfg.ena_tc |= 1;  in ice_vsi_setup_q_map()
800 	num_rxq_per_tc = min_t(u16, qcount_rx / vsi->tc_cfg.numtc, ICE_MAX_RXQS_PER_TC);  in ice_vsi_setup_q_map()
803 	num_txq_per_tc = qcount_tx / vsi->tc_cfg.numtc;  in ice_vsi_setup_q_map()
822 		if (!(vsi->tc_cfg.ena_tc & BIT(i))) {  in ice_vsi_setup_q_map()
824 			vsi->tc_cfg.tc_info[i].qoffset = 0;  in ice_vsi_setup_q_map()
825 			vsi->tc_cfg.tc_info[i].qcount_rx = 1;  in ice_vsi_setup_q_map()
826 			vsi->tc_cfg.tc_info[i].qcount_tx = 1;  in ice_vsi_setup_q_map()
827 			vsi->tc_cfg.tc_info[i].netdev_tc = 0;  in ice_vsi_setup_q_map()
833 		vsi->tc_cfg.tc_info[i].qoffset = offset;  in ice_vsi_setup_q_map()
834 		vsi->tc_cfg.tc_info[i].qcount_rx = num_rxq_per_tc;  in ice_vsi_setup_q_map()
835 		vsi->tc_cfg.tc_info[i].qcount_tx = num_txq_per_tc;  in ice_vsi_setup_q_map()
836 		vsi->tc_cfg.tc_info[i].netdev_tc = netdev_tc++;  in ice_vsi_setup_q_map()
2195 	vsi->tc_cfg.ena_tc = ice_dcb_get_ena_tc(cfg);  in ice_vsi_set_tc_cfg()
2196 	vsi->tc_cfg.numtc = ice_dcb_get_num_tc(cfg);  in ice_vsi_set_tc_cfg()
2367 				     (u8)vsi->tc_cfg.ena_tc);  in ice_set_agg_vsi()
2380 				     (u8)vsi->tc_cfg.ena_tc);  in ice_set_agg_vsi()
2395 		vsi->idx, vsi->tc_cfg.ena_tc, vsi->agg_node->agg_id,  in ice_set_agg_vsi()
2542 	for (i = 0; i < vsi->tc_cfg.numtc; i++)  in ice_vsi_setup()
2545 	status = ice_cfg_vsi_lan(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc,  in ice_vsi_setup()
3213 	for (i = 0; i < vsi->tc_cfg.numtc; i++) {  in ice_vsi_rebuild()
3220 	status = ice_cfg_vsi_lan(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc,  in ice_vsi_rebuild()
3335 	vsi->tc_cfg.ena_tc = ena_tc;  in ice_vsi_cfg_tc()
3336 	vsi->tc_cfg.numtc = num_tc;  in ice_vsi_cfg_tc()
3356 	status = ice_cfg_vsi_lan(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc,  in ice_vsi_cfg_tc()