Lines Matching refs:hw
13 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
14 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
15 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
16 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
17 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
18 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
20 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
21 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
22 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
23 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
25 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
26 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
27 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
29 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
31 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
33 static s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw);
49 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) in ixgbe_device_supports_autoneg_fc() argument
55 switch (hw->phy.media_type) { in ixgbe_device_supports_autoneg_fc()
58 switch (hw->device_id) { in ixgbe_device_supports_autoneg_fc()
64 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_device_supports_autoneg_fc()
74 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) in ixgbe_device_supports_autoneg_fc()
81 switch (hw->device_id) { in ixgbe_device_supports_autoneg_fc()
102 hw_dbg(hw, "Device %x does not support flow control autoneg\n", in ixgbe_device_supports_autoneg_fc()
103 hw->device_id); in ixgbe_device_supports_autoneg_fc()
114 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) in ixgbe_setup_fc_generic() argument
125 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { in ixgbe_setup_fc_generic()
126 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); in ixgbe_setup_fc_generic()
134 if (hw->fc.requested_mode == ixgbe_fc_default) in ixgbe_setup_fc_generic()
135 hw->fc.requested_mode = ixgbe_fc_full; in ixgbe_setup_fc_generic()
142 switch (hw->phy.media_type) { in ixgbe_setup_fc_generic()
145 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); in ixgbe_setup_fc_generic()
151 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); in ixgbe_setup_fc_generic()
155 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_setup_fc_generic()
172 switch (hw->fc.requested_mode) { in ixgbe_setup_fc_generic()
176 if (hw->phy.media_type == ixgbe_media_type_backplane) in ixgbe_setup_fc_generic()
179 else if (hw->phy.media_type == ixgbe_media_type_copper) in ixgbe_setup_fc_generic()
189 if (hw->phy.media_type == ixgbe_media_type_backplane) { in ixgbe_setup_fc_generic()
192 } else if (hw->phy.media_type == ixgbe_media_type_copper) { in ixgbe_setup_fc_generic()
210 if (hw->phy.media_type == ixgbe_media_type_backplane) in ixgbe_setup_fc_generic()
213 else if (hw->phy.media_type == ixgbe_media_type_copper) in ixgbe_setup_fc_generic()
217 hw_dbg(hw, "Flow control param set incorrectly\n"); in ixgbe_setup_fc_generic()
221 if (hw->mac.type != ixgbe_mac_X540) { in ixgbe_setup_fc_generic()
226 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); in ixgbe_setup_fc_generic()
227 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); in ixgbe_setup_fc_generic()
230 if (hw->fc.strict_ieee) in ixgbe_setup_fc_generic()
233 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); in ixgbe_setup_fc_generic()
234 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); in ixgbe_setup_fc_generic()
242 if (hw->phy.media_type == ixgbe_media_type_backplane) { in ixgbe_setup_fc_generic()
247 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); in ixgbe_setup_fc_generic()
251 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && in ixgbe_setup_fc_generic()
252 ixgbe_device_supports_autoneg_fc(hw)) { in ixgbe_setup_fc_generic()
253 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_setup_fc_generic()
257 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); in ixgbe_setup_fc_generic()
270 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) in ixgbe_start_hw_generic() argument
277 hw->phy.media_type = hw->mac.ops.get_media_type(hw); in ixgbe_start_hw_generic()
280 hw->phy.ops.identify(hw); in ixgbe_start_hw_generic()
283 hw->mac.ops.clear_vfta(hw); in ixgbe_start_hw_generic()
286 hw->mac.ops.clear_hw_cntrs(hw); in ixgbe_start_hw_generic()
289 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); in ixgbe_start_hw_generic()
291 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); in ixgbe_start_hw_generic()
292 IXGBE_WRITE_FLUSH(hw); in ixgbe_start_hw_generic()
295 if (hw->mac.ops.setup_fc) { in ixgbe_start_hw_generic()
296 ret_val = hw->mac.ops.setup_fc(hw); in ixgbe_start_hw_generic()
302 switch (hw->mac.type) { in ixgbe_start_hw_generic()
306 hw->mac.ops.get_device_caps(hw, &device_caps); in ixgbe_start_hw_generic()
308 hw->need_crosstalk_fix = false; in ixgbe_start_hw_generic()
310 hw->need_crosstalk_fix = true; in ixgbe_start_hw_generic()
313 hw->need_crosstalk_fix = false; in ixgbe_start_hw_generic()
318 hw->adapter_stopped = false; in ixgbe_start_hw_generic()
333 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) in ixgbe_start_hw_gen2() argument
338 for (i = 0; i < hw->mac.max_tx_queues; i++) { in ixgbe_start_hw_gen2()
339 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); in ixgbe_start_hw_gen2()
340 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); in ixgbe_start_hw_gen2()
342 IXGBE_WRITE_FLUSH(hw); in ixgbe_start_hw_gen2()
357 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) in ixgbe_init_hw_generic() argument
362 status = hw->mac.ops.reset_hw(hw); in ixgbe_init_hw_generic()
366 status = hw->mac.ops.start_hw(hw); in ixgbe_init_hw_generic()
370 if (hw->mac.ops.init_led_link_act) in ixgbe_init_hw_generic()
371 hw->mac.ops.init_led_link_act(hw); in ixgbe_init_hw_generic()
383 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) in ixgbe_clear_hw_cntrs_generic() argument
387 IXGBE_READ_REG(hw, IXGBE_CRCERRS); in ixgbe_clear_hw_cntrs_generic()
388 IXGBE_READ_REG(hw, IXGBE_ILLERRC); in ixgbe_clear_hw_cntrs_generic()
389 IXGBE_READ_REG(hw, IXGBE_ERRBC); in ixgbe_clear_hw_cntrs_generic()
390 IXGBE_READ_REG(hw, IXGBE_MSPDC); in ixgbe_clear_hw_cntrs_generic()
392 IXGBE_READ_REG(hw, IXGBE_MPC(i)); in ixgbe_clear_hw_cntrs_generic()
394 IXGBE_READ_REG(hw, IXGBE_MLFC); in ixgbe_clear_hw_cntrs_generic()
395 IXGBE_READ_REG(hw, IXGBE_MRFC); in ixgbe_clear_hw_cntrs_generic()
396 IXGBE_READ_REG(hw, IXGBE_RLEC); in ixgbe_clear_hw_cntrs_generic()
397 IXGBE_READ_REG(hw, IXGBE_LXONTXC); in ixgbe_clear_hw_cntrs_generic()
398 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); in ixgbe_clear_hw_cntrs_generic()
399 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
400 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); in ixgbe_clear_hw_cntrs_generic()
401 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); in ixgbe_clear_hw_cntrs_generic()
403 IXGBE_READ_REG(hw, IXGBE_LXONRXC); in ixgbe_clear_hw_cntrs_generic()
404 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); in ixgbe_clear_hw_cntrs_generic()
408 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); in ixgbe_clear_hw_cntrs_generic()
409 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); in ixgbe_clear_hw_cntrs_generic()
410 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
411 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); in ixgbe_clear_hw_cntrs_generic()
412 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); in ixgbe_clear_hw_cntrs_generic()
414 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); in ixgbe_clear_hw_cntrs_generic()
415 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); in ixgbe_clear_hw_cntrs_generic()
418 if (hw->mac.type >= ixgbe_mac_82599EB) in ixgbe_clear_hw_cntrs_generic()
420 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); in ixgbe_clear_hw_cntrs_generic()
421 IXGBE_READ_REG(hw, IXGBE_PRC64); in ixgbe_clear_hw_cntrs_generic()
422 IXGBE_READ_REG(hw, IXGBE_PRC127); in ixgbe_clear_hw_cntrs_generic()
423 IXGBE_READ_REG(hw, IXGBE_PRC255); in ixgbe_clear_hw_cntrs_generic()
424 IXGBE_READ_REG(hw, IXGBE_PRC511); in ixgbe_clear_hw_cntrs_generic()
425 IXGBE_READ_REG(hw, IXGBE_PRC1023); in ixgbe_clear_hw_cntrs_generic()
426 IXGBE_READ_REG(hw, IXGBE_PRC1522); in ixgbe_clear_hw_cntrs_generic()
427 IXGBE_READ_REG(hw, IXGBE_GPRC); in ixgbe_clear_hw_cntrs_generic()
428 IXGBE_READ_REG(hw, IXGBE_BPRC); in ixgbe_clear_hw_cntrs_generic()
429 IXGBE_READ_REG(hw, IXGBE_MPRC); in ixgbe_clear_hw_cntrs_generic()
430 IXGBE_READ_REG(hw, IXGBE_GPTC); in ixgbe_clear_hw_cntrs_generic()
431 IXGBE_READ_REG(hw, IXGBE_GORCL); in ixgbe_clear_hw_cntrs_generic()
432 IXGBE_READ_REG(hw, IXGBE_GORCH); in ixgbe_clear_hw_cntrs_generic()
433 IXGBE_READ_REG(hw, IXGBE_GOTCL); in ixgbe_clear_hw_cntrs_generic()
434 IXGBE_READ_REG(hw, IXGBE_GOTCH); in ixgbe_clear_hw_cntrs_generic()
435 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_clear_hw_cntrs_generic()
437 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); in ixgbe_clear_hw_cntrs_generic()
438 IXGBE_READ_REG(hw, IXGBE_RUC); in ixgbe_clear_hw_cntrs_generic()
439 IXGBE_READ_REG(hw, IXGBE_RFC); in ixgbe_clear_hw_cntrs_generic()
440 IXGBE_READ_REG(hw, IXGBE_ROC); in ixgbe_clear_hw_cntrs_generic()
441 IXGBE_READ_REG(hw, IXGBE_RJC); in ixgbe_clear_hw_cntrs_generic()
442 IXGBE_READ_REG(hw, IXGBE_MNGPRC); in ixgbe_clear_hw_cntrs_generic()
443 IXGBE_READ_REG(hw, IXGBE_MNGPDC); in ixgbe_clear_hw_cntrs_generic()
444 IXGBE_READ_REG(hw, IXGBE_MNGPTC); in ixgbe_clear_hw_cntrs_generic()
445 IXGBE_READ_REG(hw, IXGBE_TORL); in ixgbe_clear_hw_cntrs_generic()
446 IXGBE_READ_REG(hw, IXGBE_TORH); in ixgbe_clear_hw_cntrs_generic()
447 IXGBE_READ_REG(hw, IXGBE_TPR); in ixgbe_clear_hw_cntrs_generic()
448 IXGBE_READ_REG(hw, IXGBE_TPT); in ixgbe_clear_hw_cntrs_generic()
449 IXGBE_READ_REG(hw, IXGBE_PTC64); in ixgbe_clear_hw_cntrs_generic()
450 IXGBE_READ_REG(hw, IXGBE_PTC127); in ixgbe_clear_hw_cntrs_generic()
451 IXGBE_READ_REG(hw, IXGBE_PTC255); in ixgbe_clear_hw_cntrs_generic()
452 IXGBE_READ_REG(hw, IXGBE_PTC511); in ixgbe_clear_hw_cntrs_generic()
453 IXGBE_READ_REG(hw, IXGBE_PTC1023); in ixgbe_clear_hw_cntrs_generic()
454 IXGBE_READ_REG(hw, IXGBE_PTC1522); in ixgbe_clear_hw_cntrs_generic()
455 IXGBE_READ_REG(hw, IXGBE_MPTC); in ixgbe_clear_hw_cntrs_generic()
456 IXGBE_READ_REG(hw, IXGBE_BPTC); in ixgbe_clear_hw_cntrs_generic()
458 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); in ixgbe_clear_hw_cntrs_generic()
459 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); in ixgbe_clear_hw_cntrs_generic()
460 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
461 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); in ixgbe_clear_hw_cntrs_generic()
462 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); in ixgbe_clear_hw_cntrs_generic()
463 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); in ixgbe_clear_hw_cntrs_generic()
464 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); in ixgbe_clear_hw_cntrs_generic()
465 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); in ixgbe_clear_hw_cntrs_generic()
467 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); in ixgbe_clear_hw_cntrs_generic()
468 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); in ixgbe_clear_hw_cntrs_generic()
472 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { in ixgbe_clear_hw_cntrs_generic()
473 if (hw->phy.id == 0) in ixgbe_clear_hw_cntrs_generic()
474 hw->phy.ops.identify(hw); in ixgbe_clear_hw_cntrs_generic()
475 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
476 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
477 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
478 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i); in ixgbe_clear_hw_cntrs_generic()
492 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, in ixgbe_read_pba_string_generic() argument
502 hw_dbg(hw, "PBA string buffer was null\n"); in ixgbe_read_pba_string_generic()
506 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); in ixgbe_read_pba_string_generic()
508 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
512 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); in ixgbe_read_pba_string_generic()
514 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
524 hw_dbg(hw, "NVM PBA number is not stored as string\n"); in ixgbe_read_pba_string_generic()
528 hw_dbg(hw, "PBA string buffer too small\n"); in ixgbe_read_pba_string_generic()
558 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); in ixgbe_read_pba_string_generic()
560 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
565 hw_dbg(hw, "NVM PBA number section invalid length\n"); in ixgbe_read_pba_string_generic()
571 hw_dbg(hw, "PBA string buffer too small\n"); in ixgbe_read_pba_string_generic()
580 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); in ixgbe_read_pba_string_generic()
582 hw_dbg(hw, "NVM Read Error\n"); in ixgbe_read_pba_string_generic()
602 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) in ixgbe_get_mac_addr_generic() argument
608 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); in ixgbe_get_mac_addr_generic()
609 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); in ixgbe_get_mac_addr_generic()
656 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) in ixgbe_get_bus_info_generic() argument
660 hw->bus.type = ixgbe_bus_type_pci_express; in ixgbe_get_bus_info_generic()
663 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS); in ixgbe_get_bus_info_generic()
665 hw->bus.width = ixgbe_convert_bus_width(link_status); in ixgbe_get_bus_info_generic()
666 hw->bus.speed = ixgbe_convert_bus_speed(link_status); in ixgbe_get_bus_info_generic()
668 hw->mac.ops.set_lan_id(hw); in ixgbe_get_bus_info_generic()
680 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) in ixgbe_set_lan_id_multi_port_pcie() argument
682 struct ixgbe_bus_info *bus = &hw->bus; in ixgbe_set_lan_id_multi_port_pcie()
686 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); in ixgbe_set_lan_id_multi_port_pcie()
691 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); in ixgbe_set_lan_id_multi_port_pcie()
696 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { in ixgbe_set_lan_id_multi_port_pcie()
697 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); in ixgbe_set_lan_id_multi_port_pcie()
712 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) in ixgbe_stop_adapter_generic() argument
721 hw->adapter_stopped = true; in ixgbe_stop_adapter_generic()
724 hw->mac.ops.disable_rx(hw); in ixgbe_stop_adapter_generic()
727 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); in ixgbe_stop_adapter_generic()
730 IXGBE_READ_REG(hw, IXGBE_EICR); in ixgbe_stop_adapter_generic()
733 for (i = 0; i < hw->mac.max_tx_queues; i++) in ixgbe_stop_adapter_generic()
734 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); in ixgbe_stop_adapter_generic()
737 for (i = 0; i < hw->mac.max_rx_queues; i++) { in ixgbe_stop_adapter_generic()
738 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); in ixgbe_stop_adapter_generic()
741 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); in ixgbe_stop_adapter_generic()
745 IXGBE_WRITE_FLUSH(hw); in ixgbe_stop_adapter_generic()
752 return ixgbe_disable_pcie_primary(hw); in ixgbe_stop_adapter_generic()
762 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) in ixgbe_init_led_link_act_generic() argument
764 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_led_link_act_generic()
768 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_init_led_link_act_generic()
784 switch (hw->mac.type) { in ixgbe_init_led_link_act_generic()
803 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_led_on_generic() argument
805 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_led_on_generic()
813 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_led_on_generic()
814 IXGBE_WRITE_FLUSH(hw); in ixgbe_led_on_generic()
824 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_led_off_generic() argument
826 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_led_off_generic()
834 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_led_off_generic()
835 IXGBE_WRITE_FLUSH(hw); in ixgbe_led_off_generic()
847 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) in ixgbe_init_eeprom_params_generic() argument
849 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_init_eeprom_params_generic()
865 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_init_eeprom_params_generic()
883 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n", in ixgbe_init_eeprom_params_generic()
899 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eeprom_buffer_bit_bang_generic() argument
905 hw->eeprom.ops.init_params(hw); in ixgbe_write_eeprom_buffer_bit_bang_generic()
907 if (words == 0 || (offset + words > hw->eeprom.word_size)) in ixgbe_write_eeprom_buffer_bit_bang_generic()
914 if ((hw->eeprom.word_page_size == 0) && in ixgbe_write_eeprom_buffer_bit_bang_generic()
916 ixgbe_detect_eeprom_page_size_generic(hw, offset); in ixgbe_write_eeprom_buffer_bit_bang_generic()
926 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, in ixgbe_write_eeprom_buffer_bit_bang_generic()
946 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eeprom_buffer_bit_bang() argument
956 status = ixgbe_acquire_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
960 if (ixgbe_ready_eeprom(hw) != 0) { in ixgbe_write_eeprom_buffer_bit_bang()
961 ixgbe_release_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
966 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
969 ixgbe_shift_out_eeprom_bits(hw, in ixgbe_write_eeprom_buffer_bit_bang()
973 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
978 if ((hw->eeprom.address_bits == 8) && in ixgbe_write_eeprom_buffer_bit_bang()
983 ixgbe_shift_out_eeprom_bits(hw, write_opcode, in ixgbe_write_eeprom_buffer_bit_bang()
985 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), in ixgbe_write_eeprom_buffer_bit_bang()
986 hw->eeprom.address_bits); in ixgbe_write_eeprom_buffer_bit_bang()
988 page_size = hw->eeprom.word_page_size; in ixgbe_write_eeprom_buffer_bit_bang()
994 ixgbe_shift_out_eeprom_bits(hw, word, 16); in ixgbe_write_eeprom_buffer_bit_bang()
1005 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
1009 ixgbe_release_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
1023 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) in ixgbe_write_eeprom_generic() argument
1025 hw->eeprom.ops.init_params(hw); in ixgbe_write_eeprom_generic()
1027 if (offset >= hw->eeprom.word_size) in ixgbe_write_eeprom_generic()
1030 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); in ixgbe_write_eeprom_generic()
1042 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_buffer_bit_bang_generic() argument
1048 hw->eeprom.ops.init_params(hw); in ixgbe_read_eeprom_buffer_bit_bang_generic()
1050 if (words == 0 || (offset + words > hw->eeprom.word_size)) in ixgbe_read_eeprom_buffer_bit_bang_generic()
1062 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, in ixgbe_read_eeprom_buffer_bit_bang_generic()
1081 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_buffer_bit_bang() argument
1090 status = ixgbe_acquire_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1094 if (ixgbe_ready_eeprom(hw) != 0) { in ixgbe_read_eeprom_buffer_bit_bang()
1095 ixgbe_release_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1100 ixgbe_standby_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1104 if ((hw->eeprom.address_bits == 8) && in ixgbe_read_eeprom_buffer_bit_bang()
1109 ixgbe_shift_out_eeprom_bits(hw, read_opcode, in ixgbe_read_eeprom_buffer_bit_bang()
1111 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), in ixgbe_read_eeprom_buffer_bit_bang()
1112 hw->eeprom.address_bits); in ixgbe_read_eeprom_buffer_bit_bang()
1115 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); in ixgbe_read_eeprom_buffer_bit_bang()
1120 ixgbe_release_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1133 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_bit_bang_generic() argument
1136 hw->eeprom.ops.init_params(hw); in ixgbe_read_eeprom_bit_bang_generic()
1138 if (offset >= hw->eeprom.word_size) in ixgbe_read_eeprom_bit_bang_generic()
1141 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); in ixgbe_read_eeprom_bit_bang_generic()
1153 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eerd_buffer_generic() argument
1160 hw->eeprom.ops.init_params(hw); in ixgbe_read_eerd_buffer_generic()
1162 if (words == 0 || offset >= hw->eeprom.word_size) in ixgbe_read_eerd_buffer_generic()
1169 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); in ixgbe_read_eerd_buffer_generic()
1170 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); in ixgbe_read_eerd_buffer_generic()
1173 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> in ixgbe_read_eerd_buffer_generic()
1176 hw_dbg(hw, "Eeprom read timed out\n"); in ixgbe_read_eerd_buffer_generic()
1193 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, in ixgbe_detect_eeprom_page_size_generic() argument
1203 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; in ixgbe_detect_eeprom_page_size_generic()
1204 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, in ixgbe_detect_eeprom_page_size_generic()
1206 hw->eeprom.word_page_size = 0; in ixgbe_detect_eeprom_page_size_generic()
1210 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); in ixgbe_detect_eeprom_page_size_generic()
1218 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; in ixgbe_detect_eeprom_page_size_generic()
1220 hw_dbg(hw, "Detected EEPROM page size = %d words.\n", in ixgbe_detect_eeprom_page_size_generic()
1221 hw->eeprom.word_page_size); in ixgbe_detect_eeprom_page_size_generic()
1233 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) in ixgbe_read_eerd_generic() argument
1235 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); in ixgbe_read_eerd_generic()
1247 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eewr_buffer_generic() argument
1254 hw->eeprom.ops.init_params(hw); in ixgbe_write_eewr_buffer_generic()
1256 if (words == 0 || offset >= hw->eeprom.word_size) in ixgbe_write_eewr_buffer_generic()
1264 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); in ixgbe_write_eewr_buffer_generic()
1266 hw_dbg(hw, "Eeprom write EEWR timed out\n"); in ixgbe_write_eewr_buffer_generic()
1270 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); in ixgbe_write_eewr_buffer_generic()
1272 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); in ixgbe_write_eewr_buffer_generic()
1274 hw_dbg(hw, "Eeprom write EEWR timed out\n"); in ixgbe_write_eewr_buffer_generic()
1290 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) in ixgbe_write_eewr_generic() argument
1292 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); in ixgbe_write_eewr_generic()
1303 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) in ixgbe_poll_eerd_eewr_done() argument
1310 reg = IXGBE_READ_REG(hw, IXGBE_EERD); in ixgbe_poll_eerd_eewr_done()
1312 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); in ixgbe_poll_eerd_eewr_done()
1329 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) in ixgbe_acquire_eeprom() argument
1334 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) in ixgbe_acquire_eeprom()
1337 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_acquire_eeprom()
1341 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_acquire_eeprom()
1344 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_acquire_eeprom()
1353 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_acquire_eeprom()
1354 hw_dbg(hw, "Could not acquire EEPROM grant\n"); in ixgbe_acquire_eeprom()
1356 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); in ixgbe_acquire_eeprom()
1363 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_acquire_eeprom()
1364 IXGBE_WRITE_FLUSH(hw); in ixgbe_acquire_eeprom()
1375 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) in ixgbe_get_eeprom_semaphore() argument
1387 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1394 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n"); in ixgbe_get_eeprom_semaphore()
1400 ixgbe_release_eeprom_semaphore(hw); in ixgbe_get_eeprom_semaphore()
1407 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1409 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n"); in ixgbe_get_eeprom_semaphore()
1416 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1420 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); in ixgbe_get_eeprom_semaphore()
1425 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_get_eeprom_semaphore()
1436 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n"); in ixgbe_get_eeprom_semaphore()
1437 ixgbe_release_eeprom_semaphore(hw); in ixgbe_get_eeprom_semaphore()
1450 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) in ixgbe_release_eeprom_semaphore() argument
1454 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); in ixgbe_release_eeprom_semaphore()
1458 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); in ixgbe_release_eeprom_semaphore()
1459 IXGBE_WRITE_FLUSH(hw); in ixgbe_release_eeprom_semaphore()
1466 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) in ixgbe_ready_eeprom() argument
1478 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, in ixgbe_ready_eeprom()
1480 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); in ixgbe_ready_eeprom()
1485 ixgbe_standby_eeprom(hw); in ixgbe_ready_eeprom()
1493 hw_dbg(hw, "SPI EEPROM Status error\n"); in ixgbe_ready_eeprom()
1504 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) in ixgbe_standby_eeprom() argument
1508 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_standby_eeprom()
1512 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_standby_eeprom()
1513 IXGBE_WRITE_FLUSH(hw); in ixgbe_standby_eeprom()
1516 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_standby_eeprom()
1517 IXGBE_WRITE_FLUSH(hw); in ixgbe_standby_eeprom()
1527 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, in ixgbe_shift_out_eeprom_bits() argument
1534 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_shift_out_eeprom_bits()
1555 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_shift_out_eeprom_bits()
1556 IXGBE_WRITE_FLUSH(hw); in ixgbe_shift_out_eeprom_bits()
1560 ixgbe_raise_eeprom_clk(hw, &eec); in ixgbe_shift_out_eeprom_bits()
1561 ixgbe_lower_eeprom_clk(hw, &eec); in ixgbe_shift_out_eeprom_bits()
1572 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_shift_out_eeprom_bits()
1573 IXGBE_WRITE_FLUSH(hw); in ixgbe_shift_out_eeprom_bits()
1581 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) in ixgbe_shift_in_eeprom_bits() argument
1594 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_shift_in_eeprom_bits()
1600 ixgbe_raise_eeprom_clk(hw, &eec); in ixgbe_shift_in_eeprom_bits()
1602 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_shift_in_eeprom_bits()
1608 ixgbe_lower_eeprom_clk(hw, &eec); in ixgbe_shift_in_eeprom_bits()
1619 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) in ixgbe_raise_eeprom_clk() argument
1626 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); in ixgbe_raise_eeprom_clk()
1627 IXGBE_WRITE_FLUSH(hw); in ixgbe_raise_eeprom_clk()
1636 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) in ixgbe_lower_eeprom_clk() argument
1643 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); in ixgbe_lower_eeprom_clk()
1644 IXGBE_WRITE_FLUSH(hw); in ixgbe_lower_eeprom_clk()
1652 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) in ixgbe_release_eeprom() argument
1656 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); in ixgbe_release_eeprom()
1661 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_release_eeprom()
1662 IXGBE_WRITE_FLUSH(hw); in ixgbe_release_eeprom()
1668 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); in ixgbe_release_eeprom()
1670 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); in ixgbe_release_eeprom()
1676 usleep_range(hw->eeprom.semaphore_delay * 1000, in ixgbe_release_eeprom()
1677 hw->eeprom.semaphore_delay * 2000); in ixgbe_release_eeprom()
1684 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) in ixgbe_calc_eeprom_checksum_generic() argument
1695 if (hw->eeprom.ops.read(hw, i, &word)) { in ixgbe_calc_eeprom_checksum_generic()
1696 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1704 if (hw->eeprom.ops.read(hw, i, &pointer)) { in ixgbe_calc_eeprom_checksum_generic()
1705 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1713 if (hw->eeprom.ops.read(hw, pointer, &length)) { in ixgbe_calc_eeprom_checksum_generic()
1714 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1722 if (hw->eeprom.ops.read(hw, j, &word)) { in ixgbe_calc_eeprom_checksum_generic()
1723 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_calc_eeprom_checksum_generic()
1743 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, in ixgbe_validate_eeprom_checksum_generic() argument
1755 status = hw->eeprom.ops.read(hw, 0, &checksum); in ixgbe_validate_eeprom_checksum_generic()
1757 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_validate_eeprom_checksum_generic()
1761 status = hw->eeprom.ops.calc_checksum(hw); in ixgbe_validate_eeprom_checksum_generic()
1767 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); in ixgbe_validate_eeprom_checksum_generic()
1769 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_validate_eeprom_checksum_generic()
1790 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) in ixgbe_update_eeprom_checksum_generic() argument
1800 status = hw->eeprom.ops.read(hw, 0, &checksum); in ixgbe_update_eeprom_checksum_generic()
1802 hw_dbg(hw, "EEPROM read failed\n"); in ixgbe_update_eeprom_checksum_generic()
1806 status = hw->eeprom.ops.calc_checksum(hw); in ixgbe_update_eeprom_checksum_generic()
1812 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); in ixgbe_update_eeprom_checksum_generic()
1827 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, in ixgbe_set_rar_generic() argument
1831 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_set_rar_generic()
1835 hw_dbg(hw, "RAR index %d is out of range.\n", index); in ixgbe_set_rar_generic()
1840 hw->mac.ops.set_vmdq(hw, index, vmdq); in ixgbe_set_rar_generic()
1855 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); in ixgbe_set_rar_generic()
1866 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); in ixgbe_set_rar_generic()
1867 IXGBE_WRITE_FLUSH(hw); in ixgbe_set_rar_generic()
1868 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); in ixgbe_set_rar_generic()
1880 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_clear_rar_generic() argument
1883 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_clear_rar_generic()
1887 hw_dbg(hw, "RAR index %d is out of range.\n", index); in ixgbe_clear_rar_generic()
1896 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); in ixgbe_clear_rar_generic()
1903 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); in ixgbe_clear_rar_generic()
1904 IXGBE_WRITE_FLUSH(hw); in ixgbe_clear_rar_generic()
1905 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); in ixgbe_clear_rar_generic()
1908 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); in ixgbe_clear_rar_generic()
1921 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) in ixgbe_init_rx_addrs_generic() argument
1924 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_init_rx_addrs_generic()
1931 if (!is_valid_ether_addr(hw->mac.addr)) { in ixgbe_init_rx_addrs_generic()
1933 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); in ixgbe_init_rx_addrs_generic()
1935 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr); in ixgbe_init_rx_addrs_generic()
1938 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); in ixgbe_init_rx_addrs_generic()
1939 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr); in ixgbe_init_rx_addrs_generic()
1941 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); in ixgbe_init_rx_addrs_generic()
1945 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); in ixgbe_init_rx_addrs_generic()
1947 hw->addr_ctrl.overflow_promisc = 0; in ixgbe_init_rx_addrs_generic()
1949 hw->addr_ctrl.rar_used_count = 1; in ixgbe_init_rx_addrs_generic()
1952 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); in ixgbe_init_rx_addrs_generic()
1954 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); in ixgbe_init_rx_addrs_generic()
1955 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); in ixgbe_init_rx_addrs_generic()
1959 hw->addr_ctrl.mta_in_use = 0; in ixgbe_init_rx_addrs_generic()
1960 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); in ixgbe_init_rx_addrs_generic()
1962 hw_dbg(hw, " Clearing MTA\n"); in ixgbe_init_rx_addrs_generic()
1963 for (i = 0; i < hw->mac.mcft_size; i++) in ixgbe_init_rx_addrs_generic()
1964 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); in ixgbe_init_rx_addrs_generic()
1966 if (hw->mac.ops.init_uta_tables) in ixgbe_init_rx_addrs_generic()
1967 hw->mac.ops.init_uta_tables(hw); in ixgbe_init_rx_addrs_generic()
1984 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) in ixgbe_mta_vector() argument
1988 switch (hw->mac.mc_filter_type) { in ixgbe_mta_vector()
2002 hw_dbg(hw, "MC filter type param set incorrectly\n"); in ixgbe_mta_vector()
2018 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) in ixgbe_set_mta() argument
2024 hw->addr_ctrl.mta_in_use++; in ixgbe_set_mta()
2026 vector = ixgbe_mta_vector(hw, mc_addr); in ixgbe_set_mta()
2027 hw_dbg(hw, " bit-vector = 0x%03X\n", vector); in ixgbe_set_mta()
2040 hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit); in ixgbe_set_mta()
2053 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, in ixgbe_update_mc_addr_list_generic() argument
2063 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); in ixgbe_update_mc_addr_list_generic()
2064 hw->addr_ctrl.mta_in_use = 0; in ixgbe_update_mc_addr_list_generic()
2067 hw_dbg(hw, " Clearing MTA\n"); in ixgbe_update_mc_addr_list_generic()
2068 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); in ixgbe_update_mc_addr_list_generic()
2072 hw_dbg(hw, " Adding the multicast addresses:\n"); in ixgbe_update_mc_addr_list_generic()
2073 ixgbe_set_mta(hw, ha->addr); in ixgbe_update_mc_addr_list_generic()
2077 for (i = 0; i < hw->mac.mcft_size; i++) in ixgbe_update_mc_addr_list_generic()
2078 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, in ixgbe_update_mc_addr_list_generic()
2079 hw->mac.mta_shadow[i]); in ixgbe_update_mc_addr_list_generic()
2081 if (hw->addr_ctrl.mta_in_use > 0) in ixgbe_update_mc_addr_list_generic()
2082 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, in ixgbe_update_mc_addr_list_generic()
2083 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); in ixgbe_update_mc_addr_list_generic()
2085 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); in ixgbe_update_mc_addr_list_generic()
2095 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) in ixgbe_enable_mc_generic() argument
2097 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; in ixgbe_enable_mc_generic()
2100 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | in ixgbe_enable_mc_generic()
2101 hw->mac.mc_filter_type); in ixgbe_enable_mc_generic()
2112 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) in ixgbe_disable_mc_generic() argument
2114 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; in ixgbe_disable_mc_generic()
2117 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); in ixgbe_disable_mc_generic()
2128 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) in ixgbe_fc_enable_generic() argument
2136 if (!hw->fc.pause_time) in ixgbe_fc_enable_generic()
2141 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && in ixgbe_fc_enable_generic()
2142 hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2143 if (!hw->fc.low_water[i] || in ixgbe_fc_enable_generic()
2144 hw->fc.low_water[i] >= hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2145 hw_dbg(hw, "Invalid water mark configuration\n"); in ixgbe_fc_enable_generic()
2152 hw->mac.ops.fc_autoneg(hw); in ixgbe_fc_enable_generic()
2155 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); in ixgbe_fc_enable_generic()
2158 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); in ixgbe_fc_enable_generic()
2171 switch (hw->fc.current_mode) { in ixgbe_fc_enable_generic()
2202 hw_dbg(hw, "Flow control param set incorrectly\n"); in ixgbe_fc_enable_generic()
2208 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); in ixgbe_fc_enable_generic()
2209 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); in ixgbe_fc_enable_generic()
2213 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && in ixgbe_fc_enable_generic()
2214 hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2215 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; in ixgbe_fc_enable_generic()
2216 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); in ixgbe_fc_enable_generic()
2217 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_fc_enable_generic()
2219 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); in ixgbe_fc_enable_generic()
2227 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; in ixgbe_fc_enable_generic()
2230 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); in ixgbe_fc_enable_generic()
2234 reg = hw->fc.pause_time * 0x00010001U; in ixgbe_fc_enable_generic()
2236 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); in ixgbe_fc_enable_generic()
2238 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); in ixgbe_fc_enable_generic()
2256 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, in ixgbe_negotiate_fc() argument
2270 if (hw->fc.requested_mode == ixgbe_fc_full) { in ixgbe_negotiate_fc()
2271 hw->fc.current_mode = ixgbe_fc_full; in ixgbe_negotiate_fc()
2272 hw_dbg(hw, "Flow Control = FULL.\n"); in ixgbe_negotiate_fc()
2274 hw->fc.current_mode = ixgbe_fc_rx_pause; in ixgbe_negotiate_fc()
2275 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n"); in ixgbe_negotiate_fc()
2279 hw->fc.current_mode = ixgbe_fc_tx_pause; in ixgbe_negotiate_fc()
2280 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); in ixgbe_negotiate_fc()
2283 hw->fc.current_mode = ixgbe_fc_rx_pause; in ixgbe_negotiate_fc()
2284 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); in ixgbe_negotiate_fc()
2286 hw->fc.current_mode = ixgbe_fc_none; in ixgbe_negotiate_fc()
2287 hw_dbg(hw, "Flow Control = NONE.\n"); in ixgbe_negotiate_fc()
2298 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_fiber() argument
2309 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); in ixgbe_fc_autoneg_fiber()
2314 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); in ixgbe_fc_autoneg_fiber()
2315 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); in ixgbe_fc_autoneg_fiber()
2317 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, in ixgbe_fc_autoneg_fiber()
2332 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_backplane() argument
2342 links = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_fc_autoneg_backplane()
2346 if (hw->mac.type == ixgbe_mac_82599EB) { in ixgbe_fc_autoneg_backplane()
2347 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); in ixgbe_fc_autoneg_backplane()
2355 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_fc_autoneg_backplane()
2356 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); in ixgbe_fc_autoneg_backplane()
2358 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, in ixgbe_fc_autoneg_backplane()
2371 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_copper() argument
2376 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, in ixgbe_fc_autoneg_copper()
2379 hw->phy.ops.read_reg(hw, MDIO_AN_LPA, in ixgbe_fc_autoneg_copper()
2383 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, in ixgbe_fc_autoneg_copper()
2396 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) in ixgbe_fc_autoneg() argument
2411 if (hw->fc.disable_fc_autoneg) in ixgbe_fc_autoneg()
2414 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_fc_autoneg()
2418 switch (hw->phy.media_type) { in ixgbe_fc_autoneg()
2422 ret_val = ixgbe_fc_autoneg_fiber(hw); in ixgbe_fc_autoneg()
2427 ret_val = ixgbe_fc_autoneg_backplane(hw); in ixgbe_fc_autoneg()
2432 if (ixgbe_device_supports_autoneg_fc(hw)) in ixgbe_fc_autoneg()
2433 ret_val = ixgbe_fc_autoneg_copper(hw); in ixgbe_fc_autoneg()
2442 hw->fc.fc_was_autonegged = true; in ixgbe_fc_autoneg()
2444 hw->fc.fc_was_autonegged = false; in ixgbe_fc_autoneg()
2445 hw->fc.current_mode = hw->fc.requested_mode; in ixgbe_fc_autoneg()
2459 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) in ixgbe_pcie_timeout_poll() argument
2464 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); in ixgbe_pcie_timeout_poll()
2505 static s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw) in ixgbe_disable_pcie_primary() argument
2511 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); in ixgbe_disable_pcie_primary()
2515 if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS) in ixgbe_disable_pcie_primary()
2520 hw_dbg(hw, "GIO disable did not set - requesting resets\n"); in ixgbe_disable_pcie_primary()
2525 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || in ixgbe_disable_pcie_primary()
2526 ixgbe_removed(hw->hw_addr)) in ixgbe_disable_pcie_primary()
2532 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) in ixgbe_disable_pcie_primary()
2544 hw_dbg(hw, "GIO Primary Disable bit didn't clear - requesting resets\n"); in ixgbe_disable_pcie_primary()
2546 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; in ixgbe_disable_pcie_primary()
2548 if (hw->mac.type >= ixgbe_mac_X550) in ixgbe_disable_pcie_primary()
2555 poll = ixgbe_pcie_timeout_poll(hw); in ixgbe_disable_pcie_primary()
2558 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); in ixgbe_disable_pcie_primary()
2559 if (ixgbe_removed(hw->hw_addr)) in ixgbe_disable_pcie_primary()
2565 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); in ixgbe_disable_pcie_primary()
2577 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) in ixgbe_acquire_swfw_sync() argument
2590 if (ixgbe_get_eeprom_semaphore(hw)) in ixgbe_acquire_swfw_sync()
2593 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); in ixgbe_acquire_swfw_sync()
2596 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); in ixgbe_acquire_swfw_sync()
2597 ixgbe_release_eeprom_semaphore(hw); in ixgbe_acquire_swfw_sync()
2601 ixgbe_release_eeprom_semaphore(hw); in ixgbe_acquire_swfw_sync()
2608 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); in ixgbe_acquire_swfw_sync()
2622 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) in ixgbe_release_swfw_sync() argument
2627 ixgbe_get_eeprom_semaphore(hw); in ixgbe_release_swfw_sync()
2629 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); in ixgbe_release_swfw_sync()
2631 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); in ixgbe_release_swfw_sync()
2633 ixgbe_release_eeprom_semaphore(hw); in ixgbe_release_swfw_sync()
2645 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) in prot_autoc_read_generic() argument
2648 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); in prot_autoc_read_generic()
2659 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) in prot_autoc_write_generic() argument
2661 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); in prot_autoc_write_generic()
2672 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw) in ixgbe_disable_rx_buff_generic() argument
2678 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); in ixgbe_disable_rx_buff_generic()
2680 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); in ixgbe_disable_rx_buff_generic()
2682 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); in ixgbe_disable_rx_buff_generic()
2692 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n"); in ixgbe_disable_rx_buff_generic()
2704 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) in ixgbe_enable_rx_buff_generic() argument
2708 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); in ixgbe_enable_rx_buff_generic()
2710 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); in ixgbe_enable_rx_buff_generic()
2711 IXGBE_WRITE_FLUSH(hw); in ixgbe_enable_rx_buff_generic()
2723 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) in ixgbe_enable_rx_dma_generic() argument
2726 hw->mac.ops.enable_rx(hw); in ixgbe_enable_rx_dma_generic()
2728 hw->mac.ops.disable_rx(hw); in ixgbe_enable_rx_dma_generic()
2738 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_blink_led_start_generic() argument
2742 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_blink_led_start_generic()
2743 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_blink_led_start_generic()
2754 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_blink_led_start_generic()
2757 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); in ixgbe_blink_led_start_generic()
2764 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); in ixgbe_blink_led_start_generic()
2768 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_start_generic()
2775 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_blink_led_start_generic()
2776 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_start_generic()
2786 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_blink_led_stop_generic() argument
2789 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_blink_led_stop_generic()
2796 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); in ixgbe_blink_led_stop_generic()
2803 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); in ixgbe_blink_led_stop_generic()
2810 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_blink_led_stop_generic()
2811 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_stop_generic()
2825 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, in ixgbe_get_san_mac_addr_offset() argument
2834 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, in ixgbe_get_san_mac_addr_offset()
2837 hw_err(hw, "eeprom read at offset %d failed\n", in ixgbe_get_san_mac_addr_offset()
2853 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) in ixgbe_get_san_mac_addr_generic() argument
2863 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); in ixgbe_get_san_mac_addr_generic()
2869 hw->mac.ops.set_lan_id(hw); in ixgbe_get_san_mac_addr_generic()
2871 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : in ixgbe_get_san_mac_addr_generic()
2874 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, in ixgbe_get_san_mac_addr_generic()
2877 hw_err(hw, "eeprom read at offset %d failed\n", in ixgbe_get_san_mac_addr_generic()
2903 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) in ixgbe_get_pcie_msix_count_generic() argument
2909 switch (hw->mac.type) { in ixgbe_get_pcie_msix_count_generic()
2926 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset); in ixgbe_get_pcie_msix_count_generic()
2927 if (ixgbe_removed(hw->hw_addr)) in ixgbe_get_pcie_msix_count_generic()
2946 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) in ixgbe_clear_vmdq_generic() argument
2949 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_clear_vmdq_generic()
2953 hw_dbg(hw, "RAR index %d is out of range.\n", rar); in ixgbe_clear_vmdq_generic()
2957 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); in ixgbe_clear_vmdq_generic()
2958 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); in ixgbe_clear_vmdq_generic()
2960 if (ixgbe_removed(hw->hw_addr)) in ixgbe_clear_vmdq_generic()
2968 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); in ixgbe_clear_vmdq_generic()
2972 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); in ixgbe_clear_vmdq_generic()
2977 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); in ixgbe_clear_vmdq_generic()
2980 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); in ixgbe_clear_vmdq_generic()
2985 rar != 0 && rar != hw->mac.san_mac_rar_index) in ixgbe_clear_vmdq_generic()
2986 hw->mac.ops.clear_rar(hw, rar); in ixgbe_clear_vmdq_generic()
2997 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) in ixgbe_set_vmdq_generic() argument
3000 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_set_vmdq_generic()
3004 hw_dbg(hw, "RAR index %d is out of range.\n", rar); in ixgbe_set_vmdq_generic()
3009 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); in ixgbe_set_vmdq_generic()
3011 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); in ixgbe_set_vmdq_generic()
3013 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); in ixgbe_set_vmdq_generic()
3015 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); in ixgbe_set_vmdq_generic()
3030 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) in ixgbe_set_vmdq_san_mac_generic() argument
3032 u32 rar = hw->mac.san_mac_rar_index; in ixgbe_set_vmdq_san_mac_generic()
3035 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq)); in ixgbe_set_vmdq_san_mac_generic()
3036 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); in ixgbe_set_vmdq_san_mac_generic()
3038 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); in ixgbe_set_vmdq_san_mac_generic()
3039 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32)); in ixgbe_set_vmdq_san_mac_generic()
3049 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) in ixgbe_init_uta_tables_generic() argument
3054 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); in ixgbe_init_uta_tables_generic()
3069 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) in ixgbe_find_vlvf_slot() argument
3093 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); in ixgbe_find_vlvf_slot()
3104 hw_dbg(hw, "No space in VLVF.\n"); in ixgbe_find_vlvf_slot()
3119 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, in ixgbe_set_vfta_generic() argument
3142 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); in ixgbe_set_vfta_generic()
3159 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) in ixgbe_set_vfta_generic()
3162 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); in ixgbe_set_vfta_generic()
3169 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); in ixgbe_set_vfta_generic()
3180 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { in ixgbe_set_vfta_generic()
3186 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); in ixgbe_set_vfta_generic()
3189 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); in ixgbe_set_vfta_generic()
3190 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); in ixgbe_set_vfta_generic()
3213 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); in ixgbe_set_vfta_generic()
3214 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); in ixgbe_set_vfta_generic()
3219 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); in ixgbe_set_vfta_generic()
3230 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) in ixgbe_clear_vfta_generic() argument
3234 for (offset = 0; offset < hw->mac.vft_size; offset++) in ixgbe_clear_vfta_generic()
3235 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); in ixgbe_clear_vfta_generic()
3238 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); in ixgbe_clear_vfta_generic()
3239 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); in ixgbe_clear_vfta_generic()
3240 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); in ixgbe_clear_vfta_generic()
3253 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) in ixgbe_need_crosstalk_fix() argument
3256 if (!hw->need_crosstalk_fix) in ixgbe_need_crosstalk_fix()
3260 switch (hw->mac.ops.get_media_type(hw)) { in ixgbe_need_crosstalk_fix()
3280 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, in ixgbe_check_mac_link_generic() argument
3289 if (ixgbe_need_crosstalk_fix(hw)) { in ixgbe_check_mac_link_generic()
3292 switch (hw->mac.type) { in ixgbe_check_mac_link_generic()
3294 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & in ixgbe_check_mac_link_generic()
3299 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & in ixgbe_check_mac_link_generic()
3316 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
3318 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
3321 hw_dbg(hw, "LINKS changed from %08X to %08X\n", in ixgbe_check_mac_link_generic()
3334 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
3345 if ((hw->mac.type >= ixgbe_mac_X550) && in ixgbe_check_mac_link_generic()
3355 if ((hw->mac.type >= ixgbe_mac_X550) && in ixgbe_check_mac_link_generic()
3363 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || in ixgbe_check_mac_link_generic()
3364 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) { in ixgbe_check_mac_link_generic()
3385 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, in ixgbe_get_wwn_prefix_generic() argument
3397 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) in ixgbe_get_wwn_prefix_generic()
3406 if (hw->eeprom.ops.read(hw, offset, &caps)) in ixgbe_get_wwn_prefix_generic()
3413 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) in ixgbe_get_wwn_prefix_generic()
3414 hw_err(hw, "eeprom read at offset %d failed\n", offset); in ixgbe_get_wwn_prefix_generic()
3417 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) in ixgbe_get_wwn_prefix_generic()
3423 hw_err(hw, "eeprom read at offset %d failed\n", offset); in ixgbe_get_wwn_prefix_generic()
3434 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) in ixgbe_set_mac_anti_spoofing() argument
3440 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_set_mac_anti_spoofing()
3443 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); in ixgbe_set_mac_anti_spoofing()
3448 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); in ixgbe_set_mac_anti_spoofing()
3458 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) in ixgbe_set_vlan_anti_spoofing() argument
3464 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_set_vlan_anti_spoofing()
3467 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); in ixgbe_set_vlan_anti_spoofing()
3472 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); in ixgbe_set_vlan_anti_spoofing()
3483 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) in ixgbe_get_device_caps_generic() argument
3485 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); in ixgbe_get_device_caps_generic()
3497 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, in ixgbe_set_rxpba_generic() argument
3502 u32 pbsize = hw->mac.rx_pb_size; in ixgbe_set_rxpba_generic()
3524 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); in ixgbe_set_rxpba_generic()
3530 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); in ixgbe_set_rxpba_generic()
3544 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); in ixgbe_set_rxpba_generic()
3545 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); in ixgbe_set_rxpba_generic()
3550 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); in ixgbe_set_rxpba_generic()
3551 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); in ixgbe_set_rxpba_generic()
3552 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); in ixgbe_set_rxpba_generic()
3593 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, in ixgbe_hic_unlocked() argument
3600 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); in ixgbe_hic_unlocked()
3605 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); in ixgbe_hic_unlocked()
3606 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); in ixgbe_hic_unlocked()
3609 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); in ixgbe_hic_unlocked()
3611 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); in ixgbe_hic_unlocked()
3617 hw_dbg(hw, "Buffer length failure, not aligned to dword"); in ixgbe_hic_unlocked()
3627 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, in ixgbe_hic_unlocked()
3631 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); in ixgbe_hic_unlocked()
3634 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); in ixgbe_hic_unlocked()
3642 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) in ixgbe_hic_unlocked()
3665 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer, in ixgbe_host_interface_command() argument
3677 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); in ixgbe_host_interface_command()
3681 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); in ixgbe_host_interface_command()
3685 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); in ixgbe_host_interface_command()
3697 u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); in ixgbe_host_interface_command()
3707 hw_dbg(hw, "Buffer not large enough for reply message.\n"); in ixgbe_host_interface_command()
3717 u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); in ixgbe_host_interface_command()
3722 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); in ixgbe_host_interface_command()
3742 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, in ixgbe_set_fw_drv_ver_generic() argument
3753 fw_cmd.port_num = hw->bus.func; in ixgbe_set_fw_drv_ver_generic()
3765 ret_val = ixgbe_host_interface_command(hw, &fw_cmd, in ixgbe_set_fw_drv_ver_generic()
3792 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) in ixgbe_clear_tx_pending() argument
3801 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) in ixgbe_clear_tx_pending()
3809 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); in ixgbe_clear_tx_pending()
3810 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); in ixgbe_clear_tx_pending()
3813 IXGBE_WRITE_FLUSH(hw); in ixgbe_clear_tx_pending()
3819 poll = ixgbe_pcie_timeout_poll(hw); in ixgbe_clear_tx_pending()
3822 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); in ixgbe_clear_tx_pending()
3823 if (ixgbe_removed(hw->hw_addr)) in ixgbe_clear_tx_pending()
3830 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); in ixgbe_clear_tx_pending()
3831 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, in ixgbe_clear_tx_pending()
3835 IXGBE_WRITE_FLUSH(hw); in ixgbe_clear_tx_pending()
3839 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); in ixgbe_clear_tx_pending()
3840 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); in ixgbe_clear_tx_pending()
3864 static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg, in ixgbe_get_ets_data() argument
3869 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset); in ixgbe_get_ets_data()
3876 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg); in ixgbe_get_ets_data()
3892 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) in ixgbe_get_thermal_sensor_data_generic() argument
3900 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; in ixgbe_get_thermal_sensor_data_generic()
3903 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) in ixgbe_get_thermal_sensor_data_generic()
3906 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); in ixgbe_get_thermal_sensor_data_generic()
3918 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), in ixgbe_get_thermal_sensor_data_generic()
3929 status = hw->phy.ops.read_i2c_byte(hw, in ixgbe_get_thermal_sensor_data_generic()
3948 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) in ixgbe_init_thermal_sensor_thresh_generic() argument
3958 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; in ixgbe_init_thermal_sensor_thresh_generic()
3963 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) in ixgbe_init_thermal_sensor_thresh_generic()
3966 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); in ixgbe_init_thermal_sensor_thresh_generic()
3980 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) { in ixgbe_init_thermal_sensor_thresh_generic()
3981 hw_err(hw, "eeprom read at offset %d failed\n", in ixgbe_init_thermal_sensor_thresh_generic()
3991 hw->phy.ops.write_i2c_byte(hw, in ixgbe_init_thermal_sensor_thresh_generic()
4015 void ixgbe_get_orom_version(struct ixgbe_hw *hw, in ixgbe_get_orom_version() argument
4022 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); in ixgbe_get_orom_version()
4028 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); in ixgbe_get_orom_version()
4029 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); in ixgbe_get_orom_version()
4052 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, in ixgbe_get_oem_prod_version() argument
4058 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); in ixgbe_get_oem_prod_version()
4065 hw->eeprom.ops.read(hw, offset, &mod_len); in ixgbe_get_oem_prod_version()
4066 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); in ixgbe_get_oem_prod_version()
4073 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); in ixgbe_get_oem_prod_version()
4074 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); in ixgbe_get_oem_prod_version()
4095 void ixgbe_get_etk_id(struct ixgbe_hw *hw, in ixgbe_get_etk_id() argument
4100 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) in ixgbe_get_etk_id()
4102 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) in ixgbe_get_etk_id()
4117 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) in ixgbe_disable_rx_generic() argument
4121 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); in ixgbe_disable_rx_generic()
4123 if (hw->mac.type != ixgbe_mac_82598EB) { in ixgbe_disable_rx_generic()
4126 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); in ixgbe_disable_rx_generic()
4129 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); in ixgbe_disable_rx_generic()
4130 hw->mac.set_lben = true; in ixgbe_disable_rx_generic()
4132 hw->mac.set_lben = false; in ixgbe_disable_rx_generic()
4136 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); in ixgbe_disable_rx_generic()
4140 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) in ixgbe_enable_rx_generic() argument
4144 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); in ixgbe_enable_rx_generic()
4145 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); in ixgbe_enable_rx_generic()
4147 if (hw->mac.type != ixgbe_mac_82598EB) { in ixgbe_enable_rx_generic()
4148 if (hw->mac.set_lben) { in ixgbe_enable_rx_generic()
4151 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); in ixgbe_enable_rx_generic()
4153 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); in ixgbe_enable_rx_generic()
4154 hw->mac.set_lben = false; in ixgbe_enable_rx_generic()
4162 bool ixgbe_mng_present(struct ixgbe_hw *hw) in ixgbe_mng_present() argument
4166 if (hw->mac.type < ixgbe_mac_82599EB) in ixgbe_mng_present()
4169 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); in ixgbe_mng_present()
4182 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, in ixgbe_setup_mac_link_multispeed_fiber() argument
4194 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg); in ixgbe_setup_mac_link_multispeed_fiber()
4208 switch (hw->phy.media_type) { in ixgbe_setup_mac_link_multispeed_fiber()
4210 hw->mac.ops.set_rate_select_speed(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4217 hw_dbg(hw, "Unexpected media type\n"); in ixgbe_setup_mac_link_multispeed_fiber()
4224 status = hw->mac.ops.setup_mac_link(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4231 if (hw->mac.ops.flap_tx_laser) in ixgbe_setup_mac_link_multispeed_fiber()
4232 hw->mac.ops.flap_tx_laser(hw); in ixgbe_setup_mac_link_multispeed_fiber()
4243 status = hw->mac.ops.check_link(hw, &link_speed, in ixgbe_setup_mac_link_multispeed_fiber()
4259 switch (hw->phy.media_type) { in ixgbe_setup_mac_link_multispeed_fiber()
4261 hw->mac.ops.set_rate_select_speed(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4268 hw_dbg(hw, "Unexpected media type\n"); in ixgbe_setup_mac_link_multispeed_fiber()
4275 status = hw->mac.ops.setup_mac_link(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4282 if (hw->mac.ops.flap_tx_laser) in ixgbe_setup_mac_link_multispeed_fiber()
4283 hw->mac.ops.flap_tx_laser(hw); in ixgbe_setup_mac_link_multispeed_fiber()
4289 status = hw->mac.ops.check_link(hw, &link_speed, &link_up, in ixgbe_setup_mac_link_multispeed_fiber()
4303 status = ixgbe_setup_mac_link_multispeed_fiber(hw, in ixgbe_setup_mac_link_multispeed_fiber()
4309 hw->phy.autoneg_advertised = 0; in ixgbe_setup_mac_link_multispeed_fiber()
4312 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; in ixgbe_setup_mac_link_multispeed_fiber()
4315 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; in ixgbe_setup_mac_link_multispeed_fiber()
4327 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, in ixgbe_set_soft_rate_select_speed() argument
4342 hw_dbg(hw, "Invalid fixed module speed\n"); in ixgbe_set_soft_rate_select_speed()
4347 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, in ixgbe_set_soft_rate_select_speed()
4351 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n"); in ixgbe_set_soft_rate_select_speed()
4357 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, in ixgbe_set_soft_rate_select_speed()
4361 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n"); in ixgbe_set_soft_rate_select_speed()
4366 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, in ixgbe_set_soft_rate_select_speed()
4370 hw_dbg(hw, "Failed to read Rx Rate Select RS1\n"); in ixgbe_set_soft_rate_select_speed()
4376 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, in ixgbe_set_soft_rate_select_speed()
4380 hw_dbg(hw, "Failed to write Rx Rate Select RS1\n"); in ixgbe_set_soft_rate_select_speed()