Lines Matching refs:bits
31 #define vxge_bVALn(bits, loc, n) \ argument
32 ((((u64)bits) >> (64-(loc+n))) & ((0x1ULL << n) - 1))
34 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(bits) \ argument
35 vxge_bVALn(bits, 0, 16)
36 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(bits) \ argument
37 vxge_bVALn(bits, 48, 8)
38 #define VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(bits) \ argument
39 vxge_bVALn(bits, 56, 8)
41 #define VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(bits) \ argument
42 vxge_bVALn(bits, 3, 5)
43 #define VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(bits) \ argument
44 vxge_bVALn(bits, 5, 3)
89 #define VXGE_HW_VPATH_IS_FIRST_GET_VPATH_IS_FIRST(bits) vxge_bVALn(bits, 3, 1) argument
91 #define VXGE_HW_TIM_VPATH_ASSIGNMENT_GET_BMAP_ROOT(bits) \ argument
92 vxge_bVALn(bits, 0, 32)
94 #define VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN(bits) \ argument
95 vxge_bVALn(bits, 50, 14)
97 #define VXGE_HW_XMAC_VSPORT_CHOICES_VP_GET_VSPORT_VECTOR(bits) \ argument
98 vxge_bVALn(bits, 0, 17)
100 #define VXGE_HW_XMAC_VPATH_TO_VSPORT_VPMGMT_CLONE_GET_VSPORT_NUMBER(bits) \ argument
101 vxge_bVALn(bits, 3, 5)
103 #define VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(bits) \ argument
104 vxge_bVALn(bits, 17, 15)
122 #define VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(bits) bits argument
123 #define VXGE_HW_TOC_KDFC_FIFO_STRIDE_GET_TOC_KDFC_FIFO_STRIDE(bits) bits argument
125 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR0(bits) \ argument
126 vxge_bVALn(bits, 1, 15)
127 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR1(bits) \ argument
128 vxge_bVALn(bits, 17, 15)
129 #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR2(bits) \ argument
130 vxge_bVALn(bits, 33, 15)
163 #define VXGE_HW_RTS_MGR_STEER_DATA0_GET_DA_MAC_ADDR(bits) \ argument
164 vxge_bVALn(bits, 0, 48)
167 #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) \ argument
168 vxge_bVALn(bits, 0, 48)
172 #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_VPATH(bits) \ argument
173 vxge_bVALn(bits, 55, 5)
176 #define VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_MODE(bits) \ argument
177 vxge_bVALn(bits, 62, 2)
204 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(bits) \ argument
205 vxge_bVALn(bits, 0, 48)
208 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(bits) vxge_bVALn(bits, 0, 12) argument
211 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_ETYPE(bits) vxge_bVALn(bits, 0, 11) argument
214 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL(bits) \ argument
215 vxge_bVALn(bits, 3, 1)
217 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL(bits) \ argument
218 vxge_bVALn(bits, 7, 1)
220 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM(bits) \ argument
221 vxge_bVALn(bits, 8, 16)
224 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_EN(bits) \ argument
225 vxge_bVALn(bits, 3, 1)
227 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_BUCKET_SIZE(bits) \ argument
228 vxge_bVALn(bits, 4, 4)
231 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ALG_SEL(bits) \ argument
232 vxge_bVALn(bits, 10, 2)
238 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV4_EN(bits) \ argument
239 vxge_bVALn(bits, 15, 1)
241 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV4_EN(bits) \ argument
242 vxge_bVALn(bits, 19, 1)
244 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EN(bits) \ argument
245 vxge_bVALn(bits, 23, 1)
247 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EN(bits) \ argument
248 vxge_bVALn(bits, 27, 1)
250 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EX_EN(bits) \ argument
251 vxge_bVALn(bits, 31, 1)
253 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EX_EN(bits) \ argument
254 vxge_bVALn(bits, 35, 1)
256 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(bits) \ argument
257 vxge_bVALn(bits, 39, 1)
259 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_REPL_ENTRY_EN(bits) \ argument
260 vxge_bVALn(bits, 43, 1)
263 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_ENTRY_EN(bits) \ argument
264 vxge_bVALn(bits, 3, 1)
266 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_BUCKET_DATA(bits) \ argument
267 vxge_bVALn(bits, 9, 7)
271 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_NUM(bits) \ argument
272 vxge_bVALn(bits, 0, 8)
275 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_ENTRY_EN(bits) \ argument
276 vxge_bVALn(bits, 8, 1)
278 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_DATA(bits) \ argument
279 vxge_bVALn(bits, 9, 7)
282 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_NUM(bits) \ argument
283 vxge_bVALn(bits, 16, 8)
286 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_ENTRY_EN(bits) \ argument
287 vxge_bVALn(bits, 24, 1)
289 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_DATA(bits) \ argument
290 vxge_bVALn(bits, 25, 7)
293 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_NUM(bits) \ argument
294 vxge_bVALn(bits, 0, 8)
297 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_ENTRY_EN(bits) \ argument
298 vxge_bVALn(bits, 8, 1)
300 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_DATA(bits) \ argument
301 vxge_bVALn(bits, 9, 7)
304 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_NUM(bits) \ argument
305 vxge_bVALn(bits, 16, 8)
308 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_ENTRY_EN(bits) \ argument
309 vxge_bVALn(bits, 24, 1)
311 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_DATA(bits) \ argument
312 vxge_bVALn(bits, 25, 7)
316 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_GOLDEN_RATIO(bits) \ argument
317 vxge_bVALn(bits, 0, 32)
320 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_INIT_VALUE(bits) \ argument
321 vxge_bVALn(bits, 32, 32)
325 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_SA_MASK(bits) \ argument
326 vxge_bVALn(bits, 0, 16)
329 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_DA_MASK(bits) \ argument
330 vxge_bVALn(bits, 16, 16)
333 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_SA_MASK(bits) \ argument
334 vxge_bVALn(bits, 32, 4)
337 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_DA_MASK(bits) \ argument
338 vxge_bVALn(bits, 36, 4)
341 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4SP_MASK(bits) \ argument
342 vxge_bVALn(bits, 40, 2)
345 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4DP_MASK(bits) \ argument
346 vxge_bVALn(bits, 42, 2)
350 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_KEY_KEY(bits) \ argument
351 vxge_bVALn(bits, 0, 64)
354 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_QOS_ENTRY_EN(bits) \ argument
355 vxge_bVALn(bits, 3, 1)
358 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DS_ENTRY_EN(bits) \ argument
359 vxge_bVALn(bits, 3, 1)
362 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(bits) \ argument
363 vxge_bVALn(bits, 0, 48)
369 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_NUM(bits) \ argument
370 vxge_bVALn(bits, 0, 8)
373 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_ENTRY_EN(bits) \ argument
374 vxge_bVALn(bits, 8, 1)
376 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_DATA(bits) \ argument
377 vxge_bVALn(bits, 9, 7)
380 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_NUM(bits) \ argument
381 vxge_bVALn(bits, 16, 8)
384 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_ENTRY_EN(bits) \ argument
385 vxge_bVALn(bits, 24, 1)
387 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_DATA(bits) \ argument
388 vxge_bVALn(bits, 25, 7)
391 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_NUM(bits) \ argument
392 vxge_bVALn(bits, 32, 8)
395 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_ENTRY_EN(bits) \ argument
396 vxge_bVALn(bits, 40, 1)
398 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_DATA(bits) \ argument
399 vxge_bVALn(bits, 41, 7)
402 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_NUM(bits) \ argument
403 vxge_bVALn(bits, 48, 8)
406 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_ENTRY_EN(bits) \ argument
407 vxge_bVALn(bits, 56, 1)
409 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_DATA(bits) \ argument
410 vxge_bVALn(bits, 57, 7)
426 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(bits) \ argument
427 vxge_bVALn(bits, 0, 8)
429 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(bits) \ argument
430 vxge_bVALn(bits, 8, 8)
432 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(bits) \ argument
433 vxge_bVALn(bits, 16, 16)
437 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(bits) \ argument
438 vxge_bVALn(bits, 32, 8)
440 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(bits) \ argument
441 vxge_bVALn(bits, 40, 8)
443 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(bits) \ argument
444 vxge_bVALn(bits, 48, 16)
447 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(bits) \ argument
448 vxge_bVALn(bits, 0, 8)
450 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(bits) \ argument
451 vxge_bVALn(bits, 8, 8)
453 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(bits) \ argument
454 vxge_bVALn(bits, 16, 16)
458 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(bits) \ argument
459 vxge_bVALn(bits, 32, 8)
461 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(bits) \ argument
462 vxge_bVALn(bits, 40, 8)
464 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(bits) \ argument
465 vxge_bVALn(bits, 48, 16)
467 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(bits) vxge_bVALn(bits, 0, 8) argument
469 #define VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_GET_PPIF_SRPCIM_TO_VPATH_ALARM(bits)\ argument
470 vxge_bVALn(bits, 0, 18)
472 #define VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(bits) \ argument
473 vxge_bVALn(bits, 48, 16)
474 #define VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(bits) \ argument
475 vxge_bVALn(bits, 32, 32)
476 #define VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(bits) vxge_bVALn(bits, 48, 16) argument
477 #define VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(bits) \ argument
478 vxge_bVALn(bits, 0, 32)
479 #define VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(bits) \ argument
480 vxge_bVALn(bits, 0, 32)
481 #define VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(bits) \ argument
482 vxge_bVALn(bits, 0, 32)
483 #define VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(bits) (bits) argument
484 #define VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(bits) (bits) argument
485 #define VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(bits) \ argument
486 vxge_bVALn(bits, 32, 32)
487 #define VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(bits) \ argument
488 vxge_bVALn(bits, 32, 32)
489 #define VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(bits) \ argument
490 vxge_bVALn(bits, 0, 32)
491 #define VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(bits) \ argument
492 vxge_bVALn(bits, 32, 32)
493 #define VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(bits) \ argument
494 vxge_bVALn(bits, 0, 32)
495 #define VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(bits) \ argument
496 vxge_bVALn(bits, 32, 32)
497 #define VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(bits) \ argument
498 vxge_bVALn(bits, 0, 32)
499 #define VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(bits) \ argument
500 vxge_bVALn(bits, 32, 32)
501 #define VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(bits\ argument
502 ) vxge_bVALn(bits, 48, 16)
503 #define VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(bits) vxge_bVALn(bits, 0, 16) argument
504 #define VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(bits) \ argument
505 vxge_bVALn(bits, 16, 16)
506 #define VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(bits) \ argument
507 vxge_bVALn(bits, 32, 16)
508 #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(bits) vxge_bVALn(bits, 0, 16) argument
509 #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(bits) \ argument
510 vxge_bVALn(bits, 16, 16)
511 #define VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(bits) \ argument
512 vxge_bVALn(bits, 32, 16)
514 #define VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_WR_DROP(bits) \ argument
515 vxge_bVALn(bits, 0, 32)
516 #define VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_RD_DROP(bits) \ argument
517 vxge_bVALn(bits, 32, 32)
518 #define VXGE_HW_MRPCIM_DEBUG_STATS1_GET_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(bits\ argument
519 ) vxge_bVALn(bits, 32, 32)
520 #define VXGE_HW_MRPCIM_DEBUG_STATS2_GET_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(bits\ argument
521 ) vxge_bVALn(bits, 32, 32)
523 VXGE_HW_MRPCIM_DEBUG_STATS3_GET_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(bits) \ argument
524 vxge_bVALn(bits, 32, 32)
525 #define VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_WR_VPIN_DROP(bits) \ argument
526 vxge_bVALn(bits, 0, 32)
527 #define VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_RD_VPIN_DROP(bits) \ argument
528 vxge_bVALn(bits, 32, 32)
529 #define VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT1(bits) \ argument
530 vxge_bVALn(bits, 0, 32)
531 #define VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT0(bits) \ argument
532 vxge_bVALn(bits, 32, 32)
533 #define VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT3(bits) \ argument
534 vxge_bVALn(bits, 0, 32)
535 #define VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT2(bits) \ argument
536 vxge_bVALn(bits, 32, 32)
537 #define VXGE_HW_GENSTATS_COUNT4_GET_GENSTATS_COUNT4(bits) \ argument
538 vxge_bVALn(bits, 32, 32)
539 #define VXGE_HW_GENSTATS_COUNT5_GET_GENSTATS_COUNT5(bits) \ argument
540 vxge_bVALn(bits, 32, 32)
542 #define VXGE_HW_DEBUG_STATS0_GET_RSTDROP_MSG(bits) vxge_bVALn(bits, 0, 32) argument
543 #define VXGE_HW_DEBUG_STATS0_GET_RSTDROP_CPL(bits) vxge_bVALn(bits, 32, 32) argument
544 #define VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT0(bits) vxge_bVALn(bits, 0, 32) argument
545 #define VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT1(bits) vxge_bVALn(bits, 32, 32) argument
546 #define VXGE_HW_DEBUG_STATS2_GET_RSTDROP_CLIENT2(bits) vxge_bVALn(bits, 0, 32) argument
547 #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_PH(bits) vxge_bVALn(bits, 0, 16) argument
548 #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_NPH(bits) vxge_bVALn(bits, 16, 16) argument
549 #define VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_CPLH(bits) vxge_bVALn(bits, 32, 16) argument
550 #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_PD(bits) vxge_bVALn(bits, 0, 16) argument
551 #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_NPD(bits) bVAL(bits, 16, 16) argument
552 #define VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_CPLD(bits) vxge_bVALn(bits, 32, 16) argument
554 #define VXGE_HW_DBG_STATS_TPA_TX_PATH_GET_TX_PERMITTED_FRMS(bits) \ argument
555 vxge_bVALn(bits, 32, 32)
557 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT0_TX_ANY_FRMS(bits) \ argument
558 vxge_bVALn(bits, 0, 8)
559 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT1_TX_ANY_FRMS(bits) \ argument
560 vxge_bVALn(bits, 8, 8)
561 #define VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT2_TX_ANY_FRMS(bits) \ argument
562 vxge_bVALn(bits, 16, 8)
564 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT0_RX_ANY_FRMS(bits) \ argument
565 vxge_bVALn(bits, 0, 8)
566 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT1_RX_ANY_FRMS(bits) \ argument
567 vxge_bVALn(bits, 8, 8)
568 #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT2_RX_ANY_FRMS(bits) \ argument
569 vxge_bVALn(bits, 16, 8)