Lines Matching refs:u32
39 u32 cmd_id;
43 u32 header;
2132 u32 pdev_id;
2133 u32 start_freq;
2134 u32 end_freq;
2138 u32 numss_m1;
2139 u32 ru_bit_mask;
2140 u32 ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS];
2144 u32 default_conc_scan_config_bits;
2145 u32 default_fw_config_bits;
2147 u32 he_cap_info;
2148 u32 mpdu_density;
2149 u32 max_bssid_rx_filters;
2150 u32 num_hw_modes;
2151 u32 num_phy;
2155 u32 hw_mode_id;
2156 u32 phy_id_map;
2157 u32 hw_mode_config_type;
2169 u32 phy_id;
2170 u32 eeprom_reg_domain;
2171 u32 eeprom_reg_domain_ext;
2172 u32 regcap1;
2173 u32 regcap2;
2174 u32 wireless_modes;
2175 u32 low_2ghz_chan;
2176 u32 high_2ghz_chan;
2177 u32 low_5ghz_chan;
2178 u32 high_5ghz_chan;
2184 u32 tlv_header;
2185 u32 req_id;
2186 u32 ptr;
2187 u32 size;
2193 u32 len;
2194 u32 req_id;
2198 u32 tlv_header;
2202 u32 hw_mode_id;
2203 u32 num_band_to_mac;
2208 u32 tlv_header;
2209 u32 pdev_id;
2210 u32 start_freq;
2211 u32 end_freq;
2215 u32 tlv_header;
2216 u32 pdev_id;
2217 u32 hw_mode_index;
2218 u32 num_band_to_mac;
2222 u32 numss_m1; /** NSS - 1*/
2224 u32 ru_count;
2225 u32 ru_mask;
2227 u32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS];
2233 u32 abi_version_0;
2234 u32 abi_version_1;
2235 u32 abi_version_ns_0;
2236 u32 abi_version_ns_1;
2237 u32 abi_version_ns_2;
2238 u32 abi_version_ns_3;
2242 u32 tlv_header;
2244 u32 num_host_mem_chunks;
2248 u32 tlv_header;
2249 u32 num_vdevs;
2250 u32 num_peers;
2251 u32 num_offload_peers;
2252 u32 num_offload_reorder_buffs;
2253 u32 num_peer_keys;
2254 u32 num_tids;
2255 u32 ast_skid_limit;
2256 u32 tx_chain_mask;
2257 u32 rx_chain_mask;
2258 u32 rx_timeout_pri[4];
2259 u32 rx_decap_mode;
2260 u32 scan_max_pending_req;
2261 u32 bmiss_offload_max_vdev;
2262 u32 roam_offload_max_vdev;
2263 u32 roam_offload_max_ap_profiles;
2264 u32 num_mcast_groups;
2265 u32 num_mcast_table_elems;
2266 u32 mcast2ucast_mode;
2267 u32 tx_dbg_log_size;
2268 u32 num_wds_entries;
2269 u32 dma_burst_size;
2270 u32 mac_aggr_delim;
2271 u32 rx_skip_defrag_timeout_dup_detection_check;
2272 u32 vow_config;
2273 u32 gtk_offload_max_vdev;
2274 u32 num_msdu_desc;
2275 u32 max_frag_entries;
2276 u32 num_tdls_vdevs;
2277 u32 num_tdls_conn_table_entries;
2278 u32 beacon_tx_offload_max_vdev;
2279 u32 num_multicast_filter_entries;
2280 u32 num_wow_filters;
2281 u32 num_keep_alive_pattern;
2282 u32 keep_alive_pattern_size;
2283 u32 max_tdls_concurrent_sleep_sta;
2284 u32 max_tdls_concurrent_buffer_sta;
2285 u32 wmi_send_separate;
2286 u32 num_ocb_vdevs;
2287 u32 num_ocb_channels;
2288 u32 num_ocb_schedules;
2289 u32 flag1;
2290 u32 smart_ant_cap;
2291 u32 bk_minfree;
2292 u32 be_minfree;
2293 u32 vi_minfree;
2294 u32 vo_minfree;
2295 u32 alloc_frag_desc_for_data_pkt;
2296 u32 num_ns_ext_tuples_cfg;
2297 u32 bpf_instruction_size;
2298 u32 max_bssid_rx_filters;
2299 u32 use_pdev_id;
2300 u32 max_num_dbs_scan_duty_cycle;
2301 u32 max_num_group_keys;
2302 u32 peer_map_unmap_v2_support;
2303 u32 sched_params;
2304 u32 twt_ap_pdev_count;
2305 u32 twt_ap_sta_count;
2309 u32 fw_build_vers;
2311 u32 phy_capability;
2312 u32 max_frag_entry;
2313 u32 num_rf_chains;
2314 u32 ht_cap_info;
2315 u32 vht_cap_info;
2316 u32 vht_supp_mcs;
2317 u32 hw_min_tx_power;
2318 u32 hw_max_tx_power;
2319 u32 sys_cap_info;
2320 u32 min_pkt_size_enable;
2321 u32 max_bcn_ie_size;
2322 u32 num_mem_reqs;
2323 u32 max_num_scan_channels;
2324 u32 hw_bd_id;
2325 u32 hw_bd_info[HW_BD_INFO_SIZE];
2326 u32 max_supported_macs;
2327 u32 wmi_fw_sub_feat_caps;
2328 u32 num_dbs_hw_modes;
2335 u32 txrx_chainmask;
2336 u32 default_dbs_hw_mode_index;
2337 u32 num_msdu_desc;
2340 #define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(u32) - 1) / sizeof(u32))
2343 #define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32))
2348 u32 default_conc_scan_config_bits;
2349 u32 default_fw_config_bits;
2351 u32 he_cap_info;
2352 u32 mpdu_density;
2353 u32 max_bssid_rx_filters;
2354 u32 fw_build_vers_ext;
2355 u32 max_nlo_ssids;
2356 u32 max_bssid_indicator;
2357 u32 he_cap_info_ext;
2361 u32 num_hw_modes;
2362 u32 num_chainmask_tables;
2366 u32 tlv_header;
2367 u32 hw_mode_id;
2368 u32 phy_id_map;
2369 u32 hw_mode_config_type;
2375 u32 hw_mode_id;
2376 u32 pdev_id;
2377 u32 phy_id;
2378 u32 supported_flags;
2379 u32 supported_bands;
2380 u32 ampdu_density;
2381 u32 max_bw_supported_2g;
2382 u32 ht_cap_info_2g;
2383 u32 vht_cap_info_2g;
2384 u32 vht_supp_mcs_2g;
2385 u32 he_cap_info_2g;
2386 u32 he_supp_mcs_2g;
2387 u32 tx_chain_mask_2g;
2388 u32 rx_chain_mask_2g;
2389 u32 max_bw_supported_5g;
2390 u32 ht_cap_info_5g;
2391 u32 vht_cap_info_5g;
2392 u32 vht_supp_mcs_5g;
2393 u32 he_cap_info_5g;
2394 u32 he_supp_mcs_5g;
2395 u32 tx_chain_mask_5g;
2396 u32 rx_chain_mask_5g;
2397 u32 he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE];
2398 u32 he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE];
2401 u32 chainmask_table_id;
2402 u32 lmac_id;
2403 u32 he_cap_info_2g_ext;
2404 u32 he_cap_info_5g_ext;
2405 u32 he_cap_info_internal;
2409 u32 tlv_header;
2410 u32 phy_id;
2411 u32 eeprom_reg_domain;
2412 u32 eeprom_reg_domain_ext;
2413 u32 regcap1;
2414 u32 regcap2;
2415 u32 wireless_modes;
2416 u32 low_2ghz_chan;
2417 u32 high_2ghz_chan;
2418 u32 low_5ghz_chan;
2419 u32 high_5ghz_chan;
2423 u32 num_phy;
2431 u32 word0;
2432 u32 word1;
2438 u32 tlv_header;
2439 u32 pdev_id;
2440 u32 module_id;
2441 u32 min_elem;
2442 u32 min_buf_sz;
2443 u32 min_buf_align;
2449 u32 status;
2450 u32 num_dscp_table;
2451 u32 num_extra_mac_addr;
2452 u32 num_total_peers;
2453 u32 num_extra_peers;
2458 u32 max_ast_index;
2459 u32 pktlog_defs_checksum;
2463 u32 wmi_service_segment_offset;
2464 u32 wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32];
2471 u32 rx_decap_mode;
2476 u32 type;
2477 u32 subtype;
2482 u32 pdev_id;
2486 u32 tlv_header;
2487 u32 vdev_id;
2488 u32 vdev_type;
2489 u32 vdev_subtype;
2491 u32 num_cfg_txrx_streams;
2492 u32 pdev_id;
2496 u32 tlv_header;
2497 u32 band;
2498 u32 supported_tx_streams;
2499 u32 supported_rx_streams;
2503 u32 tlv_header;
2504 u32 vdev_id;
2508 u32 tlv_header;
2509 u32 vdev_id;
2510 u32 vdev_assoc_id;
2513 u32 profile_idx;
2514 u32 profile_num;
2518 u32 tlv_header;
2519 u32 vdev_id;
2523 u32 tlv_header;
2524 u32 vdev_id;
2532 u32 ssid_len;
2533 u32 ssid[8];
2539 u32 tlv_header;
2540 u32 vdev_id;
2541 u32 requestor_id;
2542 u32 beacon_interval;
2543 u32 dtim_period;
2544 u32 flags;
2546 u32 bcn_tx_rate;
2547 u32 bcn_txpower;
2548 u32 num_noa_descriptors;
2549 u32 disable_hw_ack;
2550 u32 preferred_tx_streams;
2551 u32 preferred_rx_streams;
2552 u32 he_ops;
2553 u32 cac_duration_ms;
2554 u32 regdomain;
2565 u32 type_count;
2566 u32 duration;
2567 u32 interval;
2568 u32 start_time;
2574 u32 mhz;
2575 u32 half_rate:1,
2585 u32 phy_mode;
2586 u32 cfreq1;
2587 u32 cfreq2;
2688 u32 freq;
2689 u32 band_center_freq1;
2690 u32 band_center_freq2;
2699 u32 min_power;
2700 u32 max_power;
2701 u32 max_reg_power;
2702 u32 max_antenna_gain;
2707 u32 vdev_id;
2709 u32 bcn_intval;
2710 u32 dtim_period;
2712 u32 ssid_len;
2713 u32 bcn_tx_rate;
2714 u32 bcn_tx_power;
2718 u32 he_ops;
2719 u32 cac_duration_ms;
2720 u32 regdomain;
2721 u32 pref_rx_streams;
2722 u32 pref_tx_streams;
2723 u32 num_noa_descriptors;
2728 u32 peer_type;
2729 u32 vdev_id;
2737 u32 peer_tid_bitmap;
2745 u32 ctl_2g;
2746 u32 ctl_5g;
2748 u32 pdev_id;
2754 u32 peer_tid_bitmap;
2836 u32 param_id;
2837 u32 param_value;
2847 u32 tlv_header;
2848 u32 vdev_id;
2850 u32 peer_type;
2854 u32 tlv_header;
2855 u32 vdev_id;
2860 u32 tlv_header;
2861 u32 vdev_id;
2863 u32 tid;
2864 u32 queue_ptr_lo;
2865 u32 queue_ptr_hi;
2866 u32 queue_no;
2867 u32 ba_window_size_valid;
2868 u32 ba_window_size;
2872 u32 tlv_header;
2873 u32 vdev_id;
2875 u32 tid_mask;
2879 u32 gpio_num;
2880 u32 input;
2881 u32 pull_type;
2882 u32 intr_mode;
2906 u32 tlv_header;
2907 u32 gpio_num;
2908 u32 input;
2909 u32 pull_type;
2910 u32 intr_mode;
2914 u32 gpio_num;
2915 u32 set;
2919 u32 tlv_header;
2920 u32 gpio_num;
2921 u32 set;
2925 u32 arg;
2926 u32 value;
2930 u32 tlv_header;
2931 u32 param_id;
2932 u32 param_value;
2936 u32 tlv_header;
2937 u32 pdev_id;
2938 u32 param_id;
2939 u32 param_value;
2943 u32 tlv_header;
2944 u32 vdev_id;
2945 u32 sta_ps_mode;
2949 u32 tlv_header;
2950 u32 pdev_id;
2951 u32 suspend_opt;
2955 u32 tlv_header;
2956 u32 pdev_id;
2960 u32 tlv_header;
2962 u32 req_type;
2963 u32 pdev_id;
2967 u32 tlv_header;
2968 u32 vdev_id;
2970 u32 param;
2971 u32 value;
2975 u32 tlv_header;
2976 u32 vdev_id;
2977 u32 param;
2978 u32 value;
2982 u32 tlv_header;
2983 u32 pdev_id;
2984 u32 reg_domain;
2985 u32 reg_domain_2g;
2986 u32 reg_domain_5g;
2987 u32 conformance_test_limit_2g;
2988 u32 conformance_test_limit_5g;
2989 u32 dfs_domain;
2993 u32 tlv_header;
2994 u32 vdev_id;
2996 u32 param_id;
2997 u32 param_value;
3001 u32 tlv_header;
3002 u32 vdev_id;
3004 u32 peer_tid_bitmap;
3008 u32 tlv_header;
3009 u32 pdev_id;
3013 u32 tlv_header;
3014 u32 vdev_id;
3015 u32 bcn_ctrl_op;
3033 u32 len;
3097 u32 tlv_header;
3098 u32 scan_id;
3099 u32 scan_req_id;
3100 u32 vdev_id;
3101 u32 scan_priority;
3102 u32 notify_scan_events;
3103 u32 dwell_time_active;
3104 u32 dwell_time_passive;
3105 u32 min_rest_time;
3106 u32 max_rest_time;
3107 u32 repeat_probe_time;
3108 u32 probe_spacing_time;
3109 u32 idle_time;
3110 u32 max_scan_time;
3111 u32 probe_delay;
3112 u32 scan_ctrl_flags;
3113 u32 burst_duration;
3114 u32 num_chan;
3115 u32 num_bssid;
3116 u32 num_ssids;
3117 u32 ie_len;
3118 u32 n_probes;
3121 u32 ie_bitmap[WMI_IE_BITMAP_SIZE];
3122 u32 num_vendor_oui;
3123 u32 scan_ctrl_flags_ext;
3124 u32 dwell_time_active_2g;
3125 u32 dwell_time_active_6g;
3126 u32 dwell_time_passive_6g;
3127 u32 scan_start_offset;
3168 u32 freq_flags;
3169 u32 short_ssid;
3173 u32 freq_flags;
3178 u32 scan_id;
3179 u32 scan_req_id;
3180 u32 vdev_id;
3181 u32 pdev_id;
3185 u32 scan_ev_started:1,
3199 u32 scan_events;
3201 u32 dwell_time_active;
3202 u32 dwell_time_active_2g;
3203 u32 dwell_time_passive;
3204 u32 dwell_time_active_6g;
3205 u32 dwell_time_passive_6g;
3206 u32 min_rest_time;
3207 u32 max_rest_time;
3208 u32 repeat_probe_time;
3209 u32 probe_spacing_time;
3210 u32 idle_time;
3211 u32 max_scan_time;
3212 u32 probe_delay;
3215 u32 scan_f_passive:1,
3241 u32 scan_flags;
3244 u32 burst_duration;
3245 u32 num_chan;
3246 u32 num_bssid;
3247 u32 num_ssids;
3248 u32 n_probes;
3249 u32 chan_list[WLAN_SCAN_MAX_NUM_CHANNELS];
3250 u32 notify_scan_events;
3256 u32 num_hint_s_ssid;
3257 u32 num_hint_bssid;
3272 u32 scan_id;
3273 u32 scan_req_id;
3274 u32 vdev_id;
3275 u32 scan_priority;
3276 u32 notify_scan_events;
3277 u32 dwell_time_active;
3278 u32 dwell_time_passive;
3279 u32 min_rest_time;
3280 u32 max_rest_time;
3281 u32 repeat_probe_time;
3282 u32 probe_spacing_time;
3283 u32 idle_time;
3284 u32 max_scan_time;
3285 u32 probe_delay;
3286 u32 scan_ctrl_flags;
3288 u32 ie_len;
3289 u32 n_channels;
3290 u32 n_ssids;
3291 u32 n_bssids;
3294 u32 channels[64];
3315 u32 requester;
3316 u32 scan_id;
3318 u32 vdev_id;
3319 u32 pdev_id;
3323 u32 tlv_header;
3324 u32 vdev_id;
3325 u32 data_len;
3327 u32 frag_ptr;
3328 u32 frag_ptr_lo;
3330 u32 frame_ctrl;
3331 u32 dtim_flag;
3332 u32 bcn_antenna;
3333 u32 frag_ptr_hi;
3360 u32 tlv_header;
3361 u32 mhz;
3362 u32 band_center_freq1;
3363 u32 band_center_freq2;
3364 u32 info;
3365 u32 reg_info_1;
3366 u32 reg_info_2;
3396 u32 tlv_header;
3397 u32 type;
3398 u32 delay_time_ms;
3402 u32 tlv_header;
3403 u32 vdev_id;
3404 u32 param_id;
3405 u32 param_value;
3426 u32 tlv_header;
3428 u32 vdev_id;
3430 u32 pdev_id;
3434 u32 tlv_header;
3435 u32 param;
3436 u32 pdev_id;
3442 u32 tlv_header;
3443 u32 vdev_id;
3444 u32 tim_ie_offset;
3445 u32 buf_len;
3446 u32 csa_switch_count_offset;
3447 u32 ext_csa_switch_count_offset;
3448 u32 csa_event_bitmap;
3449 u32 mbssid_ie_offset;
3450 u32 esp_ie_offset;
3454 u32 key_seq_counter_l;
3455 u32 key_seq_counter_h;
3459 u32 tlv_header;
3460 u32 vdev_id;
3462 u32 key_idx;
3463 u32 key_flags;
3464 u32 key_cipher;
3470 u32 key_len;
3471 u32 key_txmic_len;
3472 u32 key_rxmic_len;
3473 u32 is_group_key_id_valid;
3474 u32 group_key_id;
3482 u32 vdev_id;
3484 u32 key_idx;
3485 u32 key_flags;
3486 u32 key_cipher;
3487 u32 key_len;
3488 u32 key_txmic_len;
3489 u32 key_rxmic_len;
3502 u32 num_rates;
3508 u32 vdev_id;
3509 u32 peer_new_assoc;
3510 u32 peer_associd;
3511 u32 peer_flags;
3512 u32 peer_caps;
3513 u32 peer_listen_intval;
3514 u32 peer_ht_caps;
3515 u32 peer_max_mpdu;
3516 u32 peer_mpdu_density;
3517 u32 peer_rate_caps;
3518 u32 peer_nss;
3519 u32 peer_vht_caps;
3520 u32 peer_phymode;
3521 u32 peer_ht_info[2];
3524 u32 rx_max_rate;
3525 u32 rx_mcs_set;
3526 u32 tx_max_rate;
3527 u32 tx_mcs_set;
3530 u32 tx_max_mcs_nss;
3531 u32 peer_bw_rxnss_override;
3556 u32 peer_he_cap_macinfo[2];
3557 u32 peer_he_cap_macinfo_internal;
3558 u32 peer_he_caps_6ghz;
3559 u32 peer_he_ops;
3560 u32 peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE];
3561 u32 peer_he_mcs_count;
3562 u32 peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3563 u32 peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3570 u32 tlv_header;
3572 u32 vdev_id;
3573 u32 peer_new_assoc;
3574 u32 peer_associd;
3575 u32 peer_flags;
3576 u32 peer_caps;
3577 u32 peer_listen_intval;
3578 u32 peer_ht_caps;
3579 u32 peer_max_mpdu;
3580 u32 peer_mpdu_density;
3581 u32 peer_rate_caps;
3582 u32 peer_nss;
3583 u32 peer_vht_caps;
3584 u32 peer_phymode;
3585 u32 peer_ht_info[2];
3586 u32 num_peer_legacy_rates;
3587 u32 num_peer_ht_rates;
3588 u32 peer_bw_rxnss_override;
3590 u32 peer_he_cap_info;
3591 u32 peer_he_ops;
3592 u32 peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE];
3593 u32 peer_he_mcs;
3594 u32 peer_he_cap_info_ext;
3595 u32 peer_he_cap_info_internal;
3596 u32 min_data_rate;
3597 u32 peer_he_caps_6ghz;
3601 u32 tlv_header;
3602 u32 requestor;
3603 u32 scan_id;
3604 u32 req_type;
3605 u32 vdev_id;
3606 u32 pdev_id;
3610 u32 pdev_id;
3616 u32 tlv_header;
3617 u32 num_scan_chans;
3618 u32 flags;
3619 u32 pdev_id;
3636 u32 tlv_header;
3637 u32 tx_params_dword0;
3638 u32 tx_params_dword1;
3642 u32 tlv_header;
3643 u32 vdev_id;
3644 u32 desc_id;
3645 u32 chanfreq;
3646 u32 paddr_lo;
3647 u32 paddr_hi;
3648 u32 frame_len;
3649 u32 buf_len;
3650 u32 tx_params_valid;
3658 u32 tlv_header;
3659 u32 vdev_id;
3660 u32 sta_ps_mode;
3664 u32 tlv_header;
3665 u32 vdev_id;
3666 u32 forced_mode;
3670 u32 tlv_header;
3671 u32 vdev_id;
3672 u32 param;
3673 u32 value;
3677 u32 tlv_header;
3678 u32 caps;
3679 u32 erp;
3688 u32 value;
3692 u32 tlv_header;
3693 u32 pdev_id;
3694 u32 enable;
3698 u32 vdev_id;
3699 u32 param;
3700 u32 value;
3704 u32 if_id;
3705 u32 param_id;
3706 u32 param_value;
3710 u32 stats_id;
3711 u32 vdev_id;
3712 u32 pdev_id;
3738 u32 tlv_header;
3739 u32 pdev_id;
3740 u32 init_cc_type;
3742 u32 country_code;
3743 u32 regdom_id;
3744 u32 alpha2;
3750 u32 tmplwm;
3751 u32 tmphwm;
3752 u32 dcoffpercent;
3753 u32 priority;
3757 u32 pdev_id;
3758 u32 enable;
3759 u32 dc;
3760 u32 dc_per_event;
3765 u32 tlv_header;
3766 u32 pdev_id;
3767 u32 enable;
3768 u32 dc;
3769 u32 dc_per_event;
3770 u32 therm_throt_levels;
3774 u32 tlv_header;
3775 u32 temp_lwm;
3776 u32 temp_hwm;
3777 u32 dc_off_percent;
3778 u32 prio;
3782 u32 tlv_header;
3783 u32 vdev_id;
3785 u32 tid;
3786 u32 initiator;
3787 u32 reasoncode;
3791 u32 tlv_header;
3792 u32 vdev_id;
3794 u32 tid;
3795 u32 statuscode;
3799 u32 tlv_header;
3800 u32 vdev_id;
3802 u32 tid;
3803 u32 buffersize;
3807 u32 tlv_header;
3808 u32 vdev_id;
3813 u32 tlv_header;
3818 u32 tlv_header;
3819 u32 pdev_id;
3820 u32 enable;
3821 u32 filter_type;
3822 u32 num_mac;
3831 u32 tlv_header;
3832 u32 pdev_id;
3833 u32 evlist; /* WMI_PKTLOG_EVENT */
3834 u32 enable;
3838 u32 tlv_header;
3839 u32 pdev_id;
3854 u32 cmd_id;
3855 u32 pdev_id;
3856 u32 radar_param;
3860 u32 tlv_header;
3861 u32 vdev_id;
3862 u32 module_id;
3863 u32 num_args;
3864 u32 diag_token;
3897 u32 tim_ie_offset;
3898 u32 tmpl_len;
3899 u32 tmpl_len_aligned;
3900 u32 csa_switch_count_offset;
3901 u32 ext_csa_switch_count_offset;
3906 u32 num_rates;
3907 u32 rates[(MAX_SUPPORTED_RATES / 4) + 1];
3911 u32 tlv_header;
3912 u32 rx_max_rate;
3913 u32 rx_mcs_set;
3914 u32 tx_max_rate;
3915 u32 tx_mcs_set;
3916 u32 tx_max_mcs_nss;
3920 u32 tlv_header;
3921 u32 rx_mcs_set;
3922 u32 tx_mcs_set;
3934 u32 vdev_id;
3935 u32 requestor_id;
3937 u32 status;
3938 u32 chain_mask;
3939 u32 smps_mode;
3941 u32 mac_id;
3942 u32 pdev_id;
3944 u32 cfgd_tx_streams;
3945 u32 cfgd_rx_streams;
4005 u32 dfs_region;
4006 u32 phybitmap;
4007 u32 min_bw_2g;
4008 u32 max_bw_2g;
4009 u32 min_bw_5g;
4010 u32 max_bw_5g;
4011 u32 num_2g_reg_rules;
4012 u32 num_5g_reg_rules;
4018 u32 status_code;
4019 u32 phy_id;
4020 u32 alpha2;
4021 u32 num_phy;
4022 u32 country_id;
4023 u32 domain_code;
4024 u32 dfs_region;
4025 u32 phybitmap;
4026 u32 min_bw_2g;
4027 u32 max_bw_2g;
4028 u32 min_bw_5g;
4029 u32 max_bw_5g;
4030 u32 num_2g_reg_rules;
4031 u32 num_5g_reg_rules;
4035 u32 tlv_header;
4036 u32 freq_info;
4037 u32 bw_pwr_info;
4038 u32 flag_info;
4042 u32 vdev_id;
4046 u32 vdev_id;
4051 u32 vdev_id;
4052 u32 tx_status;
4056 u32 vdev_id;
4060 u32 freq; /* Units in MHz */
4061 u32 noise_floor; /* units are dBm */
4063 u32 rx_clear_count_low;
4064 u32 rx_clear_count_high;
4066 u32 cycle_count_low;
4067 u32 cycle_count_high;
4069 u32 tx_cycle_count_low;
4070 u32 tx_cycle_count_high;
4072 u32 rx_cycle_count_low;
4073 u32 rx_cycle_count_high;
4075 u32 rx_bss_cycle_count_low;
4076 u32 rx_bss_cycle_count_high;
4077 u32 pdev_id;
4083 u32 vdev_id;
4085 u32 key_idx;
4086 u32 key_flags;
4087 u32 status;
4091 u32 vdev_id;
4093 u32 key_idx;
4094 u32 key_flags;
4095 u32 status;
4099 u32 vdev_id;
4104 u32 vdev_id;
4109 u32 vdev_id;
4110 u32 fils_tt;
4111 u32 tbtt;
4115 u32 vdev_id;
4116 u32 tx_status;
4124 u32 tx_frame_count; /* Cycles spent transmitting frames */
4125 u32 rx_frame_count; /* Cycles spent receiving frames */
4126 u32 rx_clear_count; /* Total channel busy time, evidently */
4127 u32 cycle_count; /* Total on-channel time */
4128 u32 phy_err_count;
4129 u32 chan_tx_pwr;
4133 u32 ack_rx_bad;
4134 u32 rts_bad;
4135 u32 rts_good;
4136 u32 fcs_bad;
4137 u32 no_beacons;
4138 u32 mib_int_count;
4179 u32 tx_ko;
4182 u32 data_rc;
4185 u32 self_triggers;
4188 u32 sw_retry_failure;
4191 u32 illgl_rate_phy_err;
4194 u32 pdev_cont_xretry;
4197 u32 pdev_tx_timeout;
4200 u32 pdev_resets;
4203 u32 stateless_tid_alloc_failure;
4206 u32 phy_underrun;
4209 u32 txop_ovf;
4257 u32 vdev_id;
4258 u32 beacon_snr;
4259 u32 data_snr;
4260 u32 num_tx_frames[WLAN_MAX_AC];
4261 u32 num_rx_frames;
4262 u32 num_tx_frames_retries[WLAN_MAX_AC];
4263 u32 num_tx_frames_failures[WLAN_MAX_AC];
4264 u32 num_rts_fail;
4265 u32 num_rts_success;
4266 u32 num_rx_err;
4267 u32 num_rx_discard;
4268 u32 num_tx_not_acked;
4269 u32 tx_rate_history[MAX_TX_RATE_VALUES];
4270 u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
4274 u32 vdev_id;
4275 u32 tx_bcn_succ_cnt;
4276 u32 tx_bcn_outage_cnt;
4280 u32 stats_id;
4281 u32 num_pdev_stats;
4282 u32 num_vdev_stats;
4283 u32 num_peer_stats;
4284 u32 num_bcnflt_stats;
4285 u32 num_chan_stats;
4286 u32 num_mib_stats;
4287 u32 pdev_id;
4288 u32 num_bcn_stats;
4289 u32 num_peer_extd_stats;
4290 u32 num_peer_extd2_stats;
4294 u32 pdev_id;
4295 u32 ctl_failsafe_status;
4299 u32 pdev_id;
4300 u32 current_switch_count;
4301 u32 num_vdevs;
4305 u32 pdev_id;
4306 u32 detection_mode;
4307 u32 chan_freq;
4308 u32 chan_width;
4309 u32 detector_id;
4310 u32 segment_id;
4311 u32 timestamp;
4312 u32 is_chirp;
4320 u32 pdev_id;
4332 u32 chan_freq;
4333 u32 channel;
4334 u32 snr;
4336 u32 rate;
4338 u32 buf_len;
4340 u32 flags;
4342 u32 tsf_delta;
4349 u32 channel;
4350 u32 snr;
4351 u32 rate;
4352 u32 phy_mode;
4353 u32 buf_len;
4354 u32 status;
4355 u32 rssi_ctl[ATH_MAX_ANTENNA];
4356 u32 flags;
4358 u32 tsf_delta;
4359 u32 rx_tsf_l32;
4360 u32 rx_tsf_u32;
4361 u32 pdev_id;
4362 u32 chan_freq;
4368 u32 tlv_header;
4369 u32 rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA];
4373 u32 desc_id;
4374 u32 status;
4375 u32 pdev_id;
4379 u32 event_type; /* %WMI_SCAN_EVENT_ */
4380 u32 reason; /* %WMI_SCAN_REASON_ */
4381 u32 channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */
4382 u32 scan_req_id;
4383 u32 scan_id;
4384 u32 vdev_id;
4390 u32 tsf_timestamp;
4413 u32 vdev_id;
4414 u32 reason;
4415 u32 rssi;
4422 u32 err_code;
4423 u32 freq;
4424 u32 cmd_flags;
4425 u32 noise_floor;
4426 u32 rx_clear_count;
4427 u32 cycle_count;
4428 u32 chan_tx_pwr_range;
4429 u32 chan_tx_pwr_tp;
4430 u32 rx_frame_count;
4431 u32 my_bss_rx_cycle_count;
4432 u32 rx_11b_mode_data_duration;
4433 u32 tx_frame_cnt;
4434 u32 mac_clk_mhz;
4435 u32 vdev_id;
4439 u32 phy_capability;
4440 u32 max_frag_entry;
4441 u32 num_rf_chains;
4442 u32 ht_cap_info;
4443 u32 vht_cap_info;
4444 u32 vht_supp_mcs;
4445 u32 hw_min_tx_power;
4446 u32 hw_max_tx_power;
4447 u32 sys_cap_info;
4448 u32 min_pkt_size_enable;
4449 u32 max_bcn_ie_size;
4450 u32 max_num_scan_channels;
4451 u32 max_supported_macs;
4452 u32 wmi_fw_sub_feat_caps;
4453 u32 txrx_chainmask;
4454 u32 default_dbs_hw_mode_index;
4455 u32 num_msdu_desc;
4504 u32 wmm_ac;
4505 u32 user_priority;
4506 u32 service_interval;
4507 u32 suspend_interval;
4508 u32 delay_interval;
4512 u32 vdev_id;
4514 u32 num_ac;
4518 u32 wmm_ac;
4519 u32 user_priority;
4520 u32 service_interval;
4521 u32 suspend_interval;
4522 u32 delay_interval;
4686 u32 eeprom_rd;
4687 u32 eeprom_rd_ext;
4688 u32 regcap1;
4689 u32 regcap2;
4690 u32 wireless_modes;
4691 u32 low_2ghz_chan;
4692 u32 high_2ghz_chan;
4693 u32 low_5ghz_chan;
4694 u32 high_5ghz_chan;
4700 u32 len;
4701 u32 req_id;
4721 u32 tlv_header;
4722 u32 cwmin;
4723 u32 cwmax;
4724 u32 aifs;
4725 u32 txoplimit;
4726 u32 acm;
4727 u32 no_ack;
4740 u32 tlv_header;
4741 u32 vdev_id;
4743 u32 wmm_param_type;
4770 u32 tlv_header;
4771 u32 pdev_id;
4772 u32 sta_cong_timer_ms;
4773 u32 mbss_support;
4774 u32 default_slot_size;
4775 u32 congestion_thresh_setup;
4776 u32 congestion_thresh_teardown;
4777 u32 congestion_thresh_critical;
4778 u32 interference_thresh_teardown;
4779 u32 interference_thresh_setup;
4780 u32 min_no_sta_setup;
4781 u32 min_no_sta_teardown;
4782 u32 no_of_bcast_mcast_slots;
4783 u32 min_no_twt_slots;
4784 u32 max_no_sta_twt;
4785 u32 mode_check_interval;
4786 u32 add_sta_slot_interval;
4787 u32 remove_sta_slot_interval;
4791 u32 tlv_header;
4792 u32 pdev_id;
4796 u32 tlv_header;
4797 u32 pdev_id;
4798 u32 enable;
4801 u32 vdev_id;
4805 u32 tlv_header;
4806 u32 pdev_id;
4807 u32 bitmap[2];
4818 u32 tlv_header;
4819 u32 vdev_id;
4820 u32 flags;
4821 u32 evt_type;
4822 u32 current_bss_color;
4823 u32 detection_period_ms;
4824 u32 scan_period_ms;
4825 u32 free_slot_expiry_time_ms;
4829 u32 tlv_header;
4830 u32 vdev_id;
4831 u32 enable;
4838 u32 tlv_header;
4839 u32 lro_enable;
4840 u32 res;
4841 u32 th_4[ATH11K_IPV4_TH_SEED_SIZE];
4842 u32 th_6[ATH11K_IPV6_TH_SEED_SIZE];
4843 u32 pdev_id;
4866 u32 vdev_id;
4867 u32 scan_count;
4868 u32 scan_period;
4869 u32 scan_priority;
4870 u32 scan_fft_size;
4871 u32 scan_gc_ena;
4872 u32 scan_restart_ena;
4873 u32 scan_noise_floor_ref;
4874 u32 scan_init_delay;
4875 u32 scan_nb_tone_thr;
4876 u32 scan_str_bin_thr;
4877 u32 scan_wb_rpt_mode;
4878 u32 scan_rssi_rpt_mode;
4879 u32 scan_rssi_thr;
4880 u32 scan_pwr_format;
4881 u32 scan_rpt_mode;
4882 u32 scan_bin_scale;
4883 u32 scan_dbm_adj;
4884 u32 scan_chn_mask;
4888 u32 tlv_header;
4898 u32 tlv_header;
4899 u32 vdev_id;
4900 u32 trigger_cmd;
4901 u32 enable_cmd;
4905 u32 tlv_header;
4906 u32 pdev_id;
4907 u32 module_id; /* see enum wmi_direct_buffer_module */
4908 u32 base_paddr_lo;
4909 u32 base_paddr_hi;
4910 u32 head_idx_paddr_lo;
4911 u32 head_idx_paddr_hi;
4912 u32 tail_idx_paddr_lo;
4913 u32 tail_idx_paddr_hi;
4914 u32 num_elems; /* Number of elems in the ring */
4915 u32 buf_size; /* size of allocated buffer in bytes */
4918 u32 num_resp_per_event;
4923 u32 event_timeout_ms;
4927 u32 pdev_id;
4928 u32 module_id;
4929 u32 num_buf_release_entry;
4930 u32 num_meta_data_entry;
4934 u32 tlv_header;
4935 u32 paddr_lo;
4940 u32 paddr_hi;
4949 u32 tlv_header;
4951 u32 reset_delay;
4952 u32 freq1;
4953 u32 freq2;
4954 u32 ch_width;
4963 u32 tlv_header;
4964 u32 vdev_id;
4965 u32 interval;
4966 u32 config; /* enum wmi_fils_discovery_cmd_type */
4970 u32 tlv_header;
4971 u32 vdev_id;
4972 u32 buf_len;
4976 u32 tlv_header;
4977 u32 vdev_id;
4978 u32 buf_len;
4982 u32 num_vdevs;
4983 u32 num_peers;
4984 u32 num_active_peers;
4985 u32 num_offload_peers;
4986 u32 num_offload_reorder_buffs;
4987 u32 num_peer_keys;
4988 u32 num_tids;
4989 u32 ast_skid_limit;
4990 u32 tx_chain_mask;
4991 u32 rx_chain_mask;
4992 u32 rx_timeout_pri[4];
4993 u32 rx_decap_mode;
4994 u32 scan_max_pending_req;
4995 u32 bmiss_offload_max_vdev;
4996 u32 roam_offload_max_vdev;
4997 u32 roam_offload_max_ap_profiles;
4998 u32 num_mcast_groups;
4999 u32 num_mcast_table_elems;
5000 u32 mcast2ucast_mode;
5001 u32 tx_dbg_log_size;
5002 u32 num_wds_entries;
5003 u32 dma_burst_size;
5004 u32 mac_aggr_delim;
5005 u32 rx_skip_defrag_timeout_dup_detection_check;
5006 u32 vow_config;
5007 u32 gtk_offload_max_vdev;
5008 u32 num_msdu_desc;
5009 u32 max_frag_entries;
5010 u32 max_peer_ext_stats;
5011 u32 smart_ant_cap;
5012 u32 bk_minfree;
5013 u32 be_minfree;
5014 u32 vi_minfree;
5015 u32 vo_minfree;
5016 u32 rx_batchmode;
5017 u32 tt_support;
5018 u32 atf_config;
5019 u32 iphdr_pad_config;
5020 u32 qwrap_config:16,
5022 u32 num_tdls_vdevs;
5023 u32 num_tdls_conn_table_entries;
5024 u32 beacon_tx_offload_max_vdev;
5025 u32 num_multicast_filter_entries;
5026 u32 num_wow_filters;
5027 u32 num_keep_alive_pattern;
5028 u32 keep_alive_pattern_size;
5029 u32 max_tdls_concurrent_sleep_sta;
5030 u32 max_tdls_concurrent_buffer_sta;
5031 u32 wmi_send_separate;
5032 u32 num_ocb_vdevs;
5033 u32 num_ocb_channels;
5034 u32 num_ocb_schedules;
5035 u32 num_ns_ext_tuples_cfg;
5036 u32 bpf_instruction_size;
5037 u32 max_bssid_rx_filters;
5038 u32 use_pdev_id;
5039 u32 peer_map_unmap_v2_support;
5040 u32 sched_params;
5041 u32 twt_ap_pdev_count;
5042 u32 twt_ap_sta_count;
5056 u32 max_msg_len[MAX_RADIOS];
5063 u32 num_mem_chunks;
5064 u32 rx_decap_mode;
5218 u32 tlv_header;
5219 u32 enable;
5220 u32 pause_iface_config;
5221 u32 flags;
5225 u32 tlv_header;
5226 u32 reserved;
5230 u32 vdev_id;
5231 u32 flag;
5233 u32 data_len;
5237 u32 cmd_id);
5238 struct sk_buff *ath11k_wmi_alloc_skb(struct ath11k_wmi_base *wmi_sc, u32 len);
5239 int ath11k_wmi_mgmt_send(struct ath11k *ar, u32 vdev_id, u32 buf_id,
5241 int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id,
5245 int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid,
5251 u32 vdev_id, u32 param_id, u32 param_val);
5252 int ath11k_wmi_pdev_set_param(struct ath11k *ar, u32 param_id,
5253 u32 param_value, u8 pdev_id);
5254 int ath11k_wmi_pdev_set_ps_mode(struct ath11k *ar, int vdev_id, u32 enable);
5268 u32 ba_window_size);
5271 int ath11k_wmi_vdev_set_param_cmd(struct ath11k *ar, u32 vdev_id,
5272 u32 param_id, u32 param_value);
5274 int ath11k_wmi_set_sta_ps_param(struct ath11k *ar, u32 vdev_id,
5275 u32 param, u32 param_value);
5276 int ath11k_wmi_force_fw_hang_cmd(struct ath11k *ar, u32 type, u32 delay_time_ms);
5285 int ath11k_wmi_send_wmm_update_cmd_tlv(struct ath11k *ar, u32 vdev_id,
5287 int ath11k_wmi_pdev_suspend(struct ath11k *ar, u32 suspend_opt,
5288 u32 pdev_id);
5289 int ath11k_wmi_pdev_resume(struct ath11k *ar, u32 pdev_id);
5308 u32 pdev_id);
5309 int ath11k_wmi_addba_clear_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac);
5310 int ath11k_wmi_addba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
5311 u32 tid, u32 buf_size);
5312 int ath11k_wmi_addba_set_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac,
5313 u32 tid, u32 status);
5314 int ath11k_wmi_delba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
5315 u32 tid, u32 initiator, u32 reason);
5317 u32 vdev_id, u32 bcn_ctrl_op);
5324 int ath11k_wmi_pdev_pktlog_enable(struct ath11k *ar, u32 pktlog_filter);
5338 struct ath11k_fw_stats *fw_stats, u32 stats_id,
5341 int ath11k_wmi_send_twt_enable_cmd(struct ath11k *ar, u32 pdev_id);
5342 int ath11k_wmi_send_twt_disable_cmd(struct ath11k *ar, u32 pdev_id);
5343 int ath11k_wmi_send_obss_spr_cmd(struct ath11k *ar, u32 vdev_id,
5345 int ath11k_wmi_pdev_set_srg_bss_color_bitmap(struct ath11k *ar, u32 *bitmap);
5346 int ath11k_wmi_pdev_set_srg_patial_bssid_bitmap(struct ath11k *ar, u32 *bitmap);
5348 u32 *bitmap);
5350 u32 *bitmap);
5352 u32 *bitmap);
5354 u32 *bitmap);
5355 int ath11k_wmi_send_obss_color_collision_cfg_cmd(struct ath11k *ar, u32 vdev_id,
5356 u8 bss_color, u32 period,
5358 int ath11k_wmi_send_bss_color_change_enable_cmd(struct ath11k *ar, u32 vdev_id,
5363 int ath11k_wmi_vdev_spectral_enable(struct ath11k *ar, u32 vdev_id,
5364 u32 trigger, u32 enable);
5367 int ath11k_wmi_fils_discovery_tmpl(struct ath11k *ar, u32 vdev_id,
5369 int ath11k_wmi_fils_discovery(struct ath11k *ar, u32 vdev_id, u32 interval,
5371 int ath11k_wmi_probe_resp_tmpl(struct ath11k *ar, u32 vdev_id,