194 		iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id),  in iwl_pcie_rxq_inc_wr_ptr()
197 		iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);  in iwl_pcie_rxq_inc_wr_ptr()
851 	iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);  in iwl_pcie_rx_hw_init()
853 	iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);  in iwl_pcie_rx_hw_init()
854 	iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);  in iwl_pcie_rx_hw_init()
855 	iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);  in iwl_pcie_rx_hw_init()
858 	iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);  in iwl_pcie_rx_hw_init()
861 	iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,  in iwl_pcie_rx_hw_init()
865 	iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,  in iwl_pcie_rx_hw_init()
876 	iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,  in iwl_pcie_rx_hw_init()
1897 	iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);  in iwl_pcie_irq_handler()
1986 			iwl_write32(trans, CSR_FH_INT_STATUS,  in iwl_pcie_irq_handler()
1991 			iwl_write32(trans,  in iwl_pcie_irq_handler()
2032 		iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);  in iwl_pcie_irq_handler()
2141 	iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);  in iwl_pcie_reset_ict()
2144 	iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);  in iwl_pcie_reset_ict()
2171 	iwl_write32(trans, CSR_INT_MASK, 0x00000000);  in iwl_pcie_isr()
2205 	iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh & inta_fh_msk);  in iwl_pcie_irq_msix_handler()
2206 	iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);  in iwl_pcie_irq_msix_handler()