36 		mt76_wr(dev, addr + 4 * i, desc[i]);  in mt7603_set_tmac_template()
59 	mt76_wr(dev, MT_PSE_FRP,  in mt7603_dma_sched_init()
64 	mt76_wr(dev, MT_HIGH_PRIORITY_1, 0x55555553);  in mt7603_dma_sched_init()
65 	mt76_wr(dev, MT_HIGH_PRIORITY_2, 0x78555555);  in mt7603_dma_sched_init()
67 	mt76_wr(dev, MT_QUEUE_PRIORITY_1, 0x2b1a096e);  in mt7603_dma_sched_init()
68 	mt76_wr(dev, MT_QUEUE_PRIORITY_2, 0x785f4d3c);  in mt7603_dma_sched_init()
70 	mt76_wr(dev, MT_PRIORITY_MASK, 0xffffffff);  in mt7603_dma_sched_init()
72 	mt76_wr(dev, MT_SCH_1, page_count | (2 << 28));  in mt7603_dma_sched_init()
73 	mt76_wr(dev, MT_SCH_2, max_amsdu_pages);  in mt7603_dma_sched_init()
76 		mt76_wr(dev, MT_PAGE_COUNT(i), max_amsdu_pages);  in mt7603_dma_sched_init()
79 	mt76_wr(dev, MT_PAGE_COUNT(5), mcu_pages);  in mt7603_dma_sched_init()
82 	mt76_wr(dev, MT_PAGE_COUNT(7), beacon_pages);  in mt7603_dma_sched_init()
85 	mt76_wr(dev, MT_PAGE_COUNT(8), max_mcast_pages);  in mt7603_dma_sched_init()
91 	mt76_wr(dev, MT_RSV_MAX_THRESH, page_count - reserved_count);  in mt7603_dma_sched_init()
94 		mt76_wr(dev, MT_GROUP_THRESH(0),  in mt7603_dma_sched_init()
96 		mt76_wr(dev, MT_GROUP_THRESH(1), beacon_pages);  in mt7603_dma_sched_init()
97 		mt76_wr(dev, MT_BMAP_0, 0x0080ff5f);  in mt7603_dma_sched_init()
98 		mt76_wr(dev, MT_GROUP_THRESH(2), mcu_pages);  in mt7603_dma_sched_init()
99 		mt76_wr(dev, MT_BMAP_1, 0x00000020);  in mt7603_dma_sched_init()
101 		mt76_wr(dev, MT_GROUP_THRESH(0), page_count);  in mt7603_dma_sched_init()
102 		mt76_wr(dev, MT_BMAP_0, 0xffff);  in mt7603_dma_sched_init()
105 	mt76_wr(dev, MT_SCH_4, 0);  in mt7603_dma_sched_init()
108 		mt76_wr(dev, MT_TXTIME_THRESH(i), 0xfffff);  in mt7603_dma_sched_init()
139 	mt76_wr(dev, MT_AGG_BA_SIZE_LIMIT_0,  in mt7603_mac_init()
145 	mt76_wr(dev, MT_AGG_BA_SIZE_LIMIT_1,  in mt7603_mac_init()
151 	mt76_wr(dev, MT_AGG_LIMIT,  in mt7603_mac_init()
157 	mt76_wr(dev, MT_AGG_LIMIT_1,  in mt7603_mac_init()
163 	mt76_wr(dev, MT_AGG_CONTROL,  in mt7603_mac_init()
168 	mt76_wr(dev, MT_AGG_RETRY_CONTROL,  in mt7603_mac_init()
172 	mt76_wr(dev, MT_DMA_DCR0, MT_DMA_DCR0_RX_VEC_DROP |  in mt7603_mac_init()
183 	mt76_wr(dev, MT_WF_RFCR1, 0);  in mt7603_mac_init()
202 	mt76_wr(dev, MT_RXREQ, 4);  in mt7603_mac_init()
205 	mt76_wr(dev, MT_DMA_RCFR0, 0xc0000000);  in mt7603_mac_init()
208 	mt76_wr(dev, MT_DMA_TCFR0,  in mt7603_mac_init()
213 	mt76_wr(dev, MT_DMA_TCFR1,  in mt7603_mac_init()
218 	mt76_wr(dev, MT_MCU_PCIE_REMAP_1, MT_PSE_WTBL_2_PHYS_ADDR);  in mt7603_mac_init()
232 	mt76_wr(dev, MT_AGG_ARUCR,  in mt7603_mac_init()
242 	mt76_wr(dev, MT_AGG_ARDCR,  in mt7603_mac_init()
252 	mt76_wr(dev, MT_AGG_ARCR,  in mt7603_mac_init()
274 	mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);  in mt7603_init_hardware()
284 	mt76_wr(dev, MT_WPDMA_GLO_CFG, 0x52000850);  in mt7603_init_hardware()
290 		mt76_wr(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY | MT_PSE_RTA_WRITE |  in mt7603_init_hardware()
345 	mt76_wr(dev, addr, val);  in mt7603_led_set_config()
347 	mt76_wr(dev, addr, val);  in mt7603_led_set_config()
354 	mt76_wr(dev, addr, val);  in mt7603_led_set_config()