Lines Matching refs:priv
482 rtl8192e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) in rtl8192e_set_tx_power() argument
491 cck = priv->cck_tx_power_index_A[group]; in rtl8192e_set_tx_power()
493 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8192e_set_tx_power()
496 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8192e_set_tx_power()
498 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8192e_set_tx_power()
501 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8192e_set_tx_power()
503 ofdmbase = priv->ht40_1s_tx_power_index_A[group]; in rtl8192e_set_tx_power()
504 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a; in rtl8192e_set_tx_power()
507 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); in rtl8192e_set_tx_power()
508 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); in rtl8192e_set_tx_power()
510 mcsbase = priv->ht40_1s_tx_power_index_A[group]; in rtl8192e_set_tx_power()
512 mcsbase += priv->ht40_tx_power_diff[tx_idx++].a; in rtl8192e_set_tx_power()
514 mcsbase += priv->ht20_tx_power_diff[tx_idx++].a; in rtl8192e_set_tx_power()
517 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); in rtl8192e_set_tx_power()
518 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); in rtl8192e_set_tx_power()
519 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); in rtl8192e_set_tx_power()
520 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); in rtl8192e_set_tx_power()
522 if (priv->tx_paths > 1) { in rtl8192e_set_tx_power()
523 cck = priv->cck_tx_power_index_B[group]; in rtl8192e_set_tx_power()
525 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); in rtl8192e_set_tx_power()
528 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); in rtl8192e_set_tx_power()
530 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8192e_set_tx_power()
533 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8192e_set_tx_power()
535 ofdmbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8192e_set_tx_power()
536 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; in rtl8192e_set_tx_power()
540 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm); in rtl8192e_set_tx_power()
541 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm); in rtl8192e_set_tx_power()
543 mcsbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8192e_set_tx_power()
545 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; in rtl8192e_set_tx_power()
547 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; in rtl8192e_set_tx_power()
550 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs); in rtl8192e_set_tx_power()
551 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs); in rtl8192e_set_tx_power()
552 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs); in rtl8192e_set_tx_power()
553 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs); in rtl8192e_set_tx_power()
557 static void rtl8192eu_log_next_device_info(struct rtl8xxxu_priv *priv, in rtl8192eu_log_next_device_info() argument
572 dev_warn(&priv->udev->dev, in rtl8192eu_log_next_device_info()
583 dev_info(&priv->udev->dev, "%s: %s\n", record_name, value); in rtl8192eu_log_next_device_info()
586 dev_info(&priv->udev->dev, "%s not available.\n", record_name); in rtl8192eu_log_next_device_info()
590 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv) in rtl8192eu_parse_efuse() argument
592 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu; in rtl8192eu_parse_efuse()
599 ether_addr_copy(priv->mac_addr, efuse->mac_addr); in rtl8192eu_parse_efuse()
601 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, in rtl8192eu_parse_efuse()
603 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, in rtl8192eu_parse_efuse()
606 memcpy(priv->ht40_1s_tx_power_index_A, in rtl8192eu_parse_efuse()
609 memcpy(priv->ht40_1s_tx_power_index_B, in rtl8192eu_parse_efuse()
613 priv->ht20_tx_power_diff[0].a = in rtl8192eu_parse_efuse()
615 priv->ht20_tx_power_diff[0].b = in rtl8192eu_parse_efuse()
618 priv->ht40_tx_power_diff[0].a = 0; in rtl8192eu_parse_efuse()
619 priv->ht40_tx_power_diff[0].b = 0; in rtl8192eu_parse_efuse()
622 priv->ofdm_tx_power_diff[i].a = in rtl8192eu_parse_efuse()
624 priv->ofdm_tx_power_diff[i].b = in rtl8192eu_parse_efuse()
627 priv->ht20_tx_power_diff[i].a = in rtl8192eu_parse_efuse()
629 priv->ht20_tx_power_diff[i].b = in rtl8192eu_parse_efuse()
632 priv->ht40_tx_power_diff[i].a = in rtl8192eu_parse_efuse()
634 priv->ht40_tx_power_diff[i].b = in rtl8192eu_parse_efuse()
638 priv->has_xtalk = 1; in rtl8192eu_parse_efuse()
639 priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f; in rtl8192eu_parse_efuse()
657 rtl8192eu_log_next_device_info(priv, "Vendor", efuse->device_info, &record_offset); in rtl8192eu_parse_efuse()
658 rtl8192eu_log_next_device_info(priv, "Product", efuse->device_info, &record_offset); in rtl8192eu_parse_efuse()
659 rtl8192eu_log_next_device_info(priv, "Serial", efuse->device_info, &record_offset); in rtl8192eu_parse_efuse()
662 unsigned char *raw = priv->efuse_wifi.raw; in rtl8192eu_parse_efuse()
664 dev_info(&priv->udev->dev, in rtl8192eu_parse_efuse()
668 dev_info(&priv->udev->dev, "%02x: %8ph\n", i, &raw[i]); in rtl8192eu_parse_efuse()
673 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv) in rtl8192eu_load_firmware() argument
680 ret = rtl8xxxu_load_firmware(priv, fw_name); in rtl8192eu_load_firmware()
685 static void rtl8192eu_init_phy_bb(struct rtl8xxxu_priv *priv) in rtl8192eu_init_phy_bb() argument
690 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8192eu_init_phy_bb()
692 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8192eu_init_phy_bb()
696 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); in rtl8192eu_init_phy_bb()
698 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8192eu_init_phy_bb()
701 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8192eu_init_phy_bb()
703 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); in rtl8192eu_init_phy_bb()
704 rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table); in rtl8192eu_init_phy_bb()
706 if (priv->hi_pa) in rtl8192eu_init_phy_bb()
707 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_highpa_table); in rtl8192eu_init_phy_bb()
709 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_std_table); in rtl8192eu_init_phy_bb()
712 static int rtl8192eu_init_phy_rf(struct rtl8xxxu_priv *priv) in rtl8192eu_init_phy_rf() argument
716 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radioa_init_table, RF_A); in rtl8192eu_init_phy_rf()
720 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radiob_init_table, RF_B); in rtl8192eu_init_phy_rf()
726 static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv) in rtl8192eu_iqk_path_a() argument
735 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_iqk_path_a()
736 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00180); in rtl8192eu_iqk_path_a()
737 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_iqk_path_a()
740 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8192eu_iqk_path_a()
741 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_iqk_path_a()
742 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_iqk_path_a()
743 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_iqk_path_a()
745 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140303); in rtl8192eu_iqk_path_a()
746 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160000); in rtl8192eu_iqk_path_a()
749 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); in rtl8192eu_iqk_path_a()
752 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8192eu_iqk_path_a()
753 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_iqk_path_a()
758 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_iqk_path_a()
759 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8192eu_iqk_path_a()
760 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8192eu_iqk_path_a()
770 static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) in rtl8192eu_rx_iqk_path_a() argument
776 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00); in rtl8192eu_rx_iqk_path_a()
779 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_a()
780 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_a()
781 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_a()
782 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf117b); in rtl8192eu_rx_iqk_path_a()
785 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980); in rtl8192eu_rx_iqk_path_a()
786 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000); in rtl8192eu_rx_iqk_path_a()
789 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_a()
792 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192eu_rx_iqk_path_a()
793 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_rx_iqk_path_a()
796 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8192eu_rx_iqk_path_a()
797 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
798 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
799 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
801 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f); in rtl8192eu_rx_iqk_path_a()
802 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160c1f); in rtl8192eu_rx_iqk_path_a()
805 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); in rtl8192eu_rx_iqk_path_a()
808 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); in rtl8192eu_rx_iqk_path_a()
809 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_rx_iqk_path_a()
814 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_rx_iqk_path_a()
815 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8192eu_rx_iqk_path_a()
816 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8192eu_rx_iqk_path_a()
824 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
825 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); in rtl8192eu_rx_iqk_path_a()
831 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192eu_rx_iqk_path_a()
834 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
836 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_a()
837 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_a()
838 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_a()
839 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ffa); in rtl8192eu_rx_iqk_path_a()
842 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980); in rtl8192eu_rx_iqk_path_a()
843 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000); in rtl8192eu_rx_iqk_path_a()
846 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_a()
849 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_rx_iqk_path_a()
852 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
853 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); in rtl8192eu_rx_iqk_path_a()
854 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
855 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
857 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f); in rtl8192eu_rx_iqk_path_a()
858 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f); in rtl8192eu_rx_iqk_path_a()
861 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); in rtl8192eu_rx_iqk_path_a()
864 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); in rtl8192eu_rx_iqk_path_a()
865 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_rx_iqk_path_a()
869 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_rx_iqk_path_a()
870 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); in rtl8192eu_rx_iqk_path_a()
872 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
873 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); in rtl8192eu_rx_iqk_path_a()
880 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", in rtl8192eu_rx_iqk_path_a()
887 static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv) in rtl8192eu_iqk_path_b() argument
892 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_iqk_path_b()
893 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00180); in rtl8192eu_iqk_path_b()
894 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_iqk_path_b()
896 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_iqk_path_b()
897 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_iqk_path_b()
900 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_iqk_path_b()
901 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_iqk_path_b()
902 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); in rtl8192eu_iqk_path_b()
903 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_iqk_path_b()
905 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x821403e2); in rtl8192eu_iqk_path_b()
906 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000); in rtl8192eu_iqk_path_b()
909 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00492911); in rtl8192eu_iqk_path_b()
912 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); in rtl8192eu_iqk_path_b()
913 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_iqk_path_b()
918 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_iqk_path_b()
919 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192eu_iqk_path_b()
920 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192eu_iqk_path_b()
927 dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n", in rtl8192eu_iqk_path_b()
933 static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) in rtl8192eu_rx_iqk_path_b() argument
939 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_b()
942 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_b()
943 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_b()
944 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_b()
945 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf117b); in rtl8192eu_rx_iqk_path_b()
948 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980); in rtl8192eu_rx_iqk_path_b()
949 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000); in rtl8192eu_rx_iqk_path_b()
952 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_b()
955 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192eu_rx_iqk_path_b()
956 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_rx_iqk_path_b()
959 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
960 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
961 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); in rtl8192eu_rx_iqk_path_b()
962 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
964 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160c1f); in rtl8192eu_rx_iqk_path_b()
965 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160c1f); in rtl8192eu_rx_iqk_path_b()
968 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); in rtl8192eu_rx_iqk_path_b()
971 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); in rtl8192eu_rx_iqk_path_b()
972 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_rx_iqk_path_b()
977 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_rx_iqk_path_b()
978 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192eu_rx_iqk_path_b()
979 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192eu_rx_iqk_path_b()
990 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_b()
991 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180); in rtl8192eu_rx_iqk_path_b()
997 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192eu_rx_iqk_path_b()
1000 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_b()
1002 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_b()
1003 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_b()
1004 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_b()
1005 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ffa); in rtl8192eu_rx_iqk_path_b()
1008 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980); in rtl8192eu_rx_iqk_path_b()
1009 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000); in rtl8192eu_rx_iqk_path_b()
1012 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_b()
1015 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_rx_iqk_path_b()
1018 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
1019 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
1020 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
1021 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c); in rtl8192eu_rx_iqk_path_b()
1023 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f); in rtl8192eu_rx_iqk_path_b()
1024 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f); in rtl8192eu_rx_iqk_path_b()
1027 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); in rtl8192eu_rx_iqk_path_b()
1030 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); in rtl8192eu_rx_iqk_path_b()
1031 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_rx_iqk_path_b()
1035 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_rx_iqk_path_b()
1036 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); in rtl8192eu_rx_iqk_path_b()
1037 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); in rtl8192eu_rx_iqk_path_b()
1039 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_b()
1040 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180); in rtl8192eu_rx_iqk_path_b()
1047 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", in rtl8192eu_rx_iqk_path_b()
1054 static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, in rtl8192eu_phy_iqcalibrate() argument
1057 struct device *dev = &priv->udev->dev; in rtl8192eu_phy_iqcalibrate()
1081 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; in rtl8192eu_phy_iqcalibrate()
1082 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; in rtl8192eu_phy_iqcalibrate()
1091 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, in rtl8192eu_phy_iqcalibrate()
1093 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8192eu_phy_iqcalibrate()
1094 rtl8xxxu_save_regs(priv, iqk_bb_regs, in rtl8192eu_phy_iqcalibrate()
1095 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8192eu_phy_iqcalibrate()
1098 rtl8xxxu_path_adda_on(priv, adda_regs, true); in rtl8192eu_phy_iqcalibrate()
1101 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); in rtl8192eu_phy_iqcalibrate()
1103 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); in rtl8192eu_phy_iqcalibrate()
1105 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); in rtl8192eu_phy_iqcalibrate()
1107 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); in rtl8192eu_phy_iqcalibrate()
1108 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); in rtl8192eu_phy_iqcalibrate()
1109 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200); in rtl8192eu_phy_iqcalibrate()
1111 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); in rtl8192eu_phy_iqcalibrate()
1113 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); in rtl8192eu_phy_iqcalibrate()
1115 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); in rtl8192eu_phy_iqcalibrate()
1117 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); in rtl8192eu_phy_iqcalibrate()
1118 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8192eu_phy_iqcalibrate()
1120 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); in rtl8192eu_phy_iqcalibrate()
1122 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_phy_iqcalibrate()
1123 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192eu_phy_iqcalibrate()
1124 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_phy_iqcalibrate()
1127 path_a_ok = rtl8192eu_iqk_path_a(priv); in rtl8192eu_phy_iqcalibrate()
1129 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1132 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1144 path_a_ok = rtl8192eu_rx_iqk_path_a(priv); in rtl8192eu_phy_iqcalibrate()
1146 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1149 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1160 if (priv->rf_paths > 1) { in rtl8192eu_phy_iqcalibrate()
1162 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_phy_iqcalibrate()
1163 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); in rtl8192eu_phy_iqcalibrate()
1164 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_phy_iqcalibrate()
1167 rtl8xxxu_path_adda_on(priv, adda_regs, false); in rtl8192eu_phy_iqcalibrate()
1169 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_phy_iqcalibrate()
1170 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192eu_phy_iqcalibrate()
1171 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_phy_iqcalibrate()
1174 path_b_ok = rtl8192eu_iqk_path_b(priv); in rtl8192eu_phy_iqcalibrate()
1176 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192eu_phy_iqcalibrate()
1178 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192eu_phy_iqcalibrate()
1188 path_b_ok = rtl8192eu_rx_iqk_path_b(priv); in rtl8192eu_phy_iqcalibrate()
1190 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1193 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1205 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_phy_iqcalibrate()
1209 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, in rtl8192eu_phy_iqcalibrate()
1213 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8192eu_phy_iqcalibrate()
1216 rtl8xxxu_restore_regs(priv, iqk_bb_regs, in rtl8192eu_phy_iqcalibrate()
1217 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8192eu_phy_iqcalibrate()
1220 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8192eu_phy_iqcalibrate()
1222 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); in rtl8192eu_phy_iqcalibrate()
1223 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); in rtl8192eu_phy_iqcalibrate()
1225 if (priv->rf_paths > 1) { in rtl8192eu_phy_iqcalibrate()
1226 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); in rtl8192eu_phy_iqcalibrate()
1228 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, in rtl8192eu_phy_iqcalibrate()
1230 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, in rtl8192eu_phy_iqcalibrate()
1235 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); in rtl8192eu_phy_iqcalibrate()
1236 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); in rtl8192eu_phy_iqcalibrate()
1240 static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) in rtl8192eu_phy_iq_calibrate() argument
1242 struct device *dev = &priv->udev->dev; in rtl8192eu_phy_iq_calibrate()
1257 rtl8192eu_phy_iqcalibrate(priv, result, i); in rtl8192eu_phy_iq_calibrate()
1260 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8192eu_phy_iq_calibrate()
1269 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8192eu_phy_iq_calibrate()
1276 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8192eu_phy_iq_calibrate()
1296 priv->rege94 = reg_e94; in rtl8192eu_phy_iq_calibrate()
1298 priv->rege9c = reg_e9c; in rtl8192eu_phy_iq_calibrate()
1302 priv->regeb4 = reg_eb4; in rtl8192eu_phy_iq_calibrate()
1304 priv->regebc = reg_ebc; in rtl8192eu_phy_iq_calibrate()
1315 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; in rtl8192eu_phy_iq_calibrate()
1316 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; in rtl8192eu_phy_iq_calibrate()
1320 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, in rtl8192eu_phy_iq_calibrate()
1323 if (priv->rf_paths > 1) in rtl8192eu_phy_iq_calibrate()
1324 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, in rtl8192eu_phy_iq_calibrate()
1327 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, in rtl8192eu_phy_iq_calibrate()
1328 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); in rtl8192eu_phy_iq_calibrate()
1334 static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv) in rtl8192e_crystal_afe_adjust() argument
1342 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); in rtl8192e_crystal_afe_adjust()
1344 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); in rtl8192e_crystal_afe_adjust()
1346 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); in rtl8192e_crystal_afe_adjust()
1348 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); in rtl8192e_crystal_afe_adjust()
1354 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); in rtl8192e_crystal_afe_adjust()
1356 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); in rtl8192e_crystal_afe_adjust()
1361 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); in rtl8192e_crystal_afe_adjust()
1363 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); in rtl8192e_crystal_afe_adjust()
1366 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv) in rtl8192e_disabled_to_emu() argument
1371 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192e_disabled_to_emu()
1373 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192e_disabled_to_emu()
1376 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv) in rtl8192e_emu_to_active() argument
1383 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192e_emu_to_active()
1385 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192e_emu_to_active()
1388 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192e_emu_to_active()
1390 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192e_emu_to_active()
1393 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192e_emu_to_active()
1395 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192e_emu_to_active()
1399 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1414 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); in rtl8192e_emu_to_active()
1416 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); in rtl8192e_emu_to_active()
1419 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1421 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8192e_emu_to_active()
1424 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1441 static int rtl8192eu_active_to_lps(struct rtl8xxxu_priv *priv) in rtl8192eu_active_to_lps() argument
1443 struct device *dev = &priv->udev->dev; in rtl8192eu_active_to_lps()
1449 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); in rtl8192eu_active_to_lps()
1457 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); in rtl8192eu_active_to_lps()
1471 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); in rtl8192eu_active_to_lps()
1473 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); in rtl8192eu_active_to_lps()
1478 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); in rtl8192eu_active_to_lps()
1480 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); in rtl8192eu_active_to_lps()
1483 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8192eu_active_to_lps()
1486 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8192eu_active_to_lps()
1488 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8192eu_active_to_lps()
1490 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8192eu_active_to_lps()
1492 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); in rtl8192eu_active_to_lps()
1494 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); in rtl8192eu_active_to_lps()
1500 static int rtl8192eu_active_to_emu(struct rtl8xxxu_priv *priv) in rtl8192eu_active_to_emu() argument
1506 val8 = rtl8xxxu_read8(priv, REG_RF_CTRL); in rtl8192eu_active_to_emu()
1508 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); in rtl8192eu_active_to_emu()
1511 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); in rtl8192eu_active_to_emu()
1513 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); in rtl8192eu_active_to_emu()
1516 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192eu_active_to_emu()
1518 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192eu_active_to_emu()
1521 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192eu_active_to_emu()
1528 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", in rtl8192eu_active_to_emu()
1538 static int rtl8192eu_emu_to_disabled(struct rtl8xxxu_priv *priv) in rtl8192eu_emu_to_disabled() argument
1543 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192eu_emu_to_disabled()
1546 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192eu_emu_to_disabled()
1551 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv) in rtl8192eu_power_on() argument
1557 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); in rtl8192eu_power_on()
1559 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3); in rtl8192eu_power_on()
1564 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL); in rtl8192eu_power_on()
1567 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32); in rtl8192eu_power_on()
1568 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83); in rtl8192eu_power_on()
1574 rtl8192e_crystal_afe_adjust(priv); in rtl8192eu_power_on()
1575 rtl8192e_disabled_to_emu(priv); in rtl8192eu_power_on()
1577 ret = rtl8192e_emu_to_active(priv); in rtl8192eu_power_on()
1581 rtl8xxxu_write16(priv, REG_CR, 0x0000); in rtl8192eu_power_on()
1587 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8192eu_power_on()
1593 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8192eu_power_on()
1599 static void rtl8192eu_power_off(struct rtl8xxxu_priv *priv) in rtl8192eu_power_off() argument
1604 rtl8xxxu_flush_fifo(priv); in rtl8192eu_power_off()
1606 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); in rtl8192eu_power_off()
1608 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); in rtl8192eu_power_off()
1611 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); in rtl8192eu_power_off()
1613 rtl8192eu_active_to_lps(priv); in rtl8192eu_power_off()
1616 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) in rtl8192eu_power_off()
1617 rtl8xxxu_firmware_self_reset(priv); in rtl8192eu_power_off()
1620 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8192eu_power_off()
1622 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8192eu_power_off()
1625 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); in rtl8192eu_power_off()
1627 rtl8xxxu_reset_8051(priv); in rtl8192eu_power_off()
1629 rtl8192eu_active_to_emu(priv); in rtl8192eu_power_off()
1630 rtl8192eu_emu_to_disabled(priv); in rtl8192eu_power_off()
1633 static void rtl8192e_enable_rf(struct rtl8xxxu_priv *priv) in rtl8192e_enable_rf() argument
1638 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); in rtl8192e_enable_rf()
1640 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); in rtl8192e_enable_rf()
1642 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); in rtl8192e_enable_rf()
1644 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); in rtl8192e_enable_rf()
1649 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); in rtl8192e_enable_rf()
1651 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); in rtl8192e_enable_rf()
1653 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8192e_enable_rf()
1655 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8192e_enable_rf()
1657 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8192e_enable_rf()
1659 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77); in rtl8192e_enable_rf()
1661 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8192e_enable_rf()
1664 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8192e_enable_rf()
1669 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); in rtl8192e_enable_rf()
1671 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); in rtl8192e_enable_rf()
1676 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); in rtl8192e_enable_rf()