Lines Matching refs:priv
307 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data) in rtl8723bu_write_btreg() argument
317 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); in rtl8723bu_write_btreg()
325 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); in rtl8723bu_write_btreg()
328 static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv) in rtl8723bu_reset_8051() argument
333 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); in rtl8723bu_reset_8051()
335 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); in rtl8723bu_reset_8051()
337 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); in rtl8723bu_reset_8051()
339 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); in rtl8723bu_reset_8051()
341 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8723bu_reset_8051()
343 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); in rtl8723bu_reset_8051()
345 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); in rtl8723bu_reset_8051()
347 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); in rtl8723bu_reset_8051()
349 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); in rtl8723bu_reset_8051()
351 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); in rtl8723bu_reset_8051()
354 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); in rtl8723bu_reset_8051()
358 rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) in rtl8723b_set_tx_power() argument
367 cck = priv->cck_tx_power_index_B[group]; in rtl8723b_set_tx_power()
368 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8723b_set_tx_power()
371 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8723b_set_tx_power()
373 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8723b_set_tx_power()
376 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8723b_set_tx_power()
378 ofdmbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8723b_set_tx_power()
379 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; in rtl8723b_set_tx_power()
382 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); in rtl8723b_set_tx_power()
383 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); in rtl8723b_set_tx_power()
385 mcsbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8723b_set_tx_power()
387 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; in rtl8723b_set_tx_power()
389 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; in rtl8723b_set_tx_power()
392 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); in rtl8723b_set_tx_power()
393 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); in rtl8723b_set_tx_power()
396 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv) in rtl8723bu_parse_efuse() argument
398 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu; in rtl8723bu_parse_efuse()
404 ether_addr_copy(priv->mac_addr, efuse->mac_addr); in rtl8723bu_parse_efuse()
406 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, in rtl8723bu_parse_efuse()
408 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, in rtl8723bu_parse_efuse()
411 memcpy(priv->ht40_1s_tx_power_index_A, in rtl8723bu_parse_efuse()
414 memcpy(priv->ht40_1s_tx_power_index_B, in rtl8723bu_parse_efuse()
418 priv->ofdm_tx_power_diff[0].a = in rtl8723bu_parse_efuse()
420 priv->ofdm_tx_power_diff[0].b = in rtl8723bu_parse_efuse()
423 priv->ht20_tx_power_diff[0].a = in rtl8723bu_parse_efuse()
425 priv->ht20_tx_power_diff[0].b = in rtl8723bu_parse_efuse()
428 priv->ht40_tx_power_diff[0].a = 0; in rtl8723bu_parse_efuse()
429 priv->ht40_tx_power_diff[0].b = 0; in rtl8723bu_parse_efuse()
432 priv->ofdm_tx_power_diff[i].a = in rtl8723bu_parse_efuse()
434 priv->ofdm_tx_power_diff[i].b = in rtl8723bu_parse_efuse()
437 priv->ht20_tx_power_diff[i].a = in rtl8723bu_parse_efuse()
439 priv->ht20_tx_power_diff[i].b = in rtl8723bu_parse_efuse()
442 priv->ht40_tx_power_diff[i].a = in rtl8723bu_parse_efuse()
444 priv->ht40_tx_power_diff[i].b = in rtl8723bu_parse_efuse()
448 priv->has_xtalk = 1; in rtl8723bu_parse_efuse()
449 priv->xtalk = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f; in rtl8723bu_parse_efuse()
451 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name); in rtl8723bu_parse_efuse()
452 dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name); in rtl8723bu_parse_efuse()
456 unsigned char *raw = priv->efuse_wifi.raw; in rtl8723bu_parse_efuse()
458 dev_info(&priv->udev->dev, in rtl8723bu_parse_efuse()
462 dev_info(&priv->udev->dev, "%02x: %8ph\n", i, &raw[i]); in rtl8723bu_parse_efuse()
468 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv) in rtl8723bu_load_firmware() argument
473 if (priv->enable_bluetooth) in rtl8723bu_load_firmware()
478 ret = rtl8xxxu_load_firmware(priv, fw_name); in rtl8723bu_load_firmware()
482 static void rtl8723bu_init_phy_bb(struct rtl8xxxu_priv *priv) in rtl8723bu_init_phy_bb() argument
487 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8723bu_init_phy_bb()
489 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8723bu_init_phy_bb()
491 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); in rtl8723bu_init_phy_bb()
495 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); in rtl8723bu_init_phy_bb()
498 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3); in rtl8723bu_init_phy_bb()
499 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl8723bu_init_phy_bb()
500 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table); in rtl8723bu_init_phy_bb()
502 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table); in rtl8723bu_init_phy_bb()
505 static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv) in rtl8723bu_init_phy_rf() argument
509 ret = rtl8xxxu_init_phy_rf(priv, rtl8723bu_radioa_1t_init_table, RF_A); in rtl8723bu_init_phy_rf()
513 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0); in rtl8723bu_init_phy_rf()
514 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01); in rtl8723bu_init_phy_rf()
516 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0); in rtl8723bu_init_phy_rf()
521 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv) in rtl8723bu_phy_init_antenna_selection() argument
525 val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1); in rtl8723bu_phy_init_antenna_selection()
527 rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32); in rtl8723bu_phy_init_antenna_selection()
529 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); in rtl8723bu_phy_init_antenna_selection()
531 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); in rtl8723bu_phy_init_antenna_selection()
533 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); in rtl8723bu_phy_init_antenna_selection()
535 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); in rtl8723bu_phy_init_antenna_selection()
537 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723bu_phy_init_antenna_selection()
539 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_phy_init_antenna_selection()
541 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723bu_phy_init_antenna_selection()
543 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_phy_init_antenna_selection()
545 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8723bu_phy_init_antenna_selection()
547 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8723bu_phy_init_antenna_selection()
549 val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC); in rtl8723bu_phy_init_antenna_selection()
552 rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32); in rtl8723bu_phy_init_antenna_selection()
554 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); in rtl8723bu_phy_init_antenna_selection()
556 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8723bu_phy_init_antenna_selection()
559 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv) in rtl8723bu_iqk_path_a() argument
564 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); in rtl8723bu_iqk_path_a()
569 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
571 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
576 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_iqk_path_a()
578 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_iqk_path_a()
579 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); in rtl8723bu_iqk_path_a()
580 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f); in rtl8723bu_iqk_path_a()
581 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87); in rtl8723bu_iqk_path_a()
586 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8723bu_iqk_path_a()
587 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8723bu_iqk_path_a()
590 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8723bu_iqk_path_a()
591 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8723bu_iqk_path_a()
592 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_iqk_path_a()
593 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_iqk_path_a()
595 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea); in rtl8723bu_iqk_path_a()
596 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); in rtl8723bu_iqk_path_a()
597 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); in rtl8723bu_iqk_path_a()
598 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); in rtl8723bu_iqk_path_a()
601 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); in rtl8723bu_iqk_path_a()
606 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
609 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
615 if (priv->rf_paths > 1) in rtl8723bu_iqk_path_a()
616 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); in rtl8723bu_iqk_path_a()
618 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); in rtl8723bu_iqk_path_a()
624 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); in rtl8723bu_iqk_path_a()
627 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8723bu_iqk_path_a()
628 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8723bu_iqk_path_a()
633 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); in rtl8723bu_iqk_path_a()
636 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); in rtl8723bu_iqk_path_a()
642 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
644 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
647 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8723bu_iqk_path_a()
648 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8723bu_iqk_path_a()
649 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8723bu_iqk_path_a()
669 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) in rtl8723bu_rx_iqk_path_a() argument
674 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); in rtl8723bu_rx_iqk_path_a()
679 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
681 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
686 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_rx_iqk_path_a()
688 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_rx_iqk_path_a()
689 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8723bu_rx_iqk_path_a()
690 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); in rtl8723bu_rx_iqk_path_a()
691 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); in rtl8723bu_rx_iqk_path_a()
696 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8723bu_rx_iqk_path_a()
697 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8723bu_rx_iqk_path_a()
700 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8723bu_rx_iqk_path_a()
701 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
702 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
703 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
705 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0); in rtl8723bu_rx_iqk_path_a()
706 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); in rtl8723bu_rx_iqk_path_a()
707 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); in rtl8723bu_rx_iqk_path_a()
708 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); in rtl8723bu_rx_iqk_path_a()
711 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); in rtl8723bu_rx_iqk_path_a()
716 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
719 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
725 if (priv->rf_paths > 1) in rtl8723bu_rx_iqk_path_a()
726 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); in rtl8723bu_rx_iqk_path_a()
728 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); in rtl8723bu_rx_iqk_path_a()
734 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); in rtl8723bu_rx_iqk_path_a()
737 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8723bu_rx_iqk_path_a()
738 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8723bu_rx_iqk_path_a()
743 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); in rtl8723bu_rx_iqk_path_a()
746 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); in rtl8723bu_rx_iqk_path_a()
752 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
754 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
757 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8723bu_rx_iqk_path_a()
758 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8723bu_rx_iqk_path_a()
759 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8723bu_rx_iqk_path_a()
777 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8723bu_rx_iqk_path_a()
782 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
784 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
785 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_rx_iqk_path_a()
787 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_rx_iqk_path_a()
788 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8723bu_rx_iqk_path_a()
789 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); in rtl8723bu_rx_iqk_path_a()
790 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77); in rtl8723bu_rx_iqk_path_a()
795 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80); in rtl8723bu_rx_iqk_path_a()
796 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f); in rtl8723bu_rx_iqk_path_a()
801 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8723bu_rx_iqk_path_a()
804 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
805 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); in rtl8723bu_rx_iqk_path_a()
806 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
807 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
809 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000); in rtl8723bu_rx_iqk_path_a()
810 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f); in rtl8723bu_rx_iqk_path_a()
811 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); in rtl8723bu_rx_iqk_path_a()
812 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); in rtl8723bu_rx_iqk_path_a()
815 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1); in rtl8723bu_rx_iqk_path_a()
820 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
823 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
825 if (priv->rf_paths > 1) in rtl8723bu_rx_iqk_path_a()
826 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); in rtl8723bu_rx_iqk_path_a()
828 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); in rtl8723bu_rx_iqk_path_a()
833 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); in rtl8723bu_rx_iqk_path_a()
836 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8723bu_rx_iqk_path_a()
837 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8723bu_rx_iqk_path_a()
842 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); in rtl8723bu_rx_iqk_path_a()
845 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); in rtl8723bu_rx_iqk_path_a()
851 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
853 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
856 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8723bu_rx_iqk_path_a()
857 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); in rtl8723bu_rx_iqk_path_a()
859 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780); in rtl8723bu_rx_iqk_path_a()
878 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, in rtl8723bu_phy_iqcalibrate() argument
881 struct device *dev = &priv->udev->dev; in rtl8723bu_phy_iqcalibrate()
905 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; in rtl8723bu_phy_iqcalibrate()
906 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; in rtl8723bu_phy_iqcalibrate()
915 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, in rtl8723bu_phy_iqcalibrate()
917 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8723bu_phy_iqcalibrate()
918 rtl8xxxu_save_regs(priv, iqk_bb_regs, in rtl8723bu_phy_iqcalibrate()
919 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8723bu_phy_iqcalibrate()
922 rtl8xxxu_path_adda_on(priv, adda_regs, true); in rtl8723bu_phy_iqcalibrate()
925 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); in rtl8723bu_phy_iqcalibrate()
927 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); in rtl8723bu_phy_iqcalibrate()
929 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); in rtl8723bu_phy_iqcalibrate()
931 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); in rtl8723bu_phy_iqcalibrate()
932 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); in rtl8723bu_phy_iqcalibrate()
933 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); in rtl8723bu_phy_iqcalibrate()
939 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
941 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
943 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_phy_iqcalibrate()
945 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_phy_iqcalibrate()
947 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8723bu_phy_iqcalibrate()
948 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); in rtl8723bu_phy_iqcalibrate()
949 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); in rtl8723bu_phy_iqcalibrate()
951 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); in rtl8723bu_phy_iqcalibrate()
953 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); in rtl8723bu_phy_iqcalibrate()
955 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd); in rtl8723bu_phy_iqcalibrate()
958 path_a_ok = rtl8723bu_iqk_path_a(priv); in rtl8723bu_phy_iqcalibrate()
960 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
962 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
964 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
967 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
979 path_a_ok = rtl8723bu_rx_iqk_path_a(priv); in rtl8723bu_phy_iqcalibrate()
981 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
984 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
995 if (priv->tx_paths > 1) { in rtl8723bu_phy_iqcalibrate()
1003 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
1005 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1006 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); in rtl8723bu_phy_iqcalibrate()
1008 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
1011 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1014 rtl8xxxu_path_adda_on(priv, adda_regs, false); in rtl8723bu_phy_iqcalibrate()
1017 path_b_ok = rtl8xxxu_iqk_path_b(priv); in rtl8723bu_phy_iqcalibrate()
1019 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8723bu_phy_iqcalibrate()
1021 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8723bu_phy_iqcalibrate()
1031 path_b_ok = rtl8723bu_rx_iqk_path_b(priv); in rtl8723bu_phy_iqcalibrate()
1033 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1036 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1049 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
1051 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1055 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, in rtl8723bu_phy_iqcalibrate()
1059 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8723bu_phy_iqcalibrate()
1062 rtl8xxxu_restore_regs(priv, iqk_bb_regs, in rtl8723bu_phy_iqcalibrate()
1063 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8723bu_phy_iqcalibrate()
1066 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8723bu_phy_iqcalibrate()
1068 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); in rtl8723bu_phy_iqcalibrate()
1069 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); in rtl8723bu_phy_iqcalibrate()
1071 if (priv->tx_paths > 1) { in rtl8723bu_phy_iqcalibrate()
1072 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); in rtl8723bu_phy_iqcalibrate()
1074 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, in rtl8723bu_phy_iqcalibrate()
1076 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, in rtl8723bu_phy_iqcalibrate()
1081 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); in rtl8723bu_phy_iqcalibrate()
1082 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); in rtl8723bu_phy_iqcalibrate()
1086 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) in rtl8723bu_phy_iq_calibrate() argument
1088 struct device *dev = &priv->udev->dev; in rtl8723bu_phy_iq_calibrate()
1098 rtl8xxxu_gen2_prepare_calibrate(priv, 1); in rtl8723bu_phy_iq_calibrate()
1106 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU); in rtl8723bu_phy_iq_calibrate()
1109 rtl8723bu_phy_iqcalibrate(priv, result, i); in rtl8723bu_phy_iq_calibrate()
1112 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8723bu_phy_iq_calibrate()
1121 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8723bu_phy_iq_calibrate()
1128 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8723bu_phy_iq_calibrate()
1157 priv->rege94 = reg_e94; in rtl8723bu_phy_iq_calibrate()
1159 priv->rege9c = reg_e9c; in rtl8723bu_phy_iq_calibrate()
1163 priv->regeb4 = reg_eb4; in rtl8723bu_phy_iq_calibrate()
1165 priv->regebc = reg_ebc; in rtl8723bu_phy_iq_calibrate()
1176 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; in rtl8723bu_phy_iq_calibrate()
1177 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; in rtl8723bu_phy_iq_calibrate()
1181 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, in rtl8723bu_phy_iq_calibrate()
1184 if (priv->tx_paths > 1 && reg_eb4) in rtl8723bu_phy_iq_calibrate()
1185 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, in rtl8723bu_phy_iq_calibrate()
1188 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, in rtl8723bu_phy_iq_calibrate()
1189 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); in rtl8723bu_phy_iq_calibrate()
1191 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control); in rtl8723bu_phy_iq_calibrate()
1193 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_phy_iq_calibrate()
1195 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_phy_iq_calibrate()
1196 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000); in rtl8723bu_phy_iq_calibrate()
1197 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); in rtl8723bu_phy_iq_calibrate()
1198 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177); in rtl8723bu_phy_iq_calibrate()
1199 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); in rtl8723bu_phy_iq_calibrate()
1201 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); in rtl8723bu_phy_iq_calibrate()
1202 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd); in rtl8723bu_phy_iq_calibrate()
1204 if (priv->rf_paths > 1) in rtl8723bu_phy_iq_calibrate()
1207 rtl8xxxu_gen2_prepare_calibrate(priv, 0); in rtl8723bu_phy_iq_calibrate()
1210 static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv) in rtl8723bu_active_to_emu() argument
1218 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); in rtl8723bu_active_to_emu()
1221 val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM); in rtl8723bu_active_to_emu()
1223 rtl8xxxu_write16(priv, REG_GPIO_INTM, val16); in rtl8723bu_active_to_emu()
1226 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723bu_active_to_emu()
1228 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723bu_active_to_emu()
1231 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8723bu_active_to_emu()
1233 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8723bu_active_to_emu()
1236 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8723bu_active_to_emu()
1243 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", in rtl8723bu_active_to_emu()
1250 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); in rtl8723bu_active_to_emu()
1252 rtl8xxxu_write8(priv, REG_AFE_MISC, val8); in rtl8723bu_active_to_emu()
1255 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); in rtl8723bu_active_to_emu()
1257 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); in rtl8723bu_active_to_emu()
1260 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); in rtl8723bu_active_to_emu()
1262 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); in rtl8723bu_active_to_emu()
1268 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv) in rtl8723b_emu_to_active() argument
1275 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); in rtl8723b_emu_to_active()
1277 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); in rtl8723b_emu_to_active()
1280 val8 = rtl8xxxu_read8(priv, 0x0067); in rtl8723b_emu_to_active()
1282 rtl8xxxu_write8(priv, 0x0067, val8); in rtl8723b_emu_to_active()
1287 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); in rtl8723b_emu_to_active()
1289 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); in rtl8723b_emu_to_active()
1292 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1294 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1298 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1313 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1315 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1318 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1320 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1323 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1325 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1328 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1330 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1333 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1347 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); in rtl8723b_emu_to_active()
1349 rtl8xxxu_write8(priv, REG_AFE_MISC, val8); in rtl8723b_emu_to_active()
1352 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1); in rtl8723b_emu_to_active()
1354 rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8); in rtl8723b_emu_to_active()
1357 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1); in rtl8723b_emu_to_active()
1359 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8); in rtl8723b_emu_to_active()
1362 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2); in rtl8723b_emu_to_active()
1364 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8); in rtl8723b_emu_to_active()
1367 val8 = rtl8xxxu_read8(priv, REG_HSIMR); in rtl8723b_emu_to_active()
1369 rtl8xxxu_write8(priv, REG_HSIMR, val8); in rtl8723b_emu_to_active()
1372 val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2); in rtl8723b_emu_to_active()
1374 rtl8xxxu_write8(priv, REG_HSIMR + 2, val8); in rtl8723b_emu_to_active()
1376 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL); in rtl8723b_emu_to_active()
1378 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8); in rtl8723b_emu_to_active()
1381 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1); in rtl8723b_emu_to_active()
1383 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8); in rtl8723b_emu_to_active()
1389 static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv) in rtl8723bu_power_on() argument
1396 rtl8xxxu_disabled_to_emu(priv); in rtl8723bu_power_on()
1398 ret = rtl8723b_emu_to_active(priv); in rtl8723bu_power_on()
1406 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8723bu_power_on()
1412 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8723bu_power_on()
1418 rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20); in rtl8723bu_power_on()
1420 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8723bu_power_on()
1422 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8723bu_power_on()
1424 rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18); in rtl8723bu_power_on()
1425 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); in rtl8723bu_power_on()
1426 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); in rtl8723bu_power_on()
1428 rtl8xxxu_write8(priv, 0xfe08, 0x01); in rtl8723bu_power_on()
1430 val16 = rtl8xxxu_read16(priv, REG_PWR_DATA); in rtl8723bu_power_on()
1432 rtl8xxxu_write16(priv, REG_PWR_DATA, val16); in rtl8723bu_power_on()
1434 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723bu_power_on()
1436 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_power_on()
1438 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); in rtl8723bu_power_on()
1440 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); in rtl8723bu_power_on()
1445 static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv) in rtl8723bu_power_off() argument
1450 rtl8xxxu_flush_fifo(priv); in rtl8723bu_power_off()
1455 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); in rtl8723bu_power_off()
1457 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); in rtl8723bu_power_off()
1459 rtl8xxxu_write8(priv, REG_CR, 0x0000); in rtl8723bu_power_off()
1461 rtl8xxxu_active_to_lps(priv); in rtl8723bu_power_off()
1464 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) in rtl8723bu_power_off()
1465 rtl8xxxu_firmware_self_reset(priv); in rtl8723bu_power_off()
1468 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8723bu_power_off()
1470 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8723bu_power_off()
1473 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); in rtl8723bu_power_off()
1475 rtl8723bu_active_to_emu(priv); in rtl8723bu_power_off()
1477 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8723bu_power_off()
1479 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8723bu_power_off()
1482 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); in rtl8723bu_power_off()
1484 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); in rtl8723bu_power_off()
1487 static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv) in rtl8723b_enable_rf() argument
1493 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); in rtl8723b_enable_rf()
1495 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); in rtl8723b_enable_rf()
1501 rtl8xxxu_write8(priv, 0x0790, 0x05); in rtl8723b_enable_rf()
1507 rtl8xxxu_write8(priv, 0x0778, 0x01); in rtl8723b_enable_rf()
1509 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); in rtl8723b_enable_rf()
1511 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); in rtl8723b_enable_rf()
1513 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); in rtl8723b_enable_rf()
1515 rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */ in rtl8723b_enable_rf()
1523 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant)); in rtl8723b_enable_rf()
1528 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x0c); in rtl8723b_enable_rf()
1533 val8 = rtl8xxxu_read8(priv, 0x0067); in rtl8723b_enable_rf()
1535 rtl8xxxu_write8(priv, 0x0067, val8); in rtl8723b_enable_rf()
1537 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); in rtl8723b_enable_rf()
1539 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8723b_enable_rf()
1544 rtl8xxxu_write8(priv, 0x0974, 0xff); in rtl8723b_enable_rf()
1546 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8723b_enable_rf()
1548 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8723b_enable_rf()
1550 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77); in rtl8723b_enable_rf()
1552 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723b_enable_rf()
1555 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723b_enable_rf()
1560 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); in rtl8723b_enable_rf()
1562 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); in rtl8723b_enable_rf()
1568 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv)); in rtl8723b_enable_rf()
1578 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x80); in rtl8723b_enable_rf()
1583 rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00); in rtl8723b_enable_rf()
1585 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); in rtl8723b_enable_rf()
1586 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); in rtl8723b_enable_rf()
1587 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); in rtl8723b_enable_rf()
1588 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); in rtl8723b_enable_rf()
1593 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info)); in rtl8723b_enable_rf()
1598 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan)); in rtl8723b_enable_rf()
1601 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv) in rtl8723bu_init_aggregation() argument
1609 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); in rtl8723bu_init_aggregation()
1612 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); in rtl8723bu_init_aggregation()
1616 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); in rtl8723bu_init_aggregation()
1617 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); in rtl8723bu_init_aggregation()
1620 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv) in rtl8723bu_init_statistics() argument
1625 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710); in rtl8723bu_init_statistics()
1626 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); in rtl8723bu_init_statistics()
1627 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52); in rtl8723bu_init_statistics()
1628 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); in rtl8723bu_init_statistics()
1630 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_init_statistics()
1632 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_init_statistics()
1634 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); in rtl8723bu_init_statistics()
1636 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); in rtl8723bu_init_statistics()
1638 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); in rtl8723bu_init_statistics()
1640 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); in rtl8723bu_init_statistics()