145 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];  in _rtl88e_phy_rf_serial_read()
195 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];  in _rtl88e_phy_rf_serial_write()
811 	rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in _rtl88e_phy_init_bb_rf_register_definition()
812 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in _rtl88e_phy_init_bb_rf_register_definition()
813 	rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;  in _rtl88e_phy_init_bb_rf_register_definition()
814 	rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;  in _rtl88e_phy_init_bb_rf_register_definition()
816 	rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;  in _rtl88e_phy_init_bb_rf_register_definition()
817 	rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;  in _rtl88e_phy_init_bb_rf_register_definition()
818 	rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;  in _rtl88e_phy_init_bb_rf_register_definition()
819 	rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;  in _rtl88e_phy_init_bb_rf_register_definition()
821 	rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;  in _rtl88e_phy_init_bb_rf_register_definition()
822 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;  in _rtl88e_phy_init_bb_rf_register_definition()
824 	rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;  in _rtl88e_phy_init_bb_rf_register_definition()
825 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;  in _rtl88e_phy_init_bb_rf_register_definition()
827 	rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =  in _rtl88e_phy_init_bb_rf_register_definition()
829 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =  in _rtl88e_phy_init_bb_rf_register_definition()
832 	rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;  in _rtl88e_phy_init_bb_rf_register_definition()
833 	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;  in _rtl88e_phy_init_bb_rf_register_definition()
834 	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;  in _rtl88e_phy_init_bb_rf_register_definition()
835 	rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;  in _rtl88e_phy_init_bb_rf_register_definition()
837 	rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl88e_phy_init_bb_rf_register_definition()
838 	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl88e_phy_init_bb_rf_register_definition()
839 	rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl88e_phy_init_bb_rf_register_definition()
840 	rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl88e_phy_init_bb_rf_register_definition()
842 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;  in _rtl88e_phy_init_bb_rf_register_definition()
843 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;  in _rtl88e_phy_init_bb_rf_register_definition()
845 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;  in _rtl88e_phy_init_bb_rf_register_definition()
846 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;  in _rtl88e_phy_init_bb_rf_register_definition()
848 	rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl =  in _rtl88e_phy_init_bb_rf_register_definition()
850 	rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl =  in _rtl88e_phy_init_bb_rf_register_definition()
852 	rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl =  in _rtl88e_phy_init_bb_rf_register_definition()
854 	rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl =  in _rtl88e_phy_init_bb_rf_register_definition()
857 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;  in _rtl88e_phy_init_bb_rf_register_definition()
858 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;  in _rtl88e_phy_init_bb_rf_register_definition()
859 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;  in _rtl88e_phy_init_bb_rf_register_definition()
860 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;  in _rtl88e_phy_init_bb_rf_register_definition()
862 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;  in _rtl88e_phy_init_bb_rf_register_definition()
863 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;  in _rtl88e_phy_init_bb_rf_register_definition()
864 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;  in _rtl88e_phy_init_bb_rf_register_definition()
865 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;  in _rtl88e_phy_init_bb_rf_register_definition()
867 	rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;  in _rtl88e_phy_init_bb_rf_register_definition()
868 	rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;  in _rtl88e_phy_init_bb_rf_register_definition()
869 	rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;  in _rtl88e_phy_init_bb_rf_register_definition()
870 	rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;  in _rtl88e_phy_init_bb_rf_register_definition()
872 	rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;  in _rtl88e_phy_init_bb_rf_register_definition()
873 	rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;  in _rtl88e_phy_init_bb_rf_register_definition()
874 	rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;  in _rtl88e_phy_init_bb_rf_register_definition()
875 	rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;  in _rtl88e_phy_init_bb_rf_register_definition()
877 	rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;  in _rtl88e_phy_init_bb_rf_register_definition()
878 	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;  in _rtl88e_phy_init_bb_rf_register_definition()
879 	rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;  in _rtl88e_phy_init_bb_rf_register_definition()
880 	rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;  in _rtl88e_phy_init_bb_rf_register_definition()
882 	rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;  in _rtl88e_phy_init_bb_rf_register_definition()
883 	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;  in _rtl88e_phy_init_bb_rf_register_definition()
885 	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;  in _rtl88e_phy_init_bb_rf_register_definition()
886 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;  in _rtl88e_phy_init_bb_rf_register_definition()
888 	rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;  in _rtl88e_phy_init_bb_rf_register_definition()
889 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;  in _rtl88e_phy_init_bb_rf_register_definition()