66 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];  in _rtl92s_phy_rf_serial_read()
127 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];  in _rtl92s_phy_rf_serial_write()
672 	rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in _rtl92s_phy_init_register_definition()
673 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in _rtl92s_phy_init_register_definition()
674 	rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;  in _rtl92s_phy_init_register_definition()
675 	rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;  in _rtl92s_phy_init_register_definition()
678 	rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;  in _rtl92s_phy_init_register_definition()
679 	rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;  in _rtl92s_phy_init_register_definition()
680 	rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;  in _rtl92s_phy_init_register_definition()
681 	rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;  in _rtl92s_phy_init_register_definition()
684 	rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;  in _rtl92s_phy_init_register_definition()
685 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;  in _rtl92s_phy_init_register_definition()
686 	rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE;  in _rtl92s_phy_init_register_definition()
687 	rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE;  in _rtl92s_phy_init_register_definition()
690 	rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;  in _rtl92s_phy_init_register_definition()
691 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;  in _rtl92s_phy_init_register_definition()
692 	rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE;  in _rtl92s_phy_init_register_definition()
693 	rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE;  in _rtl92s_phy_init_register_definition()
696 	rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =  in _rtl92s_phy_init_register_definition()
698 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =  in _rtl92s_phy_init_register_definition()
700 	rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset =  in _rtl92s_phy_init_register_definition()
702 	rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset =  in _rtl92s_phy_init_register_definition()
706 	rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;  in _rtl92s_phy_init_register_definition()
707 	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;  in _rtl92s_phy_init_register_definition()
708 	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;  in _rtl92s_phy_init_register_definition()
709 	rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;  in _rtl92s_phy_init_register_definition()
712 	rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl92s_phy_init_register_definition()
713 	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl92s_phy_init_register_definition()
714 	rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl92s_phy_init_register_definition()
715 	rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl92s_phy_init_register_definition()
718 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;  in _rtl92s_phy_init_register_definition()
719 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;  in _rtl92s_phy_init_register_definition()
720 	rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1;  in _rtl92s_phy_init_register_definition()
721 	rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1;  in _rtl92s_phy_init_register_definition()
724 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;  in _rtl92s_phy_init_register_definition()
725 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;  in _rtl92s_phy_init_register_definition()
726 	rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2;  in _rtl92s_phy_init_register_definition()
727 	rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2;  in _rtl92s_phy_init_register_definition()
730 	rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;  in _rtl92s_phy_init_register_definition()
731 	rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;  in _rtl92s_phy_init_register_definition()
732 	rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;  in _rtl92s_phy_init_register_definition()
733 	rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;  in _rtl92s_phy_init_register_definition()
736 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;  in _rtl92s_phy_init_register_definition()
737 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;  in _rtl92s_phy_init_register_definition()
738 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;  in _rtl92s_phy_init_register_definition()
739 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;  in _rtl92s_phy_init_register_definition()
742 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;  in _rtl92s_phy_init_register_definition()
743 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;  in _rtl92s_phy_init_register_definition()
744 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;  in _rtl92s_phy_init_register_definition()
745 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;  in _rtl92s_phy_init_register_definition()
748 	rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;  in _rtl92s_phy_init_register_definition()
749 	rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;  in _rtl92s_phy_init_register_definition()
750 	rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;  in _rtl92s_phy_init_register_definition()
751 	rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;  in _rtl92s_phy_init_register_definition()
754 	rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;  in _rtl92s_phy_init_register_definition()
755 	rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;  in _rtl92s_phy_init_register_definition()
756 	rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;  in _rtl92s_phy_init_register_definition()
757 	rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;  in _rtl92s_phy_init_register_definition()
760 	rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;  in _rtl92s_phy_init_register_definition()
761 	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;  in _rtl92s_phy_init_register_definition()
762 	rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;  in _rtl92s_phy_init_register_definition()
763 	rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;  in _rtl92s_phy_init_register_definition()
766 	rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;  in _rtl92s_phy_init_register_definition()
767 	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;  in _rtl92s_phy_init_register_definition()
768 	rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;  in _rtl92s_phy_init_register_definition()
769 	rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;  in _rtl92s_phy_init_register_definition()
772 	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;  in _rtl92s_phy_init_register_definition()
773 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;  in _rtl92s_phy_init_register_definition()
774 	rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;  in _rtl92s_phy_init_register_definition()
775 	rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;  in _rtl92s_phy_init_register_definition()
778 	rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;  in _rtl92s_phy_init_register_definition()
779 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;  in _rtl92s_phy_init_register_definition()