Lines Matching refs:phyreg_def

263 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];  in _rtl8821ae_phy_rf_serial_write()
2152 	rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in phy_init_bb_rf_register_definition()
2153 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in phy_init_bb_rf_register_definition()
2155 	rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;  in phy_init_bb_rf_register_definition()
2156 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;  in phy_init_bb_rf_register_definition()
2158 	rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;  in phy_init_bb_rf_register_definition()
2159 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;  in phy_init_bb_rf_register_definition()
2161 	rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = RA_LSSIWRITE_8821A;  in phy_init_bb_rf_register_definition()
2162 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = RB_LSSIWRITE_8821A;  in phy_init_bb_rf_register_definition()
2164 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RHSSIREAD_8821AE;  in phy_init_bb_rf_register_definition()
2165 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RHSSIREAD_8821AE;  in phy_init_bb_rf_register_definition()
2167 	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RA_SIREAD_8821A;  in phy_init_bb_rf_register_definition()
2168 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RB_SIREAD_8821A;  in phy_init_bb_rf_register_definition()
2170 	rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = RA_PIREAD_8821A;  in phy_init_bb_rf_register_definition()
2171 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = RB_PIREAD_8821A;  in phy_init_bb_rf_register_definition()