Lines Matching refs:dt
143 struct arm_ccn_dt, pmu), struct arm_ccn, dt)
183 struct arm_ccn_dt dt; member
460 return &ccn->dt.cmp_mask[i].l; in arm_ccn_pmu_get_cmp_mask()
462 return &ccn->dt.cmp_mask[i].h; in arm_ccn_pmu_get_cmp_mask()
550 return cpumap_print_to_pagebuf(true, buf, cpumask_of(ccn->dt.cpu)); in arm_ccn_pmu_cpumask_show()
646 ccn->dt.pmu_counters_mask)) in arm_ccn_pmu_event_alloc()
650 ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event; in arm_ccn_pmu_event_alloc()
656 hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask, in arm_ccn_pmu_event_alloc()
667 ccn->dt.pmu_counters[hw->idx].source = source; in arm_ccn_pmu_event_alloc()
679 clear_bit(hw->idx, ccn->dt.pmu_counters_mask); in arm_ccn_pmu_event_alloc()
684 ccn->dt.pmu_counters[hw->idx].event = event; in arm_ccn_pmu_event_alloc()
695 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask); in arm_ccn_pmu_event_release()
698 ccn->dt.pmu_counters[hw->idx].source; in arm_ccn_pmu_event_release()
706 clear_bit(hw->idx, ccn->dt.pmu_counters_mask); in arm_ccn_pmu_event_release()
709 ccn->dt.pmu_counters[hw->idx].source = NULL; in arm_ccn_pmu_event_release()
710 ccn->dt.pmu_counters[hw->idx].event = NULL; in arm_ccn_pmu_event_release()
750 event->cpu = ccn->dt.cpu; in arm_ccn_pmu_event_init()
850 res = readq(ccn->dt.base + CCN_DT_PMCCNTR); in arm_ccn_pmu_read_counter()
853 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ); in arm_ccn_pmu_read_counter()
854 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1)) in arm_ccn_pmu_read_counter()
856 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); in arm_ccn_pmu_read_counter()
857 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff; in arm_ccn_pmu_read_counter()
859 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR); in arm_ccn_pmu_read_counter()
862 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx)); in arm_ccn_pmu_read_counter()
906 spin_lock(&ccn->dt.config_lock); in arm_ccn_pmu_xp_dt_config()
914 spin_unlock(&ccn->dt.config_lock); in arm_ccn_pmu_xp_dt_config()
948 ccn->dt.pmu_counters[hw->idx].source; in arm_ccn_pmu_xp_watchpoint_config()
953 u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l; in arm_ccn_pmu_xp_watchpoint_config()
954 u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h; in arm_ccn_pmu_xp_watchpoint_config()
996 ccn->dt.pmu_counters[hw->idx].source; in arm_ccn_pmu_xp_event_config()
1017 ccn->dt.pmu_counters[hw->idx].source; in arm_ccn_pmu_node_event_config()
1064 spin_lock(&ccn->dt.config_lock); in arm_ccn_pmu_event_config()
1068 val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); in arm_ccn_pmu_event_config()
1072 writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset); in arm_ccn_pmu_event_config()
1084 spin_unlock(&ccn->dt.config_lock); in arm_ccn_pmu_event_config()
1089 return bitmap_weight(ccn->dt.pmu_counters_mask, in arm_ccn_pmu_active_counters()
1109 hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(), in arm_ccn_pmu_event_add()
1131 hrtimer_cancel(&ccn->dt.hrtimer); in arm_ccn_pmu_event_del()
1143 u32 val = readl(ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_enable()
1145 writel(val, ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_enable()
1152 u32 val = readl(ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_disable()
1154 writel(val, ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_disable()
1157 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt) in arm_ccn_pmu_overflow_handler() argument
1159 u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR); in arm_ccn_pmu_overflow_handler()
1165 writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR); in arm_ccn_pmu_overflow_handler()
1170 struct perf_event *event = dt->pmu_counters[idx].event; in arm_ccn_pmu_overflow_handler()
1187 struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt, in arm_ccn_pmu_timer_handler() local
1192 arm_ccn_pmu_overflow_handler(dt); in arm_ccn_pmu_timer_handler()
1202 struct arm_ccn_dt *dt = hlist_entry_safe(node, struct arm_ccn_dt, node); in arm_ccn_pmu_offline_cpu() local
1203 struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt); in arm_ccn_pmu_offline_cpu()
1206 if (cpu != dt->cpu) in arm_ccn_pmu_offline_cpu()
1211 perf_pmu_migrate_context(&dt->pmu, cpu, target); in arm_ccn_pmu_offline_cpu()
1212 dt->cpu = target; in arm_ccn_pmu_offline_cpu()
1214 WARN_ON(irq_set_affinity(ccn->irq, cpumask_of(dt->cpu))); in arm_ccn_pmu_offline_cpu()
1227 ccn->dt.base = ccn->base + CCN_REGION_SIZE; in arm_ccn_pmu_init()
1228 spin_lock_init(&ccn->dt.config_lock); in arm_ccn_pmu_init()
1229 writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR); in arm_ccn_pmu_init()
1230 writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL); in arm_ccn_pmu_init()
1232 ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_init()
1233 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR); in arm_ccn_pmu_init()
1243 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0; in arm_ccn_pmu_init()
1244 ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0; in arm_ccn_pmu_init()
1245 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0; in arm_ccn_pmu_init()
1246 ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0; in arm_ccn_pmu_init()
1247 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0; in arm_ccn_pmu_init()
1248 ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15); in arm_ccn_pmu_init()
1249 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0; in arm_ccn_pmu_init()
1250 ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9); in arm_ccn_pmu_init()
1253 ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL); in arm_ccn_pmu_init()
1254 if (ccn->dt.id == 0) { in arm_ccn_pmu_init()
1258 ccn->dt.id); in arm_ccn_pmu_init()
1266 ccn->dt.pmu = (struct pmu) { in arm_ccn_pmu_init()
1284 hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC, in arm_ccn_pmu_init()
1286 ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler; in arm_ccn_pmu_init()
1290 ccn->dt.cpu = raw_smp_processor_id(); in arm_ccn_pmu_init()
1294 err = irq_set_affinity(ccn->irq, cpumask_of(ccn->dt.cpu)); in arm_ccn_pmu_init()
1302 &ccn->dt.node); in arm_ccn_pmu_init()
1304 err = perf_pmu_register(&ccn->dt.pmu, name, -1); in arm_ccn_pmu_init()
1312 &ccn->dt.node); in arm_ccn_pmu_init()
1315 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id); in arm_ccn_pmu_init()
1318 writel(0, ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_init()
1327 &ccn->dt.node); in arm_ccn_pmu_cleanup()
1330 writel(0, ccn->dt.base + CCN_DT_PMCR); in arm_ccn_pmu_cleanup()
1331 perf_pmu_unregister(&ccn->dt.pmu); in arm_ccn_pmu_cleanup()
1332 ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id); in arm_ccn_pmu_cleanup()
1440 res = arm_ccn_pmu_overflow_handler(&ccn->dt); in arm_ccn_irq_handler()