Lines Matching refs:wr_reg16
401 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
403 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
408 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
1334 wr_reg16(info, TCR, value); in set_break()
2070 wr_reg16(info, SSR, status); /* clear pending */ in isr_serial()
2210 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in isr_txeom()
2211 wr_reg16(info, TCR, val); /* clear reset bit */ in isr_txeom()
2640 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3); in rx_enable()
2693 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE)); in wait_mgsl_event()
2756 wr_reg16(info, SCR, in wait_mgsl_event()
2792 wr_reg16(info, TCR, val); in set_interface()
3776 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value) in wr_reg16() function
3828 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); in enable_loopback()
3867 wr_reg16(info, BDR, (unsigned short)div); in set_rate()
3877 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ in rx_stop()
3878 wr_reg16(info, RCR, val); /* clear reset bit */ in rx_stop()
3883 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER); in rx_stop()
3898 wr_reg16(info, SSR, IRQ_RXOVER); in rx_start()
3902 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ in rx_start()
3903 wr_reg16(info, RCR, val); /* clear reset bit */ in rx_start()
3910 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14)); in rx_start()
3918 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14)); in rx_start()
3934 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1)); in rx_start()
3943 wr_reg16(info, TCR, in tx_start()
3964 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); in tx_start()
3969 wr_reg16(info, SSR, IRQ_TXIDLE); in tx_start()
3988 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in tx_stop()
3993 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER)); in tx_stop()
4074 wr_reg16(info, TCR, val); in async_mode()
4111 wr_reg16(info, RCR, val); in async_mode()
4157 wr_reg16(info, SCR, val); in async_mode()
4236 wr_reg16(info, TCR, val); in sync_mode()
4299 wr_reg16(info, RCR, val); in sync_mode()
4350 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val)); in sync_mode()
4381 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); in sync_mode()
4408 wr_reg16(info, TCR, tcr); in tx_set_idle()
4869 wr_reg16(info, TIR, patterns[i]); in register_test()
4870 wr_reg16(info, BDR, patterns[(i+1)%count]); in register_test()
4897 wr_reg16(info, TCR, in irq_test()
4901 wr_reg16(info, TDR, 0); in irq_test()