302 		u32 save, tmp;  in radeon_pll_errata_after_data_slow()  local
303 		save = INREG(CLOCK_CNTL_INDEX);  in radeon_pll_errata_after_data_slow()
304 		tmp = save & ~(0x3f | PLL_WR_EN);  in radeon_pll_errata_after_data_slow()
307 		OUTREG(CLOCK_CNTL_INDEX, save);  in radeon_pll_errata_after_data_slow()
1310 			       struct radeon_regs *save)  in radeon_save_state()  argument
1313 	save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);  in radeon_save_state()
1314 	save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);  in radeon_save_state()
1315 	save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);  in radeon_save_state()
1316 	save->dac_cntl = INREG(DAC_CNTL);  in radeon_save_state()
1317         save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);  in radeon_save_state()
1318         save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);  in radeon_save_state()
1319         save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);  in radeon_save_state()
1320         save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);  in radeon_save_state()
1321 	save->crtc_pitch = INREG(CRTC_PITCH);  in radeon_save_state()
1322 	save->surface_cntl = INREG(SURFACE_CNTL);  in radeon_save_state()
1325 	save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);  in radeon_save_state()
1326 	save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);  in radeon_save_state()
1327 	save->fp_gen_cntl = INREG(FP_GEN_CNTL);  in radeon_save_state()
1328 	save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);  in radeon_save_state()
1329 	save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);  in radeon_save_state()
1330 	save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);  in radeon_save_state()
1331 	save->fp_vert_stretch = INREG(FP_VERT_STRETCH);  in radeon_save_state()
1332 	save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);  in radeon_save_state()
1333 	save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);  in radeon_save_state()
1334 	save->tmds_crc = INREG(TMDS_CRC);  in radeon_save_state()
1335 	save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);  in radeon_save_state()
1336 	save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);  in radeon_save_state()
1339 	save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;  in radeon_save_state()
1341 	save->ppll_div_3 = INPLL(PPLL_DIV_3);  in radeon_save_state()
1342 	save->ppll_ref_div = INPLL(PPLL_REF_DIV);  in radeon_save_state()