Lines Matching refs:u32

17 	u32 tmr_ctrl;     /* Timer control register */
18 	u32 tmr_tevent;   /* Timestamp event register */
19 	u32 tmr_temask;   /* Timer event mask register */
20 	u32 tmr_pevent;   /* Timestamp event register */
21 	u32 tmr_pemask;   /* Timer event mask register */
22 	u32 tmr_stat;     /* Timestamp status register */
23 	u32 tmr_cnt_h;    /* Timer counter high register */
24 	u32 tmr_cnt_l;    /* Timer counter low register */
25 	u32 tmr_add;      /* Timer drift compensation addend register */
26 	u32 tmr_acc;      /* Timer accumulator register */
27 	u32 tmr_prsc;     /* Timer prescale */
29 	u32 tmroff_h;     /* Timer offset high */
30 	u32 tmroff_l;     /* Timer offset low */
34 	u32 tmr_alarm1_h; /* Timer alarm 1 high register */
35 	u32 tmr_alarm1_l; /* Timer alarm 1 high register */
36 	u32 tmr_alarm2_h; /* Timer alarm 2 high register */
37 	u32 tmr_alarm2_l; /* Timer alarm 2 high register */
41 	u32 tmr_fiper1;   /* Timer fixed period interval */
42 	u32 tmr_fiper2;   /* Timer fixed period interval */
43 	u32 tmr_fiper3;   /* Timer fixed period interval */
47 	u32 tmr_etts1_h;  /* Timestamp of general purpose external trigger */
48 	u32 tmr_etts1_l;  /* Timestamp of general purpose external trigger */
49 	u32 tmr_etts2_h;  /* Timestamp of general purpose external trigger */
50 	u32 tmr_etts2_l;  /* Timestamp of general purpose external trigger */
154 	u32 tclk_period;  /* nanoseconds */
155 	u32 tmr_prsc;
156 	u32 tmr_add;
157 	u32 cksel;
158 	u32 tmr_fiper1;
159 	u32 tmr_fiper2;
160 	u32 tmr_fiper3;
161 	u32 (*read)(unsigned __iomem *addr);
162 	void (*write)(unsigned __iomem *addr, u32 val);
165 static inline u32 qoriq_read_be(unsigned __iomem *addr)  in qoriq_read_be()
170 static inline void qoriq_write_be(unsigned __iomem *addr, u32 val)  in qoriq_write_be()
175 static inline u32 qoriq_read_le(unsigned __iomem *addr)  in qoriq_read_le()
180 static inline void qoriq_write_le(unsigned __iomem *addr, u32 val)  in qoriq_write_le()