1223 #define MLX5_CAP_GEN(mdev, cap) \  argument
1226 #define MLX5_CAP_GEN_64(mdev, cap) \  argument
1229 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1232 #define MLX5_CAP_GEN_2(mdev, cap) \  argument
1235 #define MLX5_CAP_GEN_2_64(mdev, cap) \  argument
1238 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \  argument
1241 #define MLX5_CAP_ETH(mdev, cap) \  argument
1245 #define MLX5_CAP_ETH_MAX(mdev, cap) \  argument
1249 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \  argument
1253 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1256 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1259 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1262 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1265 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1268 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1271 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \  argument
1274 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1277 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \  argument
1280 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1283 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \  argument
1286 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1289 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \  argument
1292 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1295 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \  argument
1298 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1301 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \  argument
1304 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \  argument
1307 #define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \  argument
1310 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1314 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \  argument
1318 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1321 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \  argument
1324 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1327 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \  argument
1330 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1333 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \  argument
1336 #define MLX5_CAP_ESW(mdev, cap) \  argument
1340 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1344 #define MLX5_CAP_ESW_MAX(mdev, cap) \  argument
1348 #define MLX5_CAP_ODP(mdev, cap)\  argument
1351 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1354 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \  argument
1358 #define MLX5_CAP_QOS(mdev, cap)\  argument
1361 #define MLX5_CAP_DEBUG(mdev, cap)\  argument
1364 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \  argument
1367 #define MLX5_CAP_PCAM_REG(mdev, reg) \  argument
1370 #define MLX5_CAP_MCAM_REG(mdev, reg) \  argument
1374 #define MLX5_CAP_MCAM_REG1(mdev, reg) \  argument
1378 #define MLX5_CAP_MCAM_REG2(mdev, reg) \  argument
1382 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \  argument
1385 #define MLX5_CAP_QCAM_REG(mdev, fld) \  argument
1388 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \  argument
1391 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1394 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1397 #define MLX5_CAP_DEV_MEM(mdev, cap)\  argument
1400 #define MLX5_CAP64_DEV_MEM(mdev, cap)\  argument
1403 #define MLX5_CAP_TLS(mdev, cap) \  argument
1406 #define MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1409 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\  argument
1413 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\  argument
1417 #define MLX5_CAP_IPSEC(mdev, cap)\  argument