1223 #define MLX5_CAP_GEN(mdev, cap) \  argument
1224 	MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1226 #define MLX5_CAP_GEN_64(mdev, cap) \  argument
1227 	MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1229 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1230 	MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap)
1232 #define MLX5_CAP_GEN_2(mdev, cap) \  argument
1233 	MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1235 #define MLX5_CAP_GEN_2_64(mdev, cap) \  argument
1236 	MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1238 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \  argument
1239 	MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap)
1241 #define MLX5_CAP_ETH(mdev, cap) \  argument
1243 		 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap)
1245 #define MLX5_CAP_ETH_MAX(mdev, cap) \  argument
1247 		 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->max, cap)
1249 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \  argument
1251 		 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap)
1253 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1254 	MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap)
1256 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1257 	MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap)
1259 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1260 	MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap)
1262 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1263 	MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap)
1265 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1266 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1268 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \  argument
1269 	MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1271 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \  argument
1272 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->max, cap)
1274 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1275 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1277 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \  argument
1278 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1280 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \  argument
1281 		MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1283 #define MLX5_CAP_FLOWTABLE_NIC_TX_MAX(mdev, cap) \  argument
1284 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit.cap)
1286 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1287 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1289 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \  argument
1290 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1292 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1293 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1295 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \  argument
1296 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1298 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \  argument
1299 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1301 #define MLX5_CAP_FLOWTABLE_RDMA_RX_MAX(mdev, cap) \  argument
1302 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_rdma.cap)
1304 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \  argument
1305 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1307 #define MLX5_CAP_FLOWTABLE_RDMA_TX_MAX(mdev, cap) \  argument
1308 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_rdma.cap)
1310 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1312 		 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1314 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \  argument
1316 		 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->max, cap)
1318 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1319 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1321 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \  argument
1322 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1324 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1325 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1327 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \  argument
1328 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1330 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1331 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1333 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \  argument
1334 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1336 #define MLX5_CAP_ESW(mdev, cap) \  argument
1338 		 mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap)
1340 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \  argument
1342 		(mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1344 #define MLX5_CAP_ESW_MAX(mdev, cap) \  argument
1346 		 mdev->caps.hca[MLX5_CAP_ESWITCH]->max, cap)
1348 #define MLX5_CAP_ODP(mdev, cap)\  argument
1349 	MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap)
1351 #define MLX5_CAP_ODP_MAX(mdev, cap)\  argument
1352 	MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap)
1354 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \  argument
1356 		 mdev->caps.hca[MLX5_CAP_VECTOR_CALC]->cur, cap)
1358 #define MLX5_CAP_QOS(mdev, cap)\  argument
1359 	MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap)
1361 #define MLX5_CAP_DEBUG(mdev, cap)\  argument
1362 	MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap)
1391 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1392 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1394 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1395 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1397 #define MLX5_CAP_DEV_MEM(mdev, cap)\  argument
1398 	MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1400 #define MLX5_CAP64_DEV_MEM(mdev, cap)\  argument
1401 	MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1403 #define MLX5_CAP_TLS(mdev, cap) \  argument
1404 	MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap)
1406 #define MLX5_CAP_DEV_EVENT(mdev, cap)\  argument
1407 	MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap)
1409 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\  argument
1411 		(mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1413 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\  argument
1415 		(mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1417 #define MLX5_CAP_IPSEC(mdev, cap)\  argument
1418 	MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap)