Lines Matching defs:cp_qe
54 struct cp_qe { struct
55 __be32 cecr; /* QE command register */
56 __be32 ceccr; /* QE controller configuration register */
57 __be32 cecdr; /* QE command data register */
58 u8 res0[0xA];
59 __be16 ceter; /* QE timer event register */
60 u8 res1[0x2];
61 __be16 cetmr; /* QE timers mask register */
62 __be32 cetscr; /* QE time-stamp timer control register */
63 __be32 cetsr1; /* QE time-stamp register 1 */
64 __be32 cetsr2; /* QE time-stamp register 2 */
65 u8 res2[0x8];
66 __be32 cevter; /* QE virtual tasks event register */
67 __be32 cevtmr; /* QE virtual tasks mask register */
68 __be16 cercr; /* QE RAM control register */
69 u8 res3[0x2];
70 u8 res4[0x24];
71 __be16 ceexe1; /* QE external request 1 event register */
72 u8 res5[0x2];
73 __be16 ceexm1; /* QE external request 1 mask register */
74 u8 res6[0x2];
75 __be16 ceexe2; /* QE external request 2 event register */
76 u8 res7[0x2];
77 __be16 ceexm2; /* QE external request 2 mask register */
78 u8 res8[0x2];
79 __be16 ceexe3; /* QE external request 3 event register */
80 u8 res9[0x2];
81 __be16 ceexm3; /* QE external request 3 mask register */
82 u8 res10[0x2];
83 __be16 ceexe4; /* QE external request 4 event register */
84 u8 res11[0x2];
85 __be16 ceexm4; /* QE external request 4 mask register */
86 u8 res12[0x3A];
87 __be32 ceurnr; /* QE microcode revision number register */
88 u8 res13[0x244];