Lines Matching refs:dma
457 struct cs4281_dma dma[4]; member
654 struct cs4281_dma *dma = substream->runtime->private_data; in snd_cs4281_trigger() local
660 dma->valDCR |= BA0_DCR_MSK; in snd_cs4281_trigger()
661 dma->valFCR |= BA0_FCR_FEN; in snd_cs4281_trigger()
664 dma->valDCR &= ~BA0_DCR_MSK; in snd_cs4281_trigger()
665 dma->valFCR &= ~BA0_FCR_FEN; in snd_cs4281_trigger()
669 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA); in snd_cs4281_trigger()
670 dma->valDMR |= BA0_DMR_DMA; in snd_cs4281_trigger()
671 dma->valDCR &= ~BA0_DCR_MSK; in snd_cs4281_trigger()
672 dma->valFCR |= BA0_FCR_FEN; in snd_cs4281_trigger()
676 dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL); in snd_cs4281_trigger()
677 dma->valDCR |= BA0_DCR_MSK; in snd_cs4281_trigger()
678 dma->valFCR &= ~BA0_FCR_FEN; in snd_cs4281_trigger()
680 if (dma->regFCR != BA0_FCR0) in snd_cs4281_trigger()
681 dma->valFCR &= ~BA0_FCR_FEN; in snd_cs4281_trigger()
687 snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR); in snd_cs4281_trigger()
688 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR); in snd_cs4281_trigger()
689 snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR); in snd_cs4281_trigger()
717 static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma, in snd_cs4281_mode() argument
723 dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO | in snd_cs4281_mode()
726 dma->valDMR |= BA0_DMR_MONO; in snd_cs4281_mode()
728 dma->valDMR |= BA0_DMR_USIGN; in snd_cs4281_mode()
730 dma->valDMR |= BA0_DMR_BEND; in snd_cs4281_mode()
732 case 8: dma->valDMR |= BA0_DMR_SIZE8; in snd_cs4281_mode()
734 dma->valDMR |= BA0_DMR_SWAPC; in snd_cs4281_mode()
736 case 32: dma->valDMR |= BA0_DMR_SIZE20; break; in snd_cs4281_mode()
738 dma->frag = 0; /* for workaround */ in snd_cs4281_mode()
739 dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK; in snd_cs4281_mode()
741 dma->valDCR |= BA0_DCR_HTCIE; in snd_cs4281_mode()
743 snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr); in snd_cs4281_mode()
744 snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1); in snd_cs4281_mode()
745 rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO; in snd_cs4281_mode()
753 if (dma->left_slot == chip->src_left_play_slot) { in snd_cs4281_mode()
755 snd_BUG_ON(dma->right_slot != chip->src_right_play_slot); in snd_cs4281_mode()
759 if (dma->left_slot == chip->src_left_rec_slot) { in snd_cs4281_mode()
761 snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot); in snd_cs4281_mode()
767 if (dma->regFCR == BA0_FCR0) in snd_cs4281_mode()
768 snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN); in snd_cs4281_mode()
770 dma->valFCR = BA0_FCR_LS(dma->left_slot) | in snd_cs4281_mode()
771 BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) | in snd_cs4281_mode()
773 BA0_FCR_OF(dma->fifo_offset); in snd_cs4281_mode()
774 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0)); in snd_cs4281_mode()
776 if (dma->regFCR == BA0_FCR0) in snd_cs4281_mode()
777 snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN); in snd_cs4281_mode()
779 snd_cs4281_pokeBA0(chip, dma->regFSIC, 0); in snd_cs4281_mode()
785 struct cs4281_dma *dma = runtime->private_data; in snd_cs4281_playback_prepare() local
789 snd_cs4281_mode(chip, dma, runtime, 0, 1); in snd_cs4281_playback_prepare()
797 struct cs4281_dma *dma = runtime->private_data; in snd_cs4281_capture_prepare() local
801 snd_cs4281_mode(chip, dma, runtime, 1, 1); in snd_cs4281_capture_prepare()
809 struct cs4281_dma *dma = runtime->private_data; in snd_cs4281_pointer() local
819 snd_cs4281_peekBA0(chip, dma->regDCC) - 1; in snd_cs4281_pointer()
876 struct cs4281_dma *dma; in snd_cs4281_playback_open() local
878 dma = &chip->dma[0]; in snd_cs4281_playback_open()
879 dma->substream = substream; in snd_cs4281_playback_open()
880 dma->left_slot = 0; in snd_cs4281_playback_open()
881 dma->right_slot = 1; in snd_cs4281_playback_open()
882 runtime->private_data = dma; in snd_cs4281_playback_open()
895 struct cs4281_dma *dma; in snd_cs4281_capture_open() local
897 dma = &chip->dma[1]; in snd_cs4281_capture_open()
898 dma->substream = substream; in snd_cs4281_capture_open()
899 dma->left_slot = 10; in snd_cs4281_capture_open()
900 dma->right_slot = 11; in snd_cs4281_capture_open()
901 runtime->private_data = dma; in snd_cs4281_capture_open()
912 struct cs4281_dma *dma = substream->runtime->private_data; in snd_cs4281_playback_close() local
914 dma->substream = NULL; in snd_cs4281_playback_close()
920 struct cs4281_dma *dma = substream->runtime->private_data; in snd_cs4281_capture_close() local
922 dma->substream = NULL; in snd_cs4281_capture_close()
1518 struct cs4281_dma *dma = &chip->dma[tmp]; in snd_cs4281_chip_init() local
1519 dma->regDBA = BA0_DBA0 + (tmp * 0x10); in snd_cs4281_chip_init()
1520 dma->regDCA = BA0_DCA0 + (tmp * 0x10); in snd_cs4281_chip_init()
1521 dma->regDBC = BA0_DBC0 + (tmp * 0x10); in snd_cs4281_chip_init()
1522 dma->regDCC = BA0_DCC0 + (tmp * 0x10); in snd_cs4281_chip_init()
1523 dma->regDMR = BA0_DMR0 + (tmp * 8); in snd_cs4281_chip_init()
1524 dma->regDCR = BA0_DCR0 + (tmp * 8); in snd_cs4281_chip_init()
1525 dma->regHDSR = BA0_HDSR0 + (tmp * 4); in snd_cs4281_chip_init()
1526 dma->regFCR = BA0_FCR0 + (tmp * 4); in snd_cs4281_chip_init()
1527 dma->regFSIC = BA0_FSIC0 + (tmp * 4); in snd_cs4281_chip_init()
1528 dma->fifo_offset = tmp * CS4281_FIFO_SIZE; in snd_cs4281_chip_init()
1529 snd_cs4281_pokeBA0(chip, dma->regFCR, in snd_cs4281_chip_init()
1533 BA0_FCR_OF(dma->fifo_offset)); in snd_cs4281_chip_init()
1542 chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) | in snd_cs4281_chip_init()
1545 BA0_FCR_OF(chip->dma[0].fifo_offset); in snd_cs4281_chip_init()
1546 snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR); in snd_cs4281_chip_init()
1736 unsigned int status, dma, val; in snd_cs4281_interrupt() local
1748 for (dma = 0; dma < 4; dma++) in snd_cs4281_interrupt()
1749 if (status & BA0_HISR_DMA(dma)) { in snd_cs4281_interrupt()
1750 cdma = &chip->dma[dma]; in snd_cs4281_interrupt()