99 					u32 reg)  in img_i2s_out_writel()  argument
101 	writel(val, i2s->base + reg);  in img_i2s_out_writel()
104 static inline u32 img_i2s_out_readl(struct img_i2s_out *i2s, u32 reg)  in img_i2s_out_readl()  argument
106 	return readl(i2s->base + reg);  in img_i2s_out_readl()
110 					u32 chan, u32 val, u32 reg)  in img_i2s_out_ch_writel()  argument
112 	writel(val, i2s->channel_base + (chan * IMG_I2S_OUT_CH_STRIDE) + reg);  in img_i2s_out_ch_writel()
116 					u32 reg)  in img_i2s_out_ch_readl()  argument
118 	return readl(i2s->channel_base + (chan * IMG_I2S_OUT_CH_STRIDE) + reg);  in img_i2s_out_ch_readl()
123 	u32 reg;  in img_i2s_out_ch_disable()  local
125 	reg = img_i2s_out_ch_readl(i2s, chan, IMG_I2S_OUT_CH_CTL);  in img_i2s_out_ch_disable()
126 	reg &= ~IMG_I2S_OUT_CHAN_CTL_ME_MASK;  in img_i2s_out_ch_disable()
127 	img_i2s_out_ch_writel(i2s, chan, reg, IMG_I2S_OUT_CH_CTL);  in img_i2s_out_ch_disable()
132 	u32 reg;  in img_i2s_out_ch_enable()  local
134 	reg = img_i2s_out_ch_readl(i2s, chan, IMG_I2S_OUT_CH_CTL);  in img_i2s_out_ch_enable()
135 	reg |= IMG_I2S_OUT_CHAN_CTL_ME_MASK;  in img_i2s_out_ch_enable()
136 	img_i2s_out_ch_writel(i2s, chan, reg, IMG_I2S_OUT_CH_CTL);  in img_i2s_out_ch_enable()
141 	u32 reg;  in img_i2s_out_disable()  local
143 	reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);  in img_i2s_out_disable()
144 	reg &= ~IMG_I2S_OUT_CTL_ME_MASK;  in img_i2s_out_disable()
145 	img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);  in img_i2s_out_disable()
150 	u32 reg;  in img_i2s_out_enable()  local
152 	reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);  in img_i2s_out_enable()
153 	reg |= IMG_I2S_OUT_CTL_ME_MASK;  in img_i2s_out_enable()
154 	img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);  in img_i2s_out_enable()
189 	u32 reg;  in img_i2s_out_trigger()  local
195 		reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);  in img_i2s_out_trigger()
197 			reg |= IMG_I2S_OUT_CTL_CLK_EN_MASK;  in img_i2s_out_trigger()
198 		reg |= IMG_I2S_OUT_CTL_DATA_EN_MASK;  in img_i2s_out_trigger()
199 		img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);  in img_i2s_out_trigger()
220 	u32 reg, control_mask, control_set = 0;  in img_i2s_out_hw_params()  local
274 	reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);  in img_i2s_out_hw_params()
275 	reg = (reg & ~control_mask) | control_set;  in img_i2s_out_hw_params()
276 	img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);  in img_i2s_out_hw_params()
297 	u32 reg, control_set = 0;  in img_i2s_out_set_fmt()  local
357 	reg = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL);  in img_i2s_out_set_fmt()
358 	reg = (reg & ~control_mask) | control_set;  in img_i2s_out_set_fmt()
359 	img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);  in img_i2s_out_set_fmt()
365 		reg = img_i2s_out_ch_readl(i2s, i, IMG_I2S_OUT_CH_CTL);  in img_i2s_out_set_fmt()
366 		reg = (reg & ~chan_control_mask) | chan_control_set;  in img_i2s_out_set_fmt()
367 		img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL);  in img_i2s_out_set_fmt()
432 	u32 reg;  in img_i2s_out_probe()  local
497 	reg = IMG_I2S_OUT_CTL_FRM_SIZE_MASK;  in img_i2s_out_probe()
498 	img_i2s_out_writel(i2s, reg, IMG_I2S_OUT_CTL);  in img_i2s_out_probe()
500 	reg = IMG_I2S_OUT_CHAN_CTL_JUST_MASK |  in img_i2s_out_probe()
506 		img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL);  in img_i2s_out_probe()
558 	u32 reg;  in img_i2s_out_suspend()  local
567 		reg = img_i2s_out_ch_readl(i2s, i, IMG_I2S_OUT_CH_CTL);  in img_i2s_out_suspend()
568 		i2s->suspend_ch_ctl[i] = reg;  in img_i2s_out_suspend()
582 	u32 reg;  in img_i2s_out_resume()  local
589 		reg = i2s->suspend_ch_ctl[i];  in img_i2s_out_resume()
590 		img_i2s_out_ch_writel(i2s, i, reg, IMG_I2S_OUT_CH_CTL);  in img_i2s_out_resume()