1083 				 struct afe_clk_cfg *cfg)  in q6afe_port_set_lpass_clock()  argument
1085 	return q6afe_port_set_param_v2(port, cfg,  in q6afe_port_set_lpass_clock()
1088 				       sizeof(*cfg));  in q6afe_port_set_lpass_clock()
1092 				 struct afe_clk_set *cfg)  in q6afe_set_lpass_clock_v2()  argument
1094 	return q6afe_port_set_param(port, cfg, AFE_PARAM_ID_CLOCK_SET,  in q6afe_set_lpass_clock_v2()
1095 				    AFE_MODULE_CLOCK_SET, sizeof(*cfg));  in q6afe_set_lpass_clock_v2()
1099 					      struct afe_digital_clk_cfg *cfg)  in q6afe_set_digital_codec_core_clock()  argument
1101 	return q6afe_port_set_param_v2(port, cfg,  in q6afe_set_digital_codec_core_clock()
1104 				       sizeof(*cfg));  in q6afe_set_digital_codec_core_clock()
1239 			     struct q6afe_slim_cfg *cfg)  in q6afe_slim_port_prepare()  argument
1244 	pcfg->slim_cfg.sample_rate = cfg->sample_rate;  in q6afe_slim_port_prepare()
1245 	pcfg->slim_cfg.bit_width = cfg->bit_width;  in q6afe_slim_port_prepare()
1246 	pcfg->slim_cfg.num_channels = cfg->num_channels;  in q6afe_slim_port_prepare()
1247 	pcfg->slim_cfg.data_format = cfg->data_format;  in q6afe_slim_port_prepare()
1248 	pcfg->slim_cfg.shared_ch_mapping[0] = cfg->ch_mapping[0];  in q6afe_slim_port_prepare()
1249 	pcfg->slim_cfg.shared_ch_mapping[1] = cfg->ch_mapping[1];  in q6afe_slim_port_prepare()
1250 	pcfg->slim_cfg.shared_ch_mapping[2] = cfg->ch_mapping[2];  in q6afe_slim_port_prepare()
1251 	pcfg->slim_cfg.shared_ch_mapping[3] = cfg->ch_mapping[3];  in q6afe_slim_port_prepare()
1264 			     struct q6afe_tdm_cfg *cfg)  in q6afe_tdm_port_prepare()  argument
1269 	pcfg->tdm_cfg.num_channels = cfg->num_channels;  in q6afe_tdm_port_prepare()
1270 	pcfg->tdm_cfg.sample_rate = cfg->sample_rate;  in q6afe_tdm_port_prepare()
1271 	pcfg->tdm_cfg.bit_width = cfg->bit_width;  in q6afe_tdm_port_prepare()
1272 	pcfg->tdm_cfg.data_format = cfg->data_format;  in q6afe_tdm_port_prepare()
1273 	pcfg->tdm_cfg.sync_mode = cfg->sync_mode;  in q6afe_tdm_port_prepare()
1274 	pcfg->tdm_cfg.sync_src = cfg->sync_src;  in q6afe_tdm_port_prepare()
1275 	pcfg->tdm_cfg.nslots_per_frame = cfg->nslots_per_frame;  in q6afe_tdm_port_prepare()
1277 	pcfg->tdm_cfg.slot_width = cfg->slot_width;  in q6afe_tdm_port_prepare()
1278 	pcfg->tdm_cfg.slot_mask = cfg->slot_mask;  in q6afe_tdm_port_prepare()
1284 	port->scfg->num_channels = cfg->num_channels;  in q6afe_tdm_port_prepare()
1285 	port->scfg->bitwidth = cfg->bit_width;  in q6afe_tdm_port_prepare()
1286 	port->scfg->data_align_type = cfg->data_align_type;  in q6afe_tdm_port_prepare()
1287 	memcpy(port->scfg->ch_mapping, cfg->ch_mapping,  in q6afe_tdm_port_prepare()
1300 			     struct q6afe_hdmi_cfg *cfg)  in q6afe_hdmi_port_prepare()  argument
1306 	pcfg->hdmi_multi_ch.datatype = cfg->datatype;  in q6afe_hdmi_port_prepare()
1307 	pcfg->hdmi_multi_ch.channel_allocation = cfg->channel_allocation;  in q6afe_hdmi_port_prepare()
1308 	pcfg->hdmi_multi_ch.sample_rate = cfg->sample_rate;  in q6afe_hdmi_port_prepare()
1309 	pcfg->hdmi_multi_ch.bit_width = cfg->bit_width;  in q6afe_hdmi_port_prepare()
1320 int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg)  in q6afe_i2s_port_prepare()  argument
1327 	pcfg->i2s_cfg.sample_rate = cfg->sample_rate;  in q6afe_i2s_port_prepare()
1328 	pcfg->i2s_cfg.bit_width = cfg->bit_width;  in q6afe_i2s_port_prepare()
1331 	switch (cfg->fmt & SND_SOC_DAIFMT_MASTER_MASK) {  in q6afe_i2s_port_prepare()
1343 	num_sd_lines = hweight_long(cfg->sd_line_mask);  in q6afe_i2s_port_prepare()
1350 		switch (cfg->sd_line_mask) {  in q6afe_i2s_port_prepare()
1369 		switch (cfg->sd_line_mask) {  in q6afe_i2s_port_prepare()
1382 		switch (cfg->sd_line_mask) {  in q6afe_i2s_port_prepare()
1392 		switch (cfg->sd_line_mask) {  in q6afe_i2s_port_prepare()
1407 	switch (cfg->num_channels) {  in q6afe_i2s_port_prepare()
1421 		if (cfg->num_channels == 2)  in q6afe_i2s_port_prepare()
1464 				struct q6afe_cdc_dma_cfg *cfg)  in q6afe_cdc_dma_port_prepare()  argument
1470 	dma_cfg->sample_rate = cfg->sample_rate;  in q6afe_cdc_dma_port_prepare()
1471 	dma_cfg->bit_width = cfg->bit_width;  in q6afe_cdc_dma_port_prepare()
1472 	dma_cfg->data_format = cfg->data_format;  in q6afe_cdc_dma_port_prepare()
1473 	dma_cfg->num_channels = cfg->num_channels;  in q6afe_cdc_dma_port_prepare()
1474 	if (!cfg->active_channels_mask)  in q6afe_cdc_dma_port_prepare()
1475 		dma_cfg->active_channels_mask = (1 << cfg->num_channels) - 1;  in q6afe_cdc_dma_port_prepare()