25 static inline void tegra30_apbif_write(u32 reg, u32 val)  in tegra30_apbif_write()  argument
27 	regmap_write(ahub->regmap_apbif, reg, val);  in tegra30_apbif_write()
30 static inline u32 tegra30_apbif_read(u32 reg)  in tegra30_apbif_read()  argument
34 	regmap_read(ahub->regmap_apbif, reg, &val);  in tegra30_apbif_read()
38 static inline void tegra30_audio_write(u32 reg, u32 val)  in tegra30_audio_write()  argument
40 	regmap_write(ahub->regmap_ahub, reg, val);  in tegra30_audio_write()
108 	u32 reg, val;  in tegra30_ahub_allocate_rx_fifo()  local
125 	reg = TEGRA30_AHUB_CHANNEL_CTRL +  in tegra30_ahub_allocate_rx_fifo()
127 	val = tegra30_apbif_read(reg);  in tegra30_ahub_allocate_rx_fifo()
133 	tegra30_apbif_write(reg, val);  in tegra30_ahub_allocate_rx_fifo()
147 	reg = TEGRA30_AHUB_CIF_RX_CTRL +  in tegra30_ahub_allocate_rx_fifo()
149 	ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf);  in tegra30_ahub_allocate_rx_fifo()
160 	int reg, val;  in tegra30_ahub_enable_rx_fifo()  local
164 	reg = TEGRA30_AHUB_CHANNEL_CTRL +  in tegra30_ahub_enable_rx_fifo()
166 	val = tegra30_apbif_read(reg);  in tegra30_ahub_enable_rx_fifo()
168 	tegra30_apbif_write(reg, val);  in tegra30_ahub_enable_rx_fifo()
179 	int reg, val;  in tegra30_ahub_disable_rx_fifo()  local
183 	reg = TEGRA30_AHUB_CHANNEL_CTRL +  in tegra30_ahub_disable_rx_fifo()
185 	val = tegra30_apbif_read(reg);  in tegra30_ahub_disable_rx_fifo()
187 	tegra30_apbif_write(reg, val);  in tegra30_ahub_disable_rx_fifo()
210 	u32 reg, val;  in tegra30_ahub_allocate_tx_fifo()  local
227 	reg = TEGRA30_AHUB_CHANNEL_CTRL +  in tegra30_ahub_allocate_tx_fifo()
229 	val = tegra30_apbif_read(reg);  in tegra30_ahub_allocate_tx_fifo()
235 	tegra30_apbif_write(reg, val);  in tegra30_ahub_allocate_tx_fifo()
249 	reg = TEGRA30_AHUB_CIF_TX_CTRL +  in tegra30_ahub_allocate_tx_fifo()
251 	ahub->soc_data->set_audio_cif(ahub->regmap_apbif, reg, &cif_conf);  in tegra30_ahub_allocate_tx_fifo()
262 	int reg, val;  in tegra30_ahub_enable_tx_fifo()  local
266 	reg = TEGRA30_AHUB_CHANNEL_CTRL +  in tegra30_ahub_enable_tx_fifo()
268 	val = tegra30_apbif_read(reg);  in tegra30_ahub_enable_tx_fifo()
270 	tegra30_apbif_write(reg, val);  in tegra30_ahub_enable_tx_fifo()
281 	int reg, val;  in tegra30_ahub_disable_tx_fifo()  local
285 	reg = TEGRA30_AHUB_CHANNEL_CTRL +  in tegra30_ahub_disable_tx_fifo()
287 	val = tegra30_apbif_read(reg);  in tegra30_ahub_disable_tx_fifo()
289 	tegra30_apbif_write(reg, val);  in tegra30_ahub_disable_tx_fifo()
311 	int reg;  in tegra30_ahub_set_rx_cif_source()  local
315 	reg = TEGRA30_AHUB_AUDIO_RX +  in tegra30_ahub_set_rx_cif_source()
317 	tegra30_audio_write(reg, 1 << txcif);  in tegra30_ahub_set_rx_cif_source()
328 	int reg;  in tegra30_ahub_unset_rx_cif_source()  local
332 	reg = TEGRA30_AHUB_AUDIO_RX +  in tegra30_ahub_unset_rx_cif_source()
334 	tegra30_audio_write(reg, 0);  in tegra30_ahub_unset_rx_cif_source()
370 #define REG_IN_ARRAY(reg, name) \  argument
371 	((reg >= TEGRA30_AHUB_##name) && \
372 	 (reg <= LAST_REG(name) && \
373 	 (!((reg - TEGRA30_AHUB_##name) % TEGRA30_AHUB_##name##_STRIDE))))
375 static bool tegra30_ahub_apbif_wr_rd_reg(struct device *dev, unsigned int reg)  in tegra30_ahub_apbif_wr_rd_reg()  argument
377 	switch (reg) {  in tegra30_ahub_apbif_wr_rd_reg()
404 	if (REG_IN_ARRAY(reg, CHANNEL_CTRL) ||  in tegra30_ahub_apbif_wr_rd_reg()
405 	    REG_IN_ARRAY(reg, CHANNEL_CLEAR) ||  in tegra30_ahub_apbif_wr_rd_reg()
406 	    REG_IN_ARRAY(reg, CHANNEL_STATUS) ||  in tegra30_ahub_apbif_wr_rd_reg()
407 	    REG_IN_ARRAY(reg, CHANNEL_TXFIFO) ||  in tegra30_ahub_apbif_wr_rd_reg()
408 	    REG_IN_ARRAY(reg, CHANNEL_RXFIFO) ||  in tegra30_ahub_apbif_wr_rd_reg()
409 	    REG_IN_ARRAY(reg, CIF_TX_CTRL) ||  in tegra30_ahub_apbif_wr_rd_reg()
410 	    REG_IN_ARRAY(reg, CIF_RX_CTRL) ||  in tegra30_ahub_apbif_wr_rd_reg()
411 	    REG_IN_ARRAY(reg, DAM_LIVE_STATUS))  in tegra30_ahub_apbif_wr_rd_reg()
418 					    unsigned int reg)  in tegra30_ahub_apbif_volatile_reg()  argument
420 	switch (reg) {  in tegra30_ahub_apbif_volatile_reg()
439 	if (REG_IN_ARRAY(reg, CHANNEL_CLEAR) ||  in tegra30_ahub_apbif_volatile_reg()
440 	    REG_IN_ARRAY(reg, CHANNEL_STATUS) ||  in tegra30_ahub_apbif_volatile_reg()
441 	    REG_IN_ARRAY(reg, CHANNEL_TXFIFO) ||  in tegra30_ahub_apbif_volatile_reg()
442 	    REG_IN_ARRAY(reg, CHANNEL_RXFIFO) ||  in tegra30_ahub_apbif_volatile_reg()
443 	    REG_IN_ARRAY(reg, DAM_LIVE_STATUS))  in tegra30_ahub_apbif_volatile_reg()
450 					    unsigned int reg)  in tegra30_ahub_apbif_precious_reg()  argument
452 	if (REG_IN_ARRAY(reg, CHANNEL_TXFIFO) ||  in tegra30_ahub_apbif_precious_reg()
453 	    REG_IN_ARRAY(reg, CHANNEL_RXFIFO))  in tegra30_ahub_apbif_precious_reg()
472 static bool tegra30_ahub_ahub_wr_rd_reg(struct device *dev, unsigned int reg)  in tegra30_ahub_ahub_wr_rd_reg()  argument
474 	if (REG_IN_ARRAY(reg, AUDIO_RX))  in tegra30_ahub_ahub_wr_rd_reg()
622 void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg,  in tegra30_ahub_set_cif()  argument
650 	regmap_write(regmap, reg, value);  in tegra30_ahub_set_cif()
654 void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg,  in tegra124_ahub_set_cif()  argument
682 	regmap_write(regmap, reg, value);  in tegra124_ahub_set_cif()