111 	u32 v;  in aio_chip_set_pll()  local
137 		v = A2APLLCTR1_APLLX_36MHZ;  in aio_chip_set_pll()
140 		v = A2APLLCTR1_APLLX_33MHZ;  in aio_chip_set_pll()
149 			   v << shift);  in aio_chip_set_pll()
333 	u32 v;  in aio_port_set_rate()  local
338 			v = OPORTMXCTR1_FSSEL_8;  in aio_port_set_rate()
341 			v = OPORTMXCTR1_FSSEL_11_025;  in aio_port_set_rate()
344 			v = OPORTMXCTR1_FSSEL_12;  in aio_port_set_rate()
347 			v = OPORTMXCTR1_FSSEL_16;  in aio_port_set_rate()
350 			v = OPORTMXCTR1_FSSEL_22_05;  in aio_port_set_rate()
353 			v = OPORTMXCTR1_FSSEL_24;  in aio_port_set_rate()
356 			v = OPORTMXCTR1_FSSEL_32;  in aio_port_set_rate()
359 			v = OPORTMXCTR1_FSSEL_44_1;  in aio_port_set_rate()
362 			v = OPORTMXCTR1_FSSEL_48;  in aio_port_set_rate()
365 			v = OPORTMXCTR1_FSSEL_88_2;  in aio_port_set_rate()
368 			v = OPORTMXCTR1_FSSEL_96;  in aio_port_set_rate()
371 			v = OPORTMXCTR1_FSSEL_176_4;  in aio_port_set_rate()
374 			v = OPORTMXCTR1_FSSEL_192;  in aio_port_set_rate()
382 				   OPORTMXCTR1_FSSEL_MASK, v);  in aio_port_set_rate()
386 			v = IPORTMXCTR1_FSSEL_8;  in aio_port_set_rate()
389 			v = IPORTMXCTR1_FSSEL_11_025;  in aio_port_set_rate()
392 			v = IPORTMXCTR1_FSSEL_12;  in aio_port_set_rate()
395 			v = IPORTMXCTR1_FSSEL_16;  in aio_port_set_rate()
398 			v = IPORTMXCTR1_FSSEL_22_05;  in aio_port_set_rate()
401 			v = IPORTMXCTR1_FSSEL_24;  in aio_port_set_rate()
404 			v = IPORTMXCTR1_FSSEL_32;  in aio_port_set_rate()
407 			v = IPORTMXCTR1_FSSEL_44_1;  in aio_port_set_rate()
410 			v = IPORTMXCTR1_FSSEL_48;  in aio_port_set_rate()
413 			v = IPORTMXCTR1_FSSEL_88_2;  in aio_port_set_rate()
416 			v = IPORTMXCTR1_FSSEL_96;  in aio_port_set_rate()
419 			v = IPORTMXCTR1_FSSEL_176_4;  in aio_port_set_rate()
422 			v = IPORTMXCTR1_FSSEL_192;  in aio_port_set_rate()
430 				   IPORTMXCTR1_FSSEL_MASK, v);  in aio_port_set_rate()
452 	u32 v;  in aio_port_set_fmt()  local
457 			v = OPORTMXCTR1_I2SLRSEL_LEFT;  in aio_port_set_fmt()
460 			v = OPORTMXCTR1_I2SLRSEL_RIGHT;  in aio_port_set_fmt()
463 			v = OPORTMXCTR1_I2SLRSEL_I2S;  in aio_port_set_fmt()
471 		v |= OPORTMXCTR1_OUTBITSEL_24;  in aio_port_set_fmt()
474 				   OPORTMXCTR1_OUTBITSEL_MASK, v);  in aio_port_set_fmt()
478 			v = IPORTMXCTR1_LRSEL_LEFT;  in aio_port_set_fmt()
481 			v = IPORTMXCTR1_LRSEL_RIGHT;  in aio_port_set_fmt()
484 			v = IPORTMXCTR1_LRSEL_I2S;  in aio_port_set_fmt()
492 		v |= IPORTMXCTR1_OUTBITSEL_24 |  in aio_port_set_fmt()
497 				   IPORTMXCTR1_CHSEL_MASK, v);  in aio_port_set_fmt()
528 	u32 v;  in aio_port_set_clk()  local
543 			v = v_pll[sub->aio->pll_out] |  in aio_port_set_clk()
551 				v |= OPORTMXCTR2_EXTLSIFSSEL_36;  in aio_port_set_clk()
554 				v |= OPORTMXCTR2_EXTLSIFSSEL_24;  in aio_port_set_clk()
558 			v = OPORTMXCTR2_ACLKSEL_A2PLL |  in aio_port_set_clk()
568 			v = v_pll[sub->aio->pll_out] |  in aio_port_set_clk()
576 				v |= OPORTMXCTR2_EXTLSIFSSEL_36;  in aio_port_set_clk()
579 				v |= OPORTMXCTR2_EXTLSIFSSEL_24;  in aio_port_set_clk()
583 			v = OPORTMXCTR2_ACLKSEL_A1 |  in aio_port_set_clk()
588 		regmap_write(r, OPORTMXCTR2(sub->swm->oport.map), v);  in aio_port_set_clk()
590 		v = IPORTMXCTR2_ACLKSEL_A1 |  in aio_port_set_clk()
594 		regmap_write(r, IPORTMXCTR2(sub->swm->iport.map), v);  in aio_port_set_clk()
617 	u32 v;  in aio_port_set_param()  local
647 			v = OPORTMXCTR3_SRCSEL_STREAM |  in aio_port_set_param()
650 			v = OPORTMXCTR3_SRCSEL_PCM |  in aio_port_set_param()
653 		v |= OPORTMXCTR3_IECTHUR_IECOUT |  in aio_port_set_param()
656 		regmap_write(r, OPORTMXCTR3(sub->swm->oport.map), v);  in aio_port_set_param()
725 	u32 v;  in aio_port_get_volume()  local
727 	regmap_read(r, OPORTMXTYVOLGAINSTATUS(sub->swm->oport.map, 0), &v);  in aio_port_get_volume()
729 	return FIELD_GET(OPORTMXTYVOLGAINSTATUS_CUR_MASK, v);  in aio_port_get_volume()
788 	u32 memfmt, v;  in aio_if_set_param()  local
792 			v = PBOUTMXCTR0_ENDIAN_0123 |  in aio_if_set_param()
808 			v = PBOUTMXCTR0_ENDIAN_3210 | memfmt;  in aio_if_set_param()
811 		regmap_write(r, PBOUTMXCTR0(sub->swm->oif.map), v);  in aio_if_set_param()
922 	u32 v;  in aio_src_set_param()  local
937 		v = OPORTMXRATE_I_ACLKSEL_APLLA1 |  in aio_src_set_param()
942 		v = OPORTMXRATE_I_ACLKSEL_APLLA2 |  in aio_src_set_param()
947 		v = OPORTMXRATE_I_ACLKSEL_APLLA1 |  in aio_src_set_param()
954 		     v | OPORTMXRATE_I_ACLKSRC_APLL |  in aio_src_set_param()
1001 	u32 v;  in aio_srcch_set_enable()  local
1004 		v = CDA2D_STRT0_STOP_START;  in aio_srcch_set_enable()
1006 		v = CDA2D_STRT0_STOP_STOP;  in aio_srcch_set_enable()
1009 		     v | BIT(sub->swm->och.map));  in aio_srcch_set_enable()
1015 	u32 v;  in aiodma_ch_set_param()  local
1020 	v = CDA2D_CHMXAMODE_ENDIAN_3210 |  in aiodma_ch_set_param()
1025 		regmap_write(r, CDA2D_CHMXSRCAMODE(sub->swm->ch.map), v);  in aiodma_ch_set_param()
1027 		regmap_write(r, CDA2D_CHMXDSTAMODE(sub->swm->ch.map), v);  in aiodma_ch_set_param()