23 	u64 val = 0;  in guest_code()  local
25 	GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val);  in guest_code()
26 	GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val);  in guest_code()
29 	val = 1ull * GUEST_STEP;  in guest_code()
30 	wrmsr(MSR_IA32_TSC, val);  in guest_code()
31 	GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val);  in guest_code()
32 	GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val);  in guest_code()
36 	val = 2ull * GUEST_STEP;  in guest_code()
37 	wrmsr(MSR_IA32_TSC_ADJUST, val);  in guest_code()
38 	GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val);  in guest_code()
39 	GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val);  in guest_code()
43 	GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);  in guest_code()
44 	GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val);  in guest_code()
51 	val = 3ull * GUEST_STEP;  in guest_code()
52 	wrmsr(MSR_IA32_TSC_ADJUST, val);  in guest_code()
53 	GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);  in guest_code()
54 	GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val);  in guest_code()
61 	val = 4ull * GUEST_STEP;  in guest_code()
62 	wrmsr(MSR_IA32_TSC, val);  in guest_code()
63 	GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val);  in guest_code()
64 	GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC_ADJUST), val - HOST_ADJUST);  in guest_code()
98 	uint64_t val;  in main()  local
102 	val = 0;  in main()
103 	ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), val);  in main()
104 	ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC_ADJUST), val);  in main()
108 	val = 1ull * GUEST_STEP;  in main()
109 	ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), val);  in main()
110 	ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC_ADJUST), val);  in main()
114 	val = 2ull * GUEST_STEP;  in main()
115 	ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), val);  in main()
116 	ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC_ADJUST), val);  in main()
122 	vcpu_set_msr(vm, 0, MSR_IA32_TSC, HOST_ADJUST + val);  in main()
123 	ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);  in main()
124 	ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC_ADJUST), val);  in main()
129 	ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);  in main()
133 	vcpu_set_msr(vm, 0, MSR_IA32_TSC_ADJUST, val);  in main()
134 	ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);  in main()
135 	ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC_ADJUST), val);  in main()
142 	val = 3ull * GUEST_STEP;  in main()
143 	ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val);  in main()
144 	ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC_ADJUST), val);  in main()
151 	val = 4ull * GUEST_STEP;  in main()
152 	ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC), val);  in main()
153 	ASSERT_EQ(rounded_host_rdmsr(MSR_IA32_TSC_ADJUST), val - HOST_ADJUST);  in main()