1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_CCA_REQUIRED if ACPI 5 select ACPI_GENERIC_GSI if ACPI 6 select ACPI_GTDT if ACPI 7 select ACPI_IORT if ACPI 8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 9 select ACPI_MCFG if (ACPI && PCI) 10 select ACPI_SPCR_TABLE if ACPI 11 select ACPI_PPTT if ACPI 12 select ARCH_HAS_DEBUG_WX 13 select ARCH_BINFMT_ELF_EXTRA_PHDRS 14 select ARCH_BINFMT_ELF_STATE 15 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 16 select ARCH_ENABLE_MEMORY_HOTPLUG 17 select ARCH_ENABLE_MEMORY_HOTREMOVE 18 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 19 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 20 select ARCH_HAS_CACHE_LINE_SIZE 21 select ARCH_HAS_DEBUG_VIRTUAL 22 select ARCH_HAS_DEBUG_VM_PGTABLE 23 select ARCH_HAS_DMA_PREP_COHERENT 24 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 25 select ARCH_HAS_FAST_MULTIPLIER 26 select ARCH_HAS_FORTIFY_SOURCE 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_HAS_GIGANTIC_PAGE 29 select ARCH_HAS_IOREMAP_PHYS_HOOKS 30 select ARCH_HAS_KCOV 31 select ARCH_HAS_KEEPINITRD 32 select ARCH_HAS_MEMBARRIER_SYNC_CORE 33 select ARCH_HAS_MEM_ENCRYPT 34 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 35 select ARCH_HAS_PTE_DEVMAP 36 select ARCH_HAS_PTE_SPECIAL 37 select ARCH_HAS_SETUP_DMA_OPS 38 select ARCH_HAS_SET_DIRECT_MAP 39 select ARCH_HAS_SET_MEMORY 40 select ARCH_STACKWALK 41 select ARCH_HAS_STRICT_KERNEL_RWX 42 select ARCH_HAS_STRICT_MODULE_RWX 43 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 44 select ARCH_HAS_SYNC_DMA_FOR_CPU 45 select ARCH_HAS_SYSCALL_WRAPPER 46 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT 47 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 48 select ARCH_HAS_ZONE_DMA_SET if EXPERT 49 select ARCH_HAVE_ELF_PROT 50 select ARCH_HAVE_NMI_SAFE_CMPXCHG 51 select ARCH_HAVE_TRACE_MMIO_ACCESS 52 select ARCH_INLINE_READ_LOCK if !PREEMPTION 53 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 54 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 55 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 56 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 57 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 58 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 59 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 60 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 61 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 62 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 63 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 64 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 65 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 66 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 67 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 68 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 69 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 70 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 71 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 72 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 73 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 74 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 75 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 76 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 77 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 78 select ARCH_KEEP_MEMBLOCK 79 select ARCH_USE_CMPXCHG_LOCKREF 80 select ARCH_USE_GNU_PROPERTY 81 select ARCH_USE_MEMTEST 82 select ARCH_USE_QUEUED_RWLOCKS 83 select ARCH_USE_QUEUED_SPINLOCKS 84 select ARCH_USE_SYM_ANNOTATIONS 85 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 86 select ARCH_SUPPORTS_HUGETLBFS 87 select ARCH_SUPPORTS_MEMORY_FAILURE 88 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 89 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 90 select ARCH_SUPPORTS_LTO_CLANG_THIN 91 select ARCH_SUPPORTS_CFI_CLANG 92 select ARCH_SUPPORTS_ATOMIC_RMW 93 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 94 select ARCH_SUPPORTS_NUMA_BALANCING 95 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 96 select ARCH_WANT_DEFAULT_BPF_JIT 97 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 98 select ARCH_WANT_FRAME_POINTERS 99 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 100 select ARCH_WANT_LD_ORPHAN_WARN 101 select ARCH_WANTS_NO_INSTR 102 select ARCH_HAS_UBSAN_SANITIZE_ALL 103 select ARM_AMBA 104 select ARM_ARCH_TIMER 105 select ARM_GIC 106 select AUDIT_ARCH_COMPAT_GENERIC 107 select ARM_GIC_V2M if PCI 108 select ARM_GIC_V3 109 select ARM_GIC_V3_ITS if PCI 110 select ARM_PSCI_FW 111 select BUILDTIME_TABLE_SORT 112 select CLONE_BACKWARDS 113 select COMMON_CLK 114 select CPU_PM if (SUSPEND || CPU_IDLE) 115 select CRC32 116 select DCACHE_WORD_ACCESS 117 select DMA_DIRECT_REMAP 118 select EDAC_SUPPORT 119 select FRAME_POINTER 120 select GENERIC_ALLOCATOR 121 select GENERIC_ARCH_TOPOLOGY 122 select GENERIC_CLOCKEVENTS_BROADCAST 123 select GENERIC_CPU_AUTOPROBE 124 select GENERIC_CPU_VULNERABILITIES 125 select GENERIC_EARLY_IOREMAP 126 select GENERIC_FIND_FIRST_BIT 127 select GENERIC_IDLE_POLL_SETUP 128 select GENERIC_IRQ_IPI 129 select ARCH_WANTS_IRQ_RAW 130 select GENERIC_IRQ_PROBE 131 select GENERIC_IRQ_SHOW 132 select GENERIC_IRQ_SHOW_LEVEL 133 select GENERIC_LIB_DEVMEM_IS_ALLOWED 134 select GENERIC_PCI_IOMAP 135 select GENERIC_PTDUMP 136 select GENERIC_SCHED_CLOCK 137 select GENERIC_SMP_IDLE_THREAD 138 select GENERIC_TIME_VSYSCALL 139 select GENERIC_GETTIMEOFDAY 140 select GENERIC_VDSO_TIME_NS 141 select HANDLE_DOMAIN_IRQ 142 select HARDIRQS_SW_RESEND 143 select HAVE_MOVE_PMD 144 select HAVE_MOVE_PUD 145 select HAVE_PCI 146 select HAVE_ACPI_APEI if (ACPI && EFI) 147 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 148 select HAVE_ARCH_AUDITSYSCALL 149 select HAVE_ARCH_BITREVERSE 150 select HAVE_ARCH_COMPILER_H 151 select HAVE_ARCH_HUGE_VMAP 152 select HAVE_ARCH_JUMP_LABEL 153 select HAVE_ARCH_JUMP_LABEL_RELATIVE 154 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 155 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 156 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 157 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 158 select HAVE_ARCH_KFENCE 159 select HAVE_ARCH_KGDB 160 select HAVE_ARCH_MMAP_RND_BITS 161 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 162 select HAVE_ARCH_PREL32_RELOCATIONS 163 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 164 select HAVE_ARCH_SECCOMP_FILTER 165 select HAVE_ARCH_STACKLEAK 166 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 167 select HAVE_ARCH_TRACEHOOK 168 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 169 select HAVE_ARCH_VMAP_STACK 170 select HAVE_ARM_SMCCC 171 select HAVE_ASM_MODVERSIONS 172 select HAVE_EBPF_JIT 173 select HAVE_C_RECORDMCOUNT 174 select HAVE_CMPXCHG_DOUBLE 175 select HAVE_CMPXCHG_LOCAL 176 select HAVE_CONTEXT_TRACKING 177 select HAVE_DEBUG_KMEMLEAK 178 select HAVE_DMA_CONTIGUOUS 179 select HAVE_DYNAMIC_FTRACE 180 select HAVE_DYNAMIC_FTRACE_WITH_REGS \ 181 if $(cc-option,-fpatchable-function-entry=2) 182 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 183 if DYNAMIC_FTRACE_WITH_REGS 184 select HAVE_EFFICIENT_UNALIGNED_ACCESS 185 select HAVE_FAST_GUP 186 select HAVE_FTRACE_MCOUNT_RECORD 187 select HAVE_FUNCTION_TRACER 188 select HAVE_FUNCTION_ERROR_INJECTION 189 select HAVE_FUNCTION_GRAPH_TRACER 190 select HAVE_GCC_PLUGINS 191 select HAVE_HW_BREAKPOINT if PERF_EVENTS 192 select HAVE_IRQ_TIME_ACCOUNTING 193 select HAVE_KVM 194 select HAVE_NMI 195 select HAVE_PATA_PLATFORM 196 select HAVE_PERF_EVENTS 197 select HAVE_PERF_REGS 198 select HAVE_PERF_USER_STACK_DUMP 199 select HAVE_REGS_AND_STACK_ACCESS_API 200 select HAVE_FUNCTION_ARG_ACCESS_API 201 select HAVE_FUTEX_CMPXCHG if FUTEX 202 select MMU_GATHER_RCU_TABLE_FREE 203 select HAVE_RSEQ 204 select HAVE_STACKPROTECTOR 205 select HAVE_SYSCALL_TRACEPOINTS 206 select HAVE_KPROBES 207 select HAVE_KRETPROBES 208 select HAVE_GENERIC_VDSO 209 select IOMMU_DMA if IOMMU_SUPPORT 210 select IRQ_DOMAIN 211 select IRQ_FORCED_THREADING 212 select KASAN_VMALLOC if KASAN 213 select MODULES_USE_ELF_RELA 214 select NEED_DMA_MAP_STATE 215 select NEED_SG_DMA_LENGTH 216 select OF 217 select OF_EARLY_FLATTREE 218 select PCI_DOMAINS_GENERIC if PCI 219 select PCI_ECAM if (ACPI && PCI) 220 select PCI_SYSCALL if PCI 221 select POWER_RESET 222 select POWER_SUPPLY 223 select SPARSE_IRQ 224 select SWIOTLB 225 select SYSCTL_EXCEPTION_TRACE 226 select THREAD_INFO_IN_TASK 227 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 228 select TRACE_IRQFLAGS_SUPPORT 229 select TRACE_IRQFLAGS_NMI_SUPPORT 230 select ARCH_SUPPORTS_SPECULATIVE_PAGE_FAULT 231 help 232 ARM 64-bit (AArch64) Linux support. 233 234config 64BIT 235 def_bool y 236 237config MMU 238 def_bool y 239 240config ARM64_PAGE_SHIFT 241 int 242 default 16 if ARM64_64K_PAGES 243 default 14 if ARM64_16K_PAGES 244 default 12 245 246config ARM64_CONT_PTE_SHIFT 247 int 248 default 5 if ARM64_64K_PAGES 249 default 7 if ARM64_16K_PAGES 250 default 4 251 252config ARM64_CONT_PMD_SHIFT 253 int 254 default 5 if ARM64_64K_PAGES 255 default 5 if ARM64_16K_PAGES 256 default 4 257 258config ARCH_MMAP_RND_BITS_MIN 259 default 14 if ARM64_64K_PAGES 260 default 16 if ARM64_16K_PAGES 261 default 18 262 263# max bits determined by the following formula: 264# VA_BITS - PAGE_SHIFT - 3 265config ARCH_MMAP_RND_BITS_MAX 266 default 19 if ARM64_VA_BITS=36 267 default 24 if ARM64_VA_BITS=39 268 default 27 if ARM64_VA_BITS=42 269 default 30 if ARM64_VA_BITS=47 270 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 271 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 272 default 33 if ARM64_VA_BITS=48 273 default 14 if ARM64_64K_PAGES 274 default 16 if ARM64_16K_PAGES 275 default 18 276 277config ARCH_MMAP_RND_COMPAT_BITS_MIN 278 default 7 if ARM64_64K_PAGES 279 default 9 if ARM64_16K_PAGES 280 default 11 281 282config ARCH_MMAP_RND_COMPAT_BITS_MAX 283 default 16 284 285config NO_IOPORT_MAP 286 def_bool y if !PCI 287 288config STACKTRACE_SUPPORT 289 def_bool y 290 291config ILLEGAL_POINTER_VALUE 292 hex 293 default 0xdead000000000000 294 295config LOCKDEP_SUPPORT 296 def_bool y 297 298config GENERIC_BUG 299 def_bool y 300 depends on BUG 301 302config GENERIC_BUG_RELATIVE_POINTERS 303 def_bool y 304 depends on GENERIC_BUG 305 306config GENERIC_HWEIGHT 307 def_bool y 308 309config GENERIC_CSUM 310 def_bool y 311 312config GENERIC_CALIBRATE_DELAY 313 def_bool y 314 315config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 316 def_bool y 317 318config SMP 319 def_bool y 320 321config KERNEL_MODE_NEON 322 def_bool y 323 324config FIX_EARLYCON_MEM 325 def_bool y 326 327config PGTABLE_LEVELS 328 int 329 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 330 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 331 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 332 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 333 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 334 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 335 336config ARCH_SUPPORTS_UPROBES 337 def_bool y 338 339config ARCH_PROC_KCORE_TEXT 340 def_bool y 341 342config BROKEN_GAS_INST 343 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 344 345config KASAN_SHADOW_OFFSET 346 hex 347 depends on KASAN_GENERIC || KASAN_SW_TAGS 348 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS 349 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS 350 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 351 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 352 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 353 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS 354 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS 355 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 356 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 357 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 358 default 0xffffffffffffffff 359 360source "arch/arm64/Kconfig.platforms" 361 362menu "Kernel Features" 363 364menu "ARM errata workarounds via the alternatives framework" 365 366config ARM64_WORKAROUND_CLEAN_CACHE 367 bool 368 369config ARM64_ERRATUM_826319 370 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 371 default y 372 select ARM64_WORKAROUND_CLEAN_CACHE 373 help 374 This option adds an alternative code sequence to work around ARM 375 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 376 AXI master interface and an L2 cache. 377 378 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 379 and is unable to accept a certain write via this interface, it will 380 not progress on read data presented on the read data channel and the 381 system can deadlock. 382 383 The workaround promotes data cache clean instructions to 384 data cache clean-and-invalidate. 385 Please note that this does not necessarily enable the workaround, 386 as it depends on the alternative framework, which will only patch 387 the kernel if an affected CPU is detected. 388 389 If unsure, say Y. 390 391config ARM64_ERRATUM_827319 392 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 393 default y 394 select ARM64_WORKAROUND_CLEAN_CACHE 395 help 396 This option adds an alternative code sequence to work around ARM 397 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 398 master interface and an L2 cache. 399 400 Under certain conditions this erratum can cause a clean line eviction 401 to occur at the same time as another transaction to the same address 402 on the AMBA 5 CHI interface, which can cause data corruption if the 403 interconnect reorders the two transactions. 404 405 The workaround promotes data cache clean instructions to 406 data cache clean-and-invalidate. 407 Please note that this does not necessarily enable the workaround, 408 as it depends on the alternative framework, which will only patch 409 the kernel if an affected CPU is detected. 410 411 If unsure, say Y. 412 413config ARM64_ERRATUM_824069 414 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 415 default y 416 select ARM64_WORKAROUND_CLEAN_CACHE 417 help 418 This option adds an alternative code sequence to work around ARM 419 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 420 to a coherent interconnect. 421 422 If a Cortex-A53 processor is executing a store or prefetch for 423 write instruction at the same time as a processor in another 424 cluster is executing a cache maintenance operation to the same 425 address, then this erratum might cause a clean cache line to be 426 incorrectly marked as dirty. 427 428 The workaround promotes data cache clean instructions to 429 data cache clean-and-invalidate. 430 Please note that this option does not necessarily enable the 431 workaround, as it depends on the alternative framework, which will 432 only patch the kernel if an affected CPU is detected. 433 434 If unsure, say Y. 435 436config ARM64_ERRATUM_819472 437 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 438 default y 439 select ARM64_WORKAROUND_CLEAN_CACHE 440 help 441 This option adds an alternative code sequence to work around ARM 442 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 443 present when it is connected to a coherent interconnect. 444 445 If the processor is executing a load and store exclusive sequence at 446 the same time as a processor in another cluster is executing a cache 447 maintenance operation to the same address, then this erratum might 448 cause data corruption. 449 450 The workaround promotes data cache clean instructions to 451 data cache clean-and-invalidate. 452 Please note that this does not necessarily enable the workaround, 453 as it depends on the alternative framework, which will only patch 454 the kernel if an affected CPU is detected. 455 456 If unsure, say Y. 457 458config ARM64_ERRATUM_832075 459 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 460 default y 461 help 462 This option adds an alternative code sequence to work around ARM 463 erratum 832075 on Cortex-A57 parts up to r1p2. 464 465 Affected Cortex-A57 parts might deadlock when exclusive load/store 466 instructions to Write-Back memory are mixed with Device loads. 467 468 The workaround is to promote device loads to use Load-Acquire 469 semantics. 470 Please note that this does not necessarily enable the workaround, 471 as it depends on the alternative framework, which will only patch 472 the kernel if an affected CPU is detected. 473 474 If unsure, say Y. 475 476config ARM64_ERRATUM_834220 477 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 478 depends on KVM 479 default y 480 help 481 This option adds an alternative code sequence to work around ARM 482 erratum 834220 on Cortex-A57 parts up to r1p2. 483 484 Affected Cortex-A57 parts might report a Stage 2 translation 485 fault as the result of a Stage 1 fault for load crossing a 486 page boundary when there is a permission or device memory 487 alignment fault at Stage 1 and a translation fault at Stage 2. 488 489 The workaround is to verify that the Stage 1 translation 490 doesn't generate a fault before handling the Stage 2 fault. 491 Please note that this does not necessarily enable the workaround, 492 as it depends on the alternative framework, which will only patch 493 the kernel if an affected CPU is detected. 494 495 If unsure, say Y. 496 497config ARM64_ERRATUM_845719 498 bool "Cortex-A53: 845719: a load might read incorrect data" 499 depends on COMPAT 500 default y 501 help 502 This option adds an alternative code sequence to work around ARM 503 erratum 845719 on Cortex-A53 parts up to r0p4. 504 505 When running a compat (AArch32) userspace on an affected Cortex-A53 506 part, a load at EL0 from a virtual address that matches the bottom 32 507 bits of the virtual address used by a recent load at (AArch64) EL1 508 might return incorrect data. 509 510 The workaround is to write the contextidr_el1 register on exception 511 return to a 32-bit task. 512 Please note that this does not necessarily enable the workaround, 513 as it depends on the alternative framework, which will only patch 514 the kernel if an affected CPU is detected. 515 516 If unsure, say Y. 517 518config ARM64_ERRATUM_843419 519 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 520 default y 521 select ARM64_MODULE_PLTS if MODULES 522 help 523 This option links the kernel with '--fix-cortex-a53-843419' and 524 enables PLT support to replace certain ADRP instructions, which can 525 cause subsequent memory accesses to use an incorrect address on 526 Cortex-A53 parts up to r0p4. 527 528 If unsure, say Y. 529 530config ARM64_LD_HAS_FIX_ERRATUM_843419 531 def_bool $(ld-option,--fix-cortex-a53-843419) 532 533config ARM64_ERRATUM_1024718 534 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 535 default y 536 help 537 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 538 539 Affected Cortex-A55 cores (all revisions) could cause incorrect 540 update of the hardware dirty bit when the DBM/AP bits are updated 541 without a break-before-make. The workaround is to disable the usage 542 of hardware DBM locally on the affected cores. CPUs not affected by 543 this erratum will continue to use the feature. 544 545 If unsure, say Y. 546 547config ARM64_ERRATUM_1418040 548 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 549 default y 550 depends on COMPAT 551 help 552 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 553 errata 1188873 and 1418040. 554 555 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 556 cause register corruption when accessing the timer registers 557 from AArch32 userspace. 558 559 If unsure, say Y. 560 561config ARM64_WORKAROUND_SPECULATIVE_AT 562 bool 563 564config ARM64_ERRATUM_1165522 565 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 566 default y 567 select ARM64_WORKAROUND_SPECULATIVE_AT 568 help 569 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 570 571 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 572 corrupted TLBs by speculating an AT instruction during a guest 573 context switch. 574 575 If unsure, say Y. 576 577config ARM64_ERRATUM_1319367 578 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 579 default y 580 select ARM64_WORKAROUND_SPECULATIVE_AT 581 help 582 This option adds work arounds for ARM Cortex-A57 erratum 1319537 583 and A72 erratum 1319367 584 585 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 586 speculating an AT instruction during a guest context switch. 587 588 If unsure, say Y. 589 590config ARM64_ERRATUM_1530923 591 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 592 default y 593 select ARM64_WORKAROUND_SPECULATIVE_AT 594 help 595 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 596 597 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 598 corrupted TLBs by speculating an AT instruction during a guest 599 context switch. 600 601 If unsure, say Y. 602 603config ARM64_WORKAROUND_REPEAT_TLBI 604 bool 605 606config ARM64_ERRATUM_2441007 607 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" 608 default y 609 select ARM64_WORKAROUND_REPEAT_TLBI 610 help 611 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 612 613 Under very rare circumstances, affected Cortex-A55 CPUs 614 may not handle a race between a break-before-make sequence on one 615 CPU, and another CPU accessing the same page. This could allow a 616 store to a page that has been unmapped. 617 618 Work around this by adding the affected CPUs to the list that needs 619 TLB sequences to be done twice. 620 621 If unsure, say Y. 622 623config ARM64_ERRATUM_1286807 624 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 625 default y 626 select ARM64_WORKAROUND_REPEAT_TLBI 627 help 628 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 629 630 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 631 address for a cacheable mapping of a location is being 632 accessed by a core while another core is remapping the virtual 633 address to a new physical page using the recommended 634 break-before-make sequence, then under very rare circumstances 635 TLBI+DSB completes before a read using the translation being 636 invalidated has been observed by other observers. The 637 workaround repeats the TLBI+DSB operation. 638 639config ARM64_ERRATUM_1463225 640 bool "Cortex-A76: Software Step might prevent interrupt recognition" 641 default y 642 help 643 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 644 645 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 646 of a system call instruction (SVC) can prevent recognition of 647 subsequent interrupts when software stepping is disabled in the 648 exception handler of the system call and either kernel debugging 649 is enabled or VHE is in use. 650 651 Work around the erratum by triggering a dummy step exception 652 when handling a system call from a task that is being stepped 653 in a VHE configuration of the kernel. 654 655 If unsure, say Y. 656 657config ARM64_ERRATUM_1542419 658 bool "Neoverse-N1: workaround mis-ordering of instruction fetches" 659 default y 660 depends on BROKEN # CPU cap re-allocated by Android 661 help 662 This option adds a workaround for ARM Neoverse-N1 erratum 663 1542419. 664 665 Affected Neoverse-N1 cores could execute a stale instruction when 666 modified by another CPU. The workaround depends on a firmware 667 counterpart. 668 669 Workaround the issue by hiding the DIC feature from EL0. This 670 forces user-space to perform cache maintenance. 671 672 If unsure, say Y. 673 674config ARM64_ERRATUM_1508412 675 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 676 default y 677 help 678 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 679 680 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 681 of a store-exclusive or read of PAR_EL1 and a load with device or 682 non-cacheable memory attributes. The workaround depends on a firmware 683 counterpart. 684 685 KVM guests must also have the workaround implemented or they can 686 deadlock the system. 687 688 Work around the issue by inserting DMB SY barriers around PAR_EL1 689 register reads and warning KVM users. The DMB barrier is sufficient 690 to prevent a speculative PAR_EL1 read. 691 692 If unsure, say Y. 693 694config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 695 bool 696 697config ARM64_ERRATUM_2119858 698 bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode" 699 default y 700 depends on CORESIGHT_TRBE 701 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 702 help 703 This option adds the workaround for ARM Cortex-A710 erratum 2119858. 704 705 Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace 706 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 707 the event of a WRAP event. 708 709 Work around the issue by always making sure we move the TRBPTR_EL1 by 710 256 bytes before enabling the buffer and filling the first 256 bytes of 711 the buffer with ETM ignore packets upon disabling. 712 713 If unsure, say Y. 714 715config ARM64_ERRATUM_2139208 716 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 717 default y 718 depends on CORESIGHT_TRBE 719 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 720 help 721 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 722 723 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 724 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 725 the event of a WRAP event. 726 727 Work around the issue by always making sure we move the TRBPTR_EL1 by 728 256 bytes before enabling the buffer and filling the first 256 bytes of 729 the buffer with ETM ignore packets upon disabling. 730 731 If unsure, say Y. 732 733config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 734 bool 735 736config ARM64_ERRATUM_2054223 737 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 738 default y 739 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 740 help 741 Enable workaround for ARM Cortex-A710 erratum 2054223 742 743 Affected cores may fail to flush the trace data on a TSB instruction, when 744 the PE is in trace prohibited state. This will cause losing a few bytes 745 of the trace cached. 746 747 Workaround is to issue two TSB consecutively on affected cores. 748 749 If unsure, say Y. 750 751config ARM64_ERRATUM_2067961 752 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 753 default y 754 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 755 help 756 Enable workaround for ARM Neoverse-N2 erratum 2067961 757 758 Affected cores may fail to flush the trace data on a TSB instruction, when 759 the PE is in trace prohibited state. This will cause losing a few bytes 760 of the trace cached. 761 762 Workaround is to issue two TSB consecutively on affected cores. 763 764 If unsure, say Y. 765 766config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 767 bool 768 769config ARM64_ERRATUM_2253138 770 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 771 depends on CORESIGHT_TRBE 772 default y 773 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 774 help 775 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 776 777 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 778 for TRBE. Under some conditions, the TRBE might generate a write to the next 779 virtually addressed page following the last page of the TRBE address space 780 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 781 782 Work around this in the driver by always making sure that there is a 783 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 784 785 If unsure, say Y. 786 787config ARM64_ERRATUM_2224489 788 bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range" 789 depends on CORESIGHT_TRBE 790 default y 791 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 792 help 793 This option adds the workaround for ARM Cortex-A710 erratum 2224489. 794 795 Affected Cortex-A710 cores might write to an out-of-range address, not reserved 796 for TRBE. Under some conditions, the TRBE might generate a write to the next 797 virtually addressed page following the last page of the TRBE address space 798 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 799 800 Work around this in the driver by always making sure that there is a 801 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 802 803 If unsure, say Y. 804 805config ARM64_ERRATUM_2441009 806 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" 807 default y 808 select ARM64_WORKAROUND_REPEAT_TLBI 809 help 810 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 811 812 Under very rare circumstances, affected Cortex-A510 CPUs 813 may not handle a race between a break-before-make sequence on one 814 CPU, and another CPU accessing the same page. This could allow a 815 store to a page that has been unmapped. 816 817 Work around this by adding the affected CPUs to the list that needs 818 TLB sequences to be done twice. 819 820 If unsure, say Y. 821 822config ARM64_ERRATUM_2457168 823 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 824 depends on ARM64_AMU_EXTN 825 default y 826 help 827 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 828 829 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 830 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 831 incorrectly giving a significantly higher output value. 832 833 Work around this problem by returning 0 when reading the affected counter in 834 key locations that results in disabling all users of this counter. This effect 835 is the same to firmware disabling affected counters. 836 837 If unsure, say Y. 838 839config CAVIUM_ERRATUM_22375 840 bool "Cavium erratum 22375, 24313" 841 default y 842 help 843 Enable workaround for errata 22375 and 24313. 844 845 This implements two gicv3-its errata workarounds for ThunderX. Both 846 with a small impact affecting only ITS table allocation. 847 848 erratum 22375: only alloc 8MB table size 849 erratum 24313: ignore memory access type 850 851 The fixes are in ITS initialization and basically ignore memory access 852 type and table size provided by the TYPER and BASER registers. 853 854 If unsure, say Y. 855 856config CAVIUM_ERRATUM_23144 857 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 858 depends on NUMA 859 default y 860 help 861 ITS SYNC command hang for cross node io and collections/cpu mapping. 862 863 If unsure, say Y. 864 865config CAVIUM_ERRATUM_23154 866 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" 867 default y 868 help 869 The gicv3 of ThunderX requires a modified version for 870 reading the IAR status to ensure data synchronization 871 (access to icc_iar1_el1 is not sync'ed before and after). 872 873 If unsure, say Y. 874 875config CAVIUM_ERRATUM_27456 876 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 877 default y 878 depends on BROKEN # CPU cap re-allocated by Android 879 help 880 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 881 instructions may cause the icache to become corrupted if it 882 contains data for a non-current ASID. The fix is to 883 invalidate the icache when changing the mm context. 884 885 If unsure, say Y. 886 887config CAVIUM_ERRATUM_30115 888 bool "Cavium erratum 30115: Guest may disable interrupts in host" 889 default y 890 depends on BROKEN # CPU cap re-allocated by Android 891 help 892 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 893 1.2, and T83 Pass 1.0, KVM guest execution may disable 894 interrupts in host. Trapping both GICv3 group-0 and group-1 895 accesses sidesteps the issue. 896 897 If unsure, say Y. 898 899config CAVIUM_TX2_ERRATUM_219 900 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 901 default y 902 depends on BROKEN # CPU caps re-allocated by Android 903 help 904 On Cavium ThunderX2, a load, store or prefetch instruction between a 905 TTBR update and the corresponding context synchronizing operation can 906 cause a spurious Data Abort to be delivered to any hardware thread in 907 the CPU core. 908 909 Work around the issue by avoiding the problematic code sequence and 910 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 911 trap handler performs the corresponding register access, skips the 912 instruction and ensures context synchronization by virtue of the 913 exception return. 914 915 If unsure, say Y. 916 917config FUJITSU_ERRATUM_010001 918 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 919 default y 920 help 921 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 922 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 923 accesses may cause undefined fault (Data abort, DFSC=0b111111). 924 This fault occurs under a specific hardware condition when a 925 load/store instruction performs an address translation using: 926 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 927 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 928 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 929 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 930 931 The workaround is to ensure these bits are clear in TCR_ELx. 932 The workaround only affects the Fujitsu-A64FX. 933 934 If unsure, say Y. 935 936config HISILICON_ERRATUM_161600802 937 bool "Hip07 161600802: Erroneous redistributor VLPI base" 938 default y 939 help 940 The HiSilicon Hip07 SoC uses the wrong redistributor base 941 when issued ITS commands such as VMOVP and VMAPP, and requires 942 a 128kB offset to be applied to the target address in this commands. 943 944 If unsure, say Y. 945 946config QCOM_FALKOR_ERRATUM_1003 947 bool "Falkor E1003: Incorrect translation due to ASID change" 948 default y 949 help 950 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 951 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 952 in TTBR1_EL1, this situation only occurs in the entry trampoline and 953 then only for entries in the walk cache, since the leaf translation 954 is unchanged. Work around the erratum by invalidating the walk cache 955 entries for the trampoline before entering the kernel proper. 956 957config QCOM_FALKOR_ERRATUM_1009 958 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 959 default y 960 select ARM64_WORKAROUND_REPEAT_TLBI 961 help 962 On Falkor v1, the CPU may prematurely complete a DSB following a 963 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 964 one more time to fix the issue. 965 966 If unsure, say Y. 967 968config QCOM_QDF2400_ERRATUM_0065 969 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 970 default y 971 help 972 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 973 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 974 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 975 976 If unsure, say Y. 977 978config QCOM_FALKOR_ERRATUM_E1041 979 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 980 default y 981 help 982 Falkor CPU may speculatively fetch instructions from an improper 983 memory location when MMU translation is changed from SCTLR_ELn[M]=1 984 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 985 986 If unsure, say Y. 987 988config NVIDIA_CARMEL_CNP_ERRATUM 989 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 990 default y 991 help 992 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 993 invalidate shared TLB entries installed by a different core, as it would 994 on standard ARM cores. 995 996 If unsure, say Y. 997 998config SOCIONEXT_SYNQUACER_PREITS 999 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1000 default y 1001 help 1002 Socionext Synquacer SoCs implement a separate h/w block to generate 1003 MSI doorbell writes with non-zero values for the device ID. 1004 1005 If unsure, say Y. 1006 1007endmenu 1008 1009 1010choice 1011 prompt "Page size" 1012 default ARM64_4K_PAGES 1013 help 1014 Page size (translation granule) configuration. 1015 1016config ARM64_4K_PAGES 1017 bool "4KB" 1018 help 1019 This feature enables 4KB pages support. 1020 1021config ARM64_16K_PAGES 1022 bool "16KB" 1023 help 1024 The system will use 16KB pages support. AArch32 emulation 1025 requires applications compiled with 16K (or a multiple of 16K) 1026 aligned segments. 1027 1028config ARM64_64K_PAGES 1029 bool "64KB" 1030 help 1031 This feature enables 64KB pages support (4KB by default) 1032 allowing only two levels of page tables and faster TLB 1033 look-up. AArch32 emulation requires applications compiled 1034 with 64K aligned segments. 1035 1036endchoice 1037 1038choice 1039 prompt "Virtual address space size" 1040 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 1041 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 1042 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 1043 help 1044 Allows choosing one of multiple possible virtual address 1045 space sizes. The level of translation table is determined by 1046 a combination of page size and virtual address space size. 1047 1048config ARM64_VA_BITS_36 1049 bool "36-bit" if EXPERT 1050 depends on ARM64_16K_PAGES 1051 1052config ARM64_VA_BITS_39 1053 bool "39-bit" 1054 depends on ARM64_4K_PAGES 1055 1056config ARM64_VA_BITS_42 1057 bool "42-bit" 1058 depends on ARM64_64K_PAGES 1059 1060config ARM64_VA_BITS_47 1061 bool "47-bit" 1062 depends on ARM64_16K_PAGES 1063 1064config ARM64_VA_BITS_48 1065 bool "48-bit" 1066 1067config ARM64_VA_BITS_52 1068 bool "52-bit" 1069 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 1070 help 1071 Enable 52-bit virtual addressing for userspace when explicitly 1072 requested via a hint to mmap(). The kernel will also use 52-bit 1073 virtual addresses for its own mappings (provided HW support for 1074 this feature is available, otherwise it reverts to 48-bit). 1075 1076 NOTE: Enabling 52-bit virtual addressing in conjunction with 1077 ARMv8.3 Pointer Authentication will result in the PAC being 1078 reduced from 7 bits to 3 bits, which may have a significant 1079 impact on its susceptibility to brute-force attacks. 1080 1081 If unsure, select 48-bit virtual addressing instead. 1082 1083endchoice 1084 1085config ARM64_FORCE_52BIT 1086 bool "Force 52-bit virtual addresses for userspace" 1087 depends on ARM64_VA_BITS_52 && EXPERT 1088 help 1089 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1090 to maintain compatibility with older software by providing 48-bit VAs 1091 unless a hint is supplied to mmap. 1092 1093 This configuration option disables the 48-bit compatibility logic, and 1094 forces all userspace addresses to be 52-bit on HW that supports it. One 1095 should only enable this configuration option for stress testing userspace 1096 memory management code. If unsure say N here. 1097 1098config ARM64_VA_BITS 1099 int 1100 default 36 if ARM64_VA_BITS_36 1101 default 39 if ARM64_VA_BITS_39 1102 default 42 if ARM64_VA_BITS_42 1103 default 47 if ARM64_VA_BITS_47 1104 default 48 if ARM64_VA_BITS_48 1105 default 52 if ARM64_VA_BITS_52 1106 1107choice 1108 prompt "Physical address space size" 1109 default ARM64_PA_BITS_48 1110 help 1111 Choose the maximum physical address range that the kernel will 1112 support. 1113 1114config ARM64_PA_BITS_48 1115 bool "48-bit" 1116 1117config ARM64_PA_BITS_52 1118 bool "52-bit (ARMv8.2)" 1119 depends on ARM64_64K_PAGES 1120 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1121 help 1122 Enable support for a 52-bit physical address space, introduced as 1123 part of the ARMv8.2-LPA extension. 1124 1125 With this enabled, the kernel will also continue to work on CPUs that 1126 do not support ARMv8.2-LPA, but with some added memory overhead (and 1127 minor performance overhead). 1128 1129endchoice 1130 1131config ARM64_PA_BITS 1132 int 1133 default 48 if ARM64_PA_BITS_48 1134 default 52 if ARM64_PA_BITS_52 1135 1136choice 1137 prompt "Endianness" 1138 default CPU_LITTLE_ENDIAN 1139 help 1140 Select the endianness of data accesses performed by the CPU. Userspace 1141 applications will need to be compiled and linked for the endianness 1142 that is selected here. 1143 1144config CPU_BIG_ENDIAN 1145 bool "Build big-endian kernel" 1146 depends on !LD_IS_LLD || LLD_VERSION >= 130000 1147 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1148 depends on AS_IS_GNU || AS_VERSION >= 150000 1149 help 1150 Say Y if you plan on running a kernel with a big-endian userspace. 1151 1152config CPU_LITTLE_ENDIAN 1153 bool "Build little-endian kernel" 1154 help 1155 Say Y if you plan on running a kernel with a little-endian userspace. 1156 This is usually the case for distributions targeting arm64. 1157 1158endchoice 1159 1160config SCHED_MC 1161 bool "Multi-core scheduler support" 1162 help 1163 Multi-core scheduler support improves the CPU scheduler's decision 1164 making when dealing with multi-core CPU chips at a cost of slightly 1165 increased overhead in some places. If unsure say N here. 1166 1167config SCHED_SMT 1168 bool "SMT scheduler support" 1169 help 1170 Improves the CPU scheduler's decision making when dealing with 1171 MultiThreading at a cost of slightly increased overhead in some 1172 places. If unsure say N here. 1173 1174config NR_CPUS 1175 int "Maximum number of CPUs (2-4096)" 1176 range 2 4096 1177 default "256" 1178 1179config HOTPLUG_CPU 1180 bool "Support for hot-pluggable CPUs" 1181 select GENERIC_IRQ_MIGRATION 1182 help 1183 Say Y here to experiment with turning CPUs off and on. CPUs 1184 can be controlled through /sys/devices/system/cpu. 1185 1186# Common NUMA Features 1187config NUMA 1188 bool "NUMA Memory Allocation and Scheduler Support" 1189 select GENERIC_ARCH_NUMA 1190 select ACPI_NUMA if ACPI 1191 select OF_NUMA 1192 help 1193 Enable NUMA (Non-Uniform Memory Access) support. 1194 1195 The kernel will try to allocate memory used by a CPU on the 1196 local memory of the CPU and add some more 1197 NUMA awareness to the kernel. 1198 1199config NODES_SHIFT 1200 int "Maximum NUMA Nodes (as a power of 2)" 1201 range 1 10 1202 default "4" 1203 depends on NUMA 1204 help 1205 Specify the maximum number of NUMA Nodes available on the target 1206 system. Increases memory reserved to accommodate various tables. 1207 1208config USE_PERCPU_NUMA_NODE_ID 1209 def_bool y 1210 depends on NUMA 1211 1212config HAVE_SETUP_PER_CPU_AREA 1213 def_bool y 1214 depends on NUMA 1215 1216config NEED_PER_CPU_EMBED_FIRST_CHUNK 1217 def_bool y 1218 depends on NUMA 1219 1220source "kernel/Kconfig.hz" 1221 1222config ARCH_SPARSEMEM_ENABLE 1223 def_bool y 1224 select SPARSEMEM_VMEMMAP_ENABLE 1225 select SPARSEMEM_VMEMMAP 1226 1227config HW_PERF_EVENTS 1228 def_bool y 1229 depends on ARM_PMU 1230 1231# Supported by clang >= 7.0 1232config CC_HAVE_SHADOW_CALL_STACK 1233 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1234 1235config PARAVIRT 1236 bool "Enable paravirtualization code" 1237 help 1238 This changes the kernel so it can modify itself when it is run 1239 under a hypervisor, potentially improving performance significantly 1240 over full virtualization. 1241 1242config PARAVIRT_TIME_ACCOUNTING 1243 bool "Paravirtual steal time accounting" 1244 select PARAVIRT 1245 help 1246 Select this option to enable fine granularity task steal time 1247 accounting. Time spent executing other tasks in parallel with 1248 the current vCPU is discounted from the vCPU power. To account for 1249 that, there can be a small performance impact. 1250 1251 If in doubt, say N here. 1252 1253config KEXEC 1254 depends on PM_SLEEP_SMP 1255 select KEXEC_CORE 1256 bool "kexec system call" 1257 help 1258 kexec is a system call that implements the ability to shutdown your 1259 current kernel, and to start another kernel. It is like a reboot 1260 but it is independent of the system firmware. And like a reboot 1261 you can start any kernel with it, not just Linux. 1262 1263config KEXEC_FILE 1264 bool "kexec file based system call" 1265 select KEXEC_CORE 1266 select HAVE_IMA_KEXEC if IMA 1267 help 1268 This is new version of kexec system call. This system call is 1269 file based and takes file descriptors as system call argument 1270 for kernel and initramfs as opposed to list of segments as 1271 accepted by previous system call. 1272 1273config KEXEC_SIG 1274 bool "Verify kernel signature during kexec_file_load() syscall" 1275 depends on KEXEC_FILE 1276 help 1277 Select this option to verify a signature with loaded kernel 1278 image. If configured, any attempt of loading a image without 1279 valid signature will fail. 1280 1281 In addition to that option, you need to enable signature 1282 verification for the corresponding kernel image type being 1283 loaded in order for this to work. 1284 1285config KEXEC_IMAGE_VERIFY_SIG 1286 bool "Enable Image signature verification support" 1287 default y 1288 depends on KEXEC_SIG 1289 depends on EFI && SIGNED_PE_FILE_VERIFICATION 1290 help 1291 Enable Image signature verification support. 1292 1293comment "Support for PE file signature verification disabled" 1294 depends on KEXEC_SIG 1295 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION 1296 1297config CRASH_DUMP 1298 bool "Build kdump crash kernel" 1299 help 1300 Generate crash dump after being started by kexec. This should 1301 be normally only set in special crash dump kernels which are 1302 loaded in the main kernel with kexec-tools into a specially 1303 reserved region and then later executed after a crash by 1304 kdump/kexec. 1305 1306 For more details see Documentation/admin-guide/kdump/kdump.rst 1307 1308config TRANS_TABLE 1309 def_bool y 1310 depends on HIBERNATION 1311 1312config XEN_DOM0 1313 def_bool y 1314 depends on XEN 1315 1316config XEN 1317 bool "Xen guest support on ARM64" 1318 depends on ARM64 && OF 1319 select SWIOTLB_XEN 1320 select PARAVIRT 1321 help 1322 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1323 1324config FORCE_MAX_ZONEORDER 1325 int 1326 default "14" if ARM64_64K_PAGES 1327 default "12" if ARM64_16K_PAGES 1328 default "11" 1329 help 1330 The kernel memory allocator divides physically contiguous memory 1331 blocks into "zones", where each zone is a power of two number of 1332 pages. This option selects the largest power of two that the kernel 1333 keeps in the memory allocator. If you need to allocate very large 1334 blocks of physically contiguous memory, then you may need to 1335 increase this value. 1336 1337 This config option is actually maximum order plus one. For example, 1338 a value of 11 means that the largest free memory block is 2^10 pages. 1339 1340 We make sure that we can allocate upto a HugePage size for each configuration. 1341 Hence we have : 1342 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 1343 1344 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 1345 4M allocations matching the default size used by generic code. 1346 1347config UNMAP_KERNEL_AT_EL0 1348 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1349 default y 1350 help 1351 Speculation attacks against some high-performance processors can 1352 be used to bypass MMU permission checks and leak kernel data to 1353 userspace. This can be defended against by unmapping the kernel 1354 when running in userspace, mapping it back in on exception entry 1355 via a trampoline page in the vector table. 1356 1357 If unsure, say Y. 1358 1359config MITIGATE_SPECTRE_BRANCH_HISTORY 1360 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1361 default y 1362 help 1363 Speculation attacks against some high-performance processors can 1364 make use of branch history to influence future speculation. 1365 When taking an exception from user-space, a sequence of branches 1366 or a firmware call overwrites the branch history. 1367 1368config RODATA_FULL_DEFAULT_ENABLED 1369 bool "Apply r/o permissions of VM areas also to their linear aliases" 1370 default y 1371 help 1372 Apply read-only attributes of VM areas to the linear alias of 1373 the backing pages as well. This prevents code or read-only data 1374 from being modified (inadvertently or intentionally) via another 1375 mapping of the same memory page. This additional enhancement can 1376 be turned off at runtime by passing rodata=[off|on] (and turned on 1377 with rodata=full if this option is set to 'n') 1378 1379 This requires the linear region to be mapped down to pages, 1380 which may adversely affect performance in some cases. 1381 1382config ARM64_SW_TTBR0_PAN 1383 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1384 help 1385 Enabling this option prevents the kernel from accessing 1386 user-space memory directly by pointing TTBR0_EL1 to a reserved 1387 zeroed area and reserved ASID. The user access routines 1388 restore the valid TTBR0_EL1 temporarily. 1389 1390config ARM64_TAGGED_ADDR_ABI 1391 bool "Enable the tagged user addresses syscall ABI" 1392 default y 1393 help 1394 When this option is enabled, user applications can opt in to a 1395 relaxed ABI via prctl() allowing tagged addresses to be passed 1396 to system calls as pointer arguments. For details, see 1397 Documentation/arm64/tagged-address-abi.rst. 1398 1399menuconfig COMPAT 1400 bool "Kernel support for 32-bit EL0" 1401 depends on ARM64_4K_PAGES || EXPERT 1402 select HAVE_UID16 1403 select OLD_SIGSUSPEND3 1404 select COMPAT_OLD_SIGACTION 1405 help 1406 This option enables support for a 32-bit EL0 running under a 64-bit 1407 kernel at EL1. AArch32-specific components such as system calls, 1408 the user helper functions, VFP support and the ptrace interface are 1409 handled appropriately by the kernel. 1410 1411 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1412 that you will only be able to execute AArch32 binaries that were compiled 1413 with page size aligned segments. 1414 1415 If you want to execute 32-bit userspace applications, say Y. 1416 1417if COMPAT 1418 1419config KUSER_HELPERS 1420 bool "Enable kuser helpers page for 32-bit applications" 1421 default y 1422 help 1423 Warning: disabling this option may break 32-bit user programs. 1424 1425 Provide kuser helpers to compat tasks. The kernel provides 1426 helper code to userspace in read only form at a fixed location 1427 to allow userspace to be independent of the CPU type fitted to 1428 the system. This permits binaries to be run on ARMv4 through 1429 to ARMv8 without modification. 1430 1431 See Documentation/arm/kernel_user_helpers.rst for details. 1432 1433 However, the fixed address nature of these helpers can be used 1434 by ROP (return orientated programming) authors when creating 1435 exploits. 1436 1437 If all of the binaries and libraries which run on your platform 1438 are built specifically for your platform, and make no use of 1439 these helpers, then you can turn this option off to hinder 1440 such exploits. However, in that case, if a binary or library 1441 relying on those helpers is run, it will not function correctly. 1442 1443 Say N here only if you are absolutely certain that you do not 1444 need these helpers; otherwise, the safe option is to say Y. 1445 1446config COMPAT_VDSO 1447 bool "Enable vDSO for 32-bit applications" 1448 depends on !CPU_BIG_ENDIAN 1449 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1450 select GENERIC_COMPAT_VDSO 1451 default y 1452 help 1453 Place in the process address space of 32-bit applications an 1454 ELF shared object providing fast implementations of gettimeofday 1455 and clock_gettime. 1456 1457 You must have a 32-bit build of glibc 2.22 or later for programs 1458 to seamlessly take advantage of this. 1459 1460config THUMB2_COMPAT_VDSO 1461 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1462 depends on COMPAT_VDSO 1463 default y 1464 help 1465 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1466 otherwise with '-marm'. 1467 1468menuconfig ARMV8_DEPRECATED 1469 bool "Emulate deprecated/obsolete ARMv8 instructions" 1470 depends on SYSCTL 1471 help 1472 Legacy software support may require certain instructions 1473 that have been deprecated or obsoleted in the architecture. 1474 1475 Enable this config to enable selective emulation of these 1476 features. 1477 1478 If unsure, say Y 1479 1480if ARMV8_DEPRECATED 1481 1482config SWP_EMULATION 1483 bool "Emulate SWP/SWPB instructions" 1484 help 1485 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1486 they are always undefined. Say Y here to enable software 1487 emulation of these instructions for userspace using LDXR/STXR. 1488 This feature can be controlled at runtime with the abi.swp 1489 sysctl which is disabled by default. 1490 1491 In some older versions of glibc [<=2.8] SWP is used during futex 1492 trylock() operations with the assumption that the code will not 1493 be preempted. This invalid assumption may be more likely to fail 1494 with SWP emulation enabled, leading to deadlock of the user 1495 application. 1496 1497 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1498 on an external transaction monitoring block called a global 1499 monitor to maintain update atomicity. If your system does not 1500 implement a global monitor, this option can cause programs that 1501 perform SWP operations to uncached memory to deadlock. 1502 1503 If unsure, say Y 1504 1505config CP15_BARRIER_EMULATION 1506 bool "Emulate CP15 Barrier instructions" 1507 help 1508 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1509 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1510 strongly recommended to use the ISB, DSB, and DMB 1511 instructions instead. 1512 1513 Say Y here to enable software emulation of these 1514 instructions for AArch32 userspace code. When this option is 1515 enabled, CP15 barrier usage is traced which can help 1516 identify software that needs updating. This feature can be 1517 controlled at runtime with the abi.cp15_barrier sysctl. 1518 1519 If unsure, say Y 1520 1521config SETEND_EMULATION 1522 bool "Emulate SETEND instruction" 1523 help 1524 The SETEND instruction alters the data-endianness of the 1525 AArch32 EL0, and is deprecated in ARMv8. 1526 1527 Say Y here to enable software emulation of the instruction 1528 for AArch32 userspace code. This feature can be controlled 1529 at runtime with the abi.setend sysctl. 1530 1531 Note: All the cpus on the system must have mixed endian support at EL0 1532 for this feature to be enabled. If a new CPU - which doesn't support mixed 1533 endian - is hotplugged in after this feature has been enabled, there could 1534 be unexpected results in the applications. 1535 1536 If unsure, say Y 1537endif 1538 1539endif 1540 1541menu "ARMv8.1 architectural features" 1542 1543config ARM64_HW_AFDBM 1544 bool "Support for hardware updates of the Access and Dirty page flags" 1545 default y 1546 help 1547 The ARMv8.1 architecture extensions introduce support for 1548 hardware updates of the access and dirty information in page 1549 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1550 capable processors, accesses to pages with PTE_AF cleared will 1551 set this bit instead of raising an access flag fault. 1552 Similarly, writes to read-only pages with the DBM bit set will 1553 clear the read-only bit (AP[2]) instead of raising a 1554 permission fault. 1555 1556 Kernels built with this configuration option enabled continue 1557 to work on pre-ARMv8.1 hardware and the performance impact is 1558 minimal. If unsure, say Y. 1559 1560config ARM64_PAN 1561 bool "Enable support for Privileged Access Never (PAN)" 1562 default y 1563 help 1564 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1565 prevents the kernel or hypervisor from accessing user-space (EL0) 1566 memory directly. 1567 1568 Choosing this option will cause any unprotected (not using 1569 copy_to_user et al) memory access to fail with a permission fault. 1570 1571 The feature is detected at runtime, and will remain as a 'nop' 1572 instruction if the cpu does not implement the feature. 1573 1574config AS_HAS_LDAPR 1575 def_bool $(as-instr,.arch_extension rcpc) 1576 1577config AS_HAS_LSE_ATOMICS 1578 def_bool $(as-instr,.arch_extension lse) 1579 1580config ARM64_LSE_ATOMICS 1581 bool 1582 default ARM64_USE_LSE_ATOMICS 1583 depends on AS_HAS_LSE_ATOMICS 1584 1585config ARM64_USE_LSE_ATOMICS 1586 bool "Atomic instructions" 1587 depends on JUMP_LABEL 1588 default y 1589 help 1590 As part of the Large System Extensions, ARMv8.1 introduces new 1591 atomic instructions that are designed specifically to scale in 1592 very large systems. 1593 1594 Say Y here to make use of these instructions for the in-kernel 1595 atomic routines. This incurs a small overhead on CPUs that do 1596 not support these instructions and requires the kernel to be 1597 built with binutils >= 2.25 in order for the new instructions 1598 to be used. 1599 1600endmenu 1601 1602menu "ARMv8.2 architectural features" 1603 1604config ARM64_PMEM 1605 bool "Enable support for persistent memory" 1606 select ARCH_HAS_PMEM_API 1607 select ARCH_HAS_UACCESS_FLUSHCACHE 1608 help 1609 Say Y to enable support for the persistent memory API based on the 1610 ARMv8.2 DCPoP feature. 1611 1612 The feature is detected at runtime, and the kernel will use DC CVAC 1613 operations if DC CVAP is not supported (following the behaviour of 1614 DC CVAP itself if the system does not define a point of persistence). 1615 1616config ARM64_RAS_EXTN 1617 bool "Enable support for RAS CPU Extensions" 1618 default y 1619 help 1620 CPUs that support the Reliability, Availability and Serviceability 1621 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1622 errors, classify them and report them to software. 1623 1624 On CPUs with these extensions system software can use additional 1625 barriers to determine if faults are pending and read the 1626 classification from a new set of registers. 1627 1628 Selecting this feature will allow the kernel to use these barriers 1629 and access the new registers if the system supports the extension. 1630 Platform RAS features may additionally depend on firmware support. 1631 1632config ARM64_CNP 1633 bool "Enable support for Common Not Private (CNP) translations" 1634 default y 1635 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1636 help 1637 Common Not Private (CNP) allows translation table entries to 1638 be shared between different PEs in the same inner shareable 1639 domain, so the hardware can use this fact to optimise the 1640 caching of such entries in the TLB. 1641 1642 Selecting this option allows the CNP feature to be detected 1643 at runtime, and does not affect PEs that do not implement 1644 this feature. 1645 1646endmenu 1647 1648menu "ARMv8.3 architectural features" 1649 1650config ARM64_PTR_AUTH 1651 bool "Enable support for pointer authentication" 1652 default y 1653 help 1654 Pointer authentication (part of the ARMv8.3 Extensions) provides 1655 instructions for signing and authenticating pointers against secret 1656 keys, which can be used to mitigate Return Oriented Programming (ROP) 1657 and other attacks. 1658 1659 This option enables these instructions at EL0 (i.e. for userspace). 1660 Choosing this option will cause the kernel to initialise secret keys 1661 for each process at exec() time, with these keys being 1662 context-switched along with the process. 1663 1664 The feature is detected at runtime. If the feature is not present in 1665 hardware it will not be advertised to userspace/KVM guest nor will it 1666 be enabled. 1667 1668 If the feature is present on the boot CPU but not on a late CPU, then 1669 the late CPU will be parked. Also, if the boot CPU does not have 1670 address auth and the late CPU has then the late CPU will still boot 1671 but with the feature disabled. On such a system, this option should 1672 not be selected. 1673 1674config ARM64_PTR_AUTH_KERNEL 1675 bool "Use pointer authentication for kernel" 1676 default y 1677 depends on ARM64_PTR_AUTH 1678 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC 1679 # Modern compilers insert a .note.gnu.property section note for PAC 1680 # which is only understood by binutils starting with version 2.33.1. 1681 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1682 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1683 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1684 help 1685 If the compiler supports the -mbranch-protection or 1686 -msign-return-address flag (e.g. GCC 7 or later), then this option 1687 will cause the kernel itself to be compiled with return address 1688 protection. In this case, and if the target hardware is known to 1689 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1690 disabled with minimal loss of protection. 1691 1692 This feature works with FUNCTION_GRAPH_TRACER option only if 1693 DYNAMIC_FTRACE_WITH_REGS is enabled. 1694 1695config CC_HAS_BRANCH_PROT_PAC_RET 1696 # GCC 9 or later, clang 8 or later 1697 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1698 1699config CC_HAS_SIGN_RETURN_ADDRESS 1700 # GCC 7, 8 1701 def_bool $(cc-option,-msign-return-address=all) 1702 1703config AS_HAS_PAC 1704 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1705 1706config AS_HAS_CFI_NEGATE_RA_STATE 1707 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1708 1709endmenu 1710 1711menu "ARMv8.4 architectural features" 1712 1713config ARM64_AMU_EXTN 1714 bool "Enable support for the Activity Monitors Unit CPU extension" 1715 default y 1716 help 1717 The activity monitors extension is an optional extension introduced 1718 by the ARMv8.4 CPU architecture. This enables support for version 1 1719 of the activity monitors architecture, AMUv1. 1720 1721 To enable the use of this extension on CPUs that implement it, say Y. 1722 1723 Note that for architectural reasons, firmware _must_ implement AMU 1724 support when running on CPUs that present the activity monitors 1725 extension. The required support is present in: 1726 * Version 1.5 and later of the ARM Trusted Firmware 1727 1728 For kernels that have this configuration enabled but boot with broken 1729 firmware, you may need to say N here until the firmware is fixed. 1730 Otherwise you may experience firmware panics or lockups when 1731 accessing the counter registers. Even if you are not observing these 1732 symptoms, the values returned by the register reads might not 1733 correctly reflect reality. Most commonly, the value read will be 0, 1734 indicating that the counter is not enabled. 1735 1736config AS_HAS_ARMV8_4 1737 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 1738 1739config ARM64_TLB_RANGE 1740 bool "Enable support for tlbi range feature" 1741 default y 1742 depends on AS_HAS_ARMV8_4 1743 help 1744 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 1745 range of input addresses. 1746 1747 The feature introduces new assembly instructions, and they were 1748 support when binutils >= 2.30. 1749 1750config ARM64_MPAM 1751 bool "Enable support for MPAM" 1752 help 1753 Memory Partitioning and Monitoring is an optional extension 1754 that allows the CPUs to mark load and store transactions with 1755 labels for partition-id and performance-monitoring-group. 1756 System components, such as the caches, can use the partition-id 1757 to apply a performance policy. MPAM monitors can use the 1758 partition-id and performance-monitoring-group to measure the 1759 cache occupancy or data throughput. 1760 1761 Use of this extension requires CPU support, support in the 1762 memory system components (MSC), and a description from firmware 1763 of where the MSC are in the address space. 1764 1765endmenu 1766 1767menu "ARMv8.5 architectural features" 1768 1769config AS_HAS_ARMV8_5 1770 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 1771 1772config ARM64_BTI 1773 bool "Branch Target Identification support" 1774 default y 1775 help 1776 Branch Target Identification (part of the ARMv8.5 Extensions) 1777 provides a mechanism to limit the set of locations to which computed 1778 branch instructions such as BR or BLR can jump. 1779 1780 To make use of BTI on CPUs that support it, say Y. 1781 1782 BTI is intended to provide complementary protection to other control 1783 flow integrity protection mechanisms, such as the Pointer 1784 authentication mechanism provided as part of the ARMv8.3 Extensions. 1785 For this reason, it does not make sense to enable this option without 1786 also enabling support for pointer authentication. Thus, when 1787 enabling this option you should also select ARM64_PTR_AUTH=y. 1788 1789 Userspace binaries must also be specifically compiled to make use of 1790 this mechanism. If you say N here or the hardware does not support 1791 BTI, such binaries can still run, but you get no additional 1792 enforcement of branch destinations. 1793 1794config ARM64_BTI_KERNEL 1795 bool "Use Branch Target Identification for kernel" 1796 default y 1797 depends on ARM64_BTI 1798 depends on ARM64_PTR_AUTH_KERNEL 1799 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 1800 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 1801 depends on !CC_IS_GCC || GCC_VERSION >= 100100 1802 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 1803 depends on !CC_IS_GCC 1804 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9 1805 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 1806 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1807 help 1808 Build the kernel with Branch Target Identification annotations 1809 and enable enforcement of this for kernel code. When this option 1810 is enabled and the system supports BTI all kernel code including 1811 modular code must have BTI enabled. 1812 1813config CC_HAS_BRANCH_PROT_PAC_RET_BTI 1814 # GCC 9 or later, clang 8 or later 1815 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 1816 1817config ARM64_E0PD 1818 bool "Enable support for E0PD" 1819 default y 1820 help 1821 E0PD (part of the ARMv8.5 extensions) allows us to ensure 1822 that EL0 accesses made via TTBR1 always fault in constant time, 1823 providing similar benefits to KASLR as those provided by KPTI, but 1824 with lower overhead and without disrupting legitimate access to 1825 kernel memory such as SPE. 1826 1827 This option enables E0PD for TTBR1 where available. 1828 1829config ARCH_RANDOM 1830 bool "Enable support for random number generation" 1831 default y 1832 help 1833 Random number generation (part of the ARMv8.5 Extensions) 1834 provides a high bandwidth, cryptographically secure 1835 hardware random number generator. 1836 1837config ARM64_AS_HAS_MTE 1838 # Initial support for MTE went in binutils 2.32.0, checked with 1839 # ".arch armv8.5-a+memtag" below. However, this was incomplete 1840 # as a late addition to the final architecture spec (LDGM/STGM) 1841 # is only supported in the newer 2.32.x and 2.33 binutils 1842 # versions, hence the extra "stgm" instruction check below. 1843 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 1844 1845config ARM64_MTE 1846 bool "Memory Tagging Extension support" 1847 default y 1848 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 1849 depends on AS_HAS_ARMV8_5 1850 depends on AS_HAS_LSE_ATOMICS 1851 # Required for tag checking in the uaccess routines 1852 depends on ARM64_PAN 1853 select ARCH_USES_HIGH_VMA_FLAGS 1854 help 1855 Memory Tagging (part of the ARMv8.5 Extensions) provides 1856 architectural support for run-time, always-on detection of 1857 various classes of memory error to aid with software debugging 1858 to eliminate vulnerabilities arising from memory-unsafe 1859 languages. 1860 1861 This option enables the support for the Memory Tagging 1862 Extension at EL0 (i.e. for userspace). 1863 1864 Selecting this option allows the feature to be detected at 1865 runtime. Any secondary CPU not implementing this feature will 1866 not be allowed a late bring-up. 1867 1868 Userspace binaries that want to use this feature must 1869 explicitly opt in. The mechanism for the userspace is 1870 described in: 1871 1872 Documentation/arm64/memory-tagging-extension.rst. 1873 1874endmenu 1875 1876menu "ARMv8.7 architectural features" 1877 1878config ARM64_EPAN 1879 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 1880 default y 1881 depends on ARM64_PAN 1882 help 1883 Enhanced Privileged Access Never (EPAN) allows Privileged 1884 Access Never to be used with Execute-only mappings. 1885 1886 The feature is detected at runtime, and will remain disabled 1887 if the cpu does not implement the feature. 1888endmenu 1889 1890config ARM64_SVE 1891 bool "ARM Scalable Vector Extension support" 1892 default y 1893 help 1894 The Scalable Vector Extension (SVE) is an extension to the AArch64 1895 execution state which complements and extends the SIMD functionality 1896 of the base architecture to support much larger vectors and to enable 1897 additional vectorisation opportunities. 1898 1899 To enable use of this extension on CPUs that implement it, say Y. 1900 1901 On CPUs that support the SVE2 extensions, this option will enable 1902 those too. 1903 1904 Note that for architectural reasons, firmware _must_ implement SVE 1905 support when running on SVE capable hardware. The required support 1906 is present in: 1907 1908 * version 1.5 and later of the ARM Trusted Firmware 1909 * the AArch64 boot wrapper since commit 5e1261e08abf 1910 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 1911 1912 For other firmware implementations, consult the firmware documentation 1913 or vendor. 1914 1915 If you need the kernel to boot on SVE-capable hardware with broken 1916 firmware, you may need to say N here until you get your firmware 1917 fixed. Otherwise, you may experience firmware panics or lockups when 1918 booting the kernel. If unsure and you are not observing these 1919 symptoms, you should assume that it is safe to say Y. 1920 1921config ARM64_MODULE_PLTS 1922 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1923 depends on MODULES 1924 select HAVE_MOD_ARCH_SPECIFIC 1925 help 1926 Allocate PLTs when loading modules so that jumps and calls whose 1927 targets are too far away for their relative offsets to be encoded 1928 in the instructions themselves can be bounced via veneers in the 1929 module's PLT. This allows modules to be allocated in the generic 1930 vmalloc area after the dedicated module memory area has been 1931 exhausted. 1932 1933 When running with address space randomization (KASLR), the module 1934 region itself may be too far away for ordinary relative jumps and 1935 calls, and so in that case, module PLTs are required and cannot be 1936 disabled. 1937 1938 Specific errata workaround(s) might also force module PLTs to be 1939 enabled (ARM64_ERRATUM_843419). 1940 1941config ARM64_PSEUDO_NMI 1942 bool "Support for NMI-like interrupts" 1943 select ARM_GIC_V3 1944 help 1945 Adds support for mimicking Non-Maskable Interrupts through the use of 1946 GIC interrupt priority. This support requires version 3 or later of 1947 ARM GIC. 1948 1949 This high priority configuration for interrupts needs to be 1950 explicitly enabled by setting the kernel parameter 1951 "irqchip.gicv3_pseudo_nmi" to 1. 1952 1953 If unsure, say N 1954 1955if ARM64_PSEUDO_NMI 1956config ARM64_DEBUG_PRIORITY_MASKING 1957 bool "Debug interrupt priority masking" 1958 help 1959 This adds runtime checks to functions enabling/disabling 1960 interrupts when using priority masking. The additional checks verify 1961 the validity of ICC_PMR_EL1 when calling concerned functions. 1962 1963 If unsure, say N 1964endif 1965 1966config RELOCATABLE 1967 bool "Build a relocatable kernel image" if EXPERT 1968 select ARCH_HAS_RELR 1969 default y 1970 help 1971 This builds the kernel as a Position Independent Executable (PIE), 1972 which retains all relocation metadata required to relocate the 1973 kernel binary at runtime to a different virtual address than the 1974 address it was linked at. 1975 Since AArch64 uses the RELA relocation format, this requires a 1976 relocation pass at runtime even if the kernel is loaded at the 1977 same address it was linked at. 1978 1979config RANDOMIZE_BASE 1980 bool "Randomize the address of the kernel image" 1981 select ARM64_MODULE_PLTS if MODULES 1982 select RELOCATABLE 1983 help 1984 Randomizes the virtual address at which the kernel image is 1985 loaded, as a security feature that deters exploit attempts 1986 relying on knowledge of the location of kernel internals. 1987 1988 It is the bootloader's job to provide entropy, by passing a 1989 random u64 value in /chosen/kaslr-seed at kernel entry. 1990 1991 When booting via the UEFI stub, it will invoke the firmware's 1992 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 1993 to the kernel proper. In addition, it will randomise the physical 1994 location of the kernel Image as well. 1995 1996 If unsure, say N. 1997 1998config RANDOMIZE_MODULE_REGION_FULL 1999 bool "Randomize the module region over a 2 GB range" 2000 depends on RANDOMIZE_BASE 2001 default y 2002 help 2003 Randomizes the location of the module region inside a 2 GB window 2004 covering the core kernel. This way, it is less likely for modules 2005 to leak information about the location of core kernel data structures 2006 but it does imply that function calls between modules and the core 2007 kernel will need to be resolved via veneers in the module PLT. 2008 2009 When this option is not set, the module region will be randomized over 2010 a limited range that contains the [_stext, _etext] interval of the 2011 core kernel, so branch relocations are almost always in range unless 2012 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this 2013 particular case of region exhaustion, modules might be able to fall 2014 back to a larger 2GB area. 2015 2016config CC_HAVE_STACKPROTECTOR_SYSREG 2017 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2018 2019config STACKPROTECTOR_PER_TASK 2020 def_bool y 2021 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2022 2023endmenu 2024 2025menu "Boot options" 2026 2027config ARM64_ACPI_PARKING_PROTOCOL 2028 bool "Enable support for the ARM64 ACPI parking protocol" 2029 depends on ACPI 2030 help 2031 Enable support for the ARM64 ACPI parking protocol. If disabled 2032 the kernel will not allow booting through the ARM64 ACPI parking 2033 protocol even if the corresponding data is present in the ACPI 2034 MADT table. 2035 2036config CMDLINE 2037 string "Default kernel command string" 2038 default "" 2039 help 2040 Provide a set of default command-line options at build time by 2041 entering them here. As a minimum, you should specify the the 2042 root device (e.g. root=/dev/nfs). 2043 2044choice 2045 prompt "Kernel command line type" if CMDLINE != "" 2046 default CMDLINE_FROM_BOOTLOADER 2047 help 2048 Choose how the kernel will handle the provided default kernel 2049 command line string. 2050 2051config CMDLINE_FROM_BOOTLOADER 2052 bool "Use bootloader kernel arguments if available" 2053 help 2054 Uses the command-line options passed by the boot loader. If 2055 the boot loader doesn't provide any, the default kernel command 2056 string provided in CMDLINE will be used. 2057 2058config CMDLINE_EXTEND 2059 bool "Extend bootloader kernel arguments" 2060 help 2061 The command-line arguments provided by the boot loader will be 2062 appended to the default kernel command string. 2063 2064config CMDLINE_FORCE 2065 bool "Always use the default kernel command string" 2066 help 2067 Always use the default kernel command string, even if the boot 2068 loader passes other arguments to the kernel. 2069 This is useful if you cannot or don't want to change the 2070 command-line options your boot loader passes to the kernel. 2071 2072endchoice 2073 2074config EFI_STUB 2075 bool 2076 2077config EFI 2078 bool "UEFI runtime support" 2079 depends on OF && !CPU_BIG_ENDIAN 2080 depends on KERNEL_MODE_NEON 2081 select ARCH_SUPPORTS_ACPI 2082 select LIBFDT 2083 select UCS2_STRING 2084 select EFI_PARAMS_FROM_FDT 2085 select EFI_RUNTIME_WRAPPERS 2086 select EFI_STUB 2087 select EFI_GENERIC_STUB 2088 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2089 default y 2090 help 2091 This option provides support for runtime services provided 2092 by UEFI firmware (such as non-volatile variables, realtime 2093 clock, and platform reset). A UEFI stub is also provided to 2094 allow the kernel to be booted as an EFI application. This 2095 is only useful on systems that have UEFI firmware. 2096 2097config DMI 2098 bool "Enable support for SMBIOS (DMI) tables" 2099 depends on EFI 2100 default y 2101 help 2102 This enables SMBIOS/DMI feature for systems. 2103 2104 This option is only useful on systems that have UEFI firmware. 2105 However, even with this option, the resultant kernel should 2106 continue to boot on existing non-UEFI platforms. 2107 2108endmenu 2109 2110config SYSVIPC_COMPAT 2111 def_bool y 2112 depends on COMPAT && SYSVIPC 2113 2114menu "Power management options" 2115 2116source "kernel/power/Kconfig" 2117 2118config ARCH_HIBERNATION_POSSIBLE 2119 def_bool y 2120 depends on CPU_PM 2121 2122config ARCH_HIBERNATION_HEADER 2123 def_bool y 2124 depends on HIBERNATION 2125 2126config ARCH_SUSPEND_POSSIBLE 2127 def_bool y 2128 2129endmenu 2130 2131menu "CPU Power Management" 2132 2133source "drivers/cpuidle/Kconfig" 2134 2135source "drivers/cpufreq/Kconfig" 2136 2137endmenu 2138 2139source "drivers/acpi/Kconfig" 2140 2141source "arch/arm64/kvm/Kconfig" 2142 2143if CRYPTO 2144source "arch/arm64/crypto/Kconfig" 2145endif 2146