1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef _DPU_HW_CATALOG_H 6 #define _DPU_HW_CATALOG_H 7 8 #include <linux/kernel.h> 9 #include <linux/bug.h> 10 #include <linux/bitmap.h> 11 #include <linux/err.h> 12 13 /** 14 * Max hardware block count: For ex: max 12 SSPP pipes or 15 * 5 ctl paths. In all cases, it can have max 12 hardware blocks 16 * based on current design 17 */ 18 #define MAX_BLOCKS 12 19 20 #define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\ 21 ((MINOR & 0xFFF) << 16) |\ 22 (STEP & 0xFFFF)) 23 24 #define DPU_HW_MAJOR(rev) ((rev) >> 28) 25 #define DPU_HW_MINOR(rev) (((rev) >> 16) & 0xFFF) 26 #define DPU_HW_STEP(rev) ((rev) & 0xFFFF) 27 #define DPU_HW_MAJOR_MINOR(rev) ((rev) >> 16) 28 29 #define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2) \ 30 (DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2))) 31 32 #define DPU_HW_VER_170 DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */ 33 #define DPU_HW_VER_171 DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */ 34 #define DPU_HW_VER_172 DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */ 35 #define DPU_HW_VER_300 DPU_HW_VER(3, 0, 0) /* 8998 v1.0 */ 36 #define DPU_HW_VER_301 DPU_HW_VER(3, 0, 1) /* 8998 v1.1 */ 37 #define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */ 38 #define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */ 39 #define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */ 40 #define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sm8150 v1.0 */ 41 #define DPU_HW_VER_501 DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */ 42 #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */ 43 #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ 44 #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ 45 46 #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) 47 #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) 48 #define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400) 49 #define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410) 50 #define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500) 51 #define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620) 52 #define IS_SC7280_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_720) 53 54 #define DPU_HW_BLK_NAME_LEN 16 55 56 #define MAX_IMG_WIDTH 0x3fff 57 #define MAX_IMG_HEIGHT 0x3fff 58 59 #define CRTC_DUAL_MIXERS 2 60 61 #define MAX_XIN_COUNT 16 62 63 /** 64 * Supported UBWC feature versions 65 */ 66 enum { 67 DPU_HW_UBWC_VER_10 = 0x100, 68 DPU_HW_UBWC_VER_20 = 0x200, 69 DPU_HW_UBWC_VER_30 = 0x300, 70 DPU_HW_UBWC_VER_40 = 0x400, 71 }; 72 73 /** 74 * MDP TOP BLOCK features 75 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe 76 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats 77 * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression. 78 * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth 79 * compression initial revision 80 * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 81 * @DPU_MDP_MAX Maximum value 82 83 */ 84 enum { 85 DPU_MDP_PANIC_PER_PIPE = 0x1, 86 DPU_MDP_10BIT_SUPPORT, 87 DPU_MDP_BWC, 88 DPU_MDP_UBWC_1_0, 89 DPU_MDP_UBWC_1_5, 90 DPU_MDP_MAX 91 }; 92 93 /** 94 * SSPP sub-blocks/features 95 * @DPU_SSPP_SRC Src and fetch part of the pipes, 96 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support 97 * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support 98 * @DPU_SSPP_SCALER_QSEED3LITE, QSEED3 Lite alogorithm support 99 * @DPU_SSPP_SCALER_QSEED4, QSEED4 algorithm support 100 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes 101 * @DPU_SSPP_CSC, Support of Color space converion 102 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion 103 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer 104 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq 105 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control 106 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect 107 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support 108 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support 109 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper 110 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec 111 * @DPU_SSPP_CDP Supports client driven prefetch 112 * @DPU_SSPP_MAX maximum value 113 */ 114 enum { 115 DPU_SSPP_SRC = 0x1, 116 DPU_SSPP_SCALER_QSEED2, 117 DPU_SSPP_SCALER_QSEED3, 118 DPU_SSPP_SCALER_QSEED3LITE, 119 DPU_SSPP_SCALER_QSEED4, 120 DPU_SSPP_SCALER_RGB, 121 DPU_SSPP_CSC, 122 DPU_SSPP_CSC_10BIT, 123 DPU_SSPP_CURSOR, 124 DPU_SSPP_QOS, 125 DPU_SSPP_QOS_8LVL, 126 DPU_SSPP_EXCL_RECT, 127 DPU_SSPP_SMART_DMA_V1, 128 DPU_SSPP_SMART_DMA_V2, 129 DPU_SSPP_TS_PREFILL, 130 DPU_SSPP_TS_PREFILL_REC1, 131 DPU_SSPP_CDP, 132 DPU_SSPP_MAX 133 }; 134 135 /* 136 * MIXER sub-blocks/features 137 * @DPU_MIXER_LAYER Layer mixer layer blend configuration, 138 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration 139 * @DPU_MIXER_GC Gamma correction block 140 * @DPU_DIM_LAYER Layer mixer supports dim layer 141 * @DPU_MIXER_MAX maximum value 142 */ 143 enum { 144 DPU_MIXER_LAYER = 0x1, 145 DPU_MIXER_SOURCESPLIT, 146 DPU_MIXER_GC, 147 DPU_DIM_LAYER, 148 DPU_MIXER_MAX 149 }; 150 151 /** 152 * DSPP sub-blocks 153 * @DPU_DSPP_PCC Panel color correction block 154 * @DPU_DSPP_GC Gamma correction block 155 */ 156 enum { 157 DPU_DSPP_PCC = 0x1, 158 DPU_DSPP_GC, 159 DPU_DSPP_MAX 160 }; 161 162 /** 163 * PINGPONG sub-blocks 164 * @DPU_PINGPONG_TE Tear check block 165 * @DPU_PINGPONG_TE2 Additional tear check block for split pipes 166 * @DPU_PINGPONG_SPLIT PP block supports split fifo 167 * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo 168 * @DPU_PINGPONG_DITHER, Dither blocks 169 * @DPU_PINGPONG_MAX 170 */ 171 enum { 172 DPU_PINGPONG_TE = 0x1, 173 DPU_PINGPONG_TE2, 174 DPU_PINGPONG_SPLIT, 175 DPU_PINGPONG_SLAVE, 176 DPU_PINGPONG_DITHER, 177 DPU_PINGPONG_MAX 178 }; 179 180 /** 181 * CTL sub-blocks 182 * @DPU_CTL_SPLIT_DISPLAY CTL supports video mode split display 183 * @DPU_CTL_MAX 184 */ 185 enum { 186 DPU_CTL_SPLIT_DISPLAY = 0x1, 187 DPU_CTL_ACTIVE_CFG, 188 DPU_CTL_FETCH_ACTIVE, 189 DPU_CTL_MAX 190 }; 191 192 /** 193 * INTF sub-blocks 194 * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which 195 * pixel data arrives to this INTF 196 * @DPU_INTF_TE INTF block has TE configuration support 197 * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate 198 * than video timing 199 * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register 200 * @DPU_INTF_MAX 201 */ 202 enum { 203 DPU_INTF_INPUT_CTRL = 0x1, 204 DPU_INTF_TE, 205 DPU_DATA_HCTL_EN, 206 DPU_INTF_STATUS_SUPPORTED, 207 DPU_INTF_MAX 208 }; 209 210 /** 211 * VBIF sub-blocks and features 212 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit 213 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap 214 * @DPU_VBIF_MAX maximum value 215 */ 216 enum { 217 DPU_VBIF_QOS_OTLIM = 0x1, 218 DPU_VBIF_QOS_REMAP, 219 DPU_VBIF_MAX 220 }; 221 222 /** 223 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU 224 * @name: string name for debug purposes 225 * @id: enum identifying this block 226 * @base: register base offset to mdss 227 * @len: length of hardware block 228 * @features bit mask identifying sub-blocks/features 229 */ 230 #define DPU_HW_BLK_INFO \ 231 char name[DPU_HW_BLK_NAME_LEN]; \ 232 u32 id; \ 233 u32 base; \ 234 u32 len; \ 235 unsigned long features 236 237 /** 238 * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU 239 * @name: string name for debug purposes 240 * @id: enum identifying this sub-block 241 * @base: offset of this sub-block relative to the block 242 * offset 243 * @len register block length of this sub-block 244 */ 245 #define DPU_HW_SUBBLK_INFO \ 246 char name[DPU_HW_BLK_NAME_LEN]; \ 247 u32 id; \ 248 u32 base; \ 249 u32 len 250 251 /** 252 * struct dpu_src_blk: SSPP part of the source pipes 253 * @info: HW register and features supported by this sub-blk 254 */ 255 struct dpu_src_blk { 256 DPU_HW_SUBBLK_INFO; 257 }; 258 259 /** 260 * struct dpu_scaler_blk: Scaler information 261 * @info: HW register and features supported by this sub-blk 262 * @version: qseed block revision 263 */ 264 struct dpu_scaler_blk { 265 DPU_HW_SUBBLK_INFO; 266 u32 version; 267 }; 268 269 struct dpu_csc_blk { 270 DPU_HW_SUBBLK_INFO; 271 }; 272 273 /** 274 * struct dpu_pp_blk : Pixel processing sub-blk information 275 * @info: HW register and features supported by this sub-blk 276 * @version: HW Algorithm version 277 */ 278 struct dpu_pp_blk { 279 DPU_HW_SUBBLK_INFO; 280 u32 version; 281 }; 282 283 /** 284 * enum dpu_qos_lut_usage - define QoS LUT use cases 285 */ 286 enum dpu_qos_lut_usage { 287 DPU_QOS_LUT_USAGE_LINEAR, 288 DPU_QOS_LUT_USAGE_MACROTILE, 289 DPU_QOS_LUT_USAGE_NRT, 290 DPU_QOS_LUT_USAGE_MAX, 291 }; 292 293 /** 294 * struct dpu_qos_lut_entry - define QoS LUT table entry 295 * @fl: fill level, or zero on last entry to indicate default lut 296 * @lut: lut to use if equal to or less than fill level 297 */ 298 struct dpu_qos_lut_entry { 299 u32 fl; 300 u64 lut; 301 }; 302 303 /** 304 * struct dpu_qos_lut_tbl - define QoS LUT table 305 * @nentry: number of entry in this table 306 * @entries: Pointer to table entries 307 */ 308 struct dpu_qos_lut_tbl { 309 u32 nentry; 310 const struct dpu_qos_lut_entry *entries; 311 }; 312 313 /** 314 * struct dpu_caps - define DPU capabilities 315 * @max_mixer_width max layer mixer line width support. 316 * @max_mixer_blendstages max layer mixer blend stages or 317 * supported z order 318 * @qseed_type qseed2 or qseed3 support. 319 * @smart_dma_rev Supported version of SmartDMA feature. 320 * @ubwc_version UBWC feature version (0x0 for not supported) 321 * @has_src_split source split feature status 322 * @has_dim_layer dim layer feature status 323 * @has_idle_pc indicate if idle power collapse feature is supported 324 * @has_3d_merge indicate if 3D merge is supported 325 * @max_linewidth max linewidth for sspp 326 * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes 327 * @max_hdeci_exp max horizontal decimation supported (max is 2^value) 328 * @max_vdeci_exp max vertical decimation supported (max is 2^value) 329 */ 330 struct dpu_caps { 331 u32 max_mixer_width; 332 u32 max_mixer_blendstages; 333 u32 qseed_type; 334 u32 smart_dma_rev; 335 u32 ubwc_version; 336 bool has_src_split; 337 bool has_dim_layer; 338 bool has_idle_pc; 339 bool has_3d_merge; 340 /* SSPP limits */ 341 u32 max_linewidth; 342 u32 pixel_ram_size; 343 u32 max_hdeci_exp; 344 u32 max_vdeci_exp; 345 }; 346 347 /** 348 * struct dpu_sspp_sub_blks : SSPP sub-blocks 349 * common: Pointer to common configurations shared by sub blocks 350 * @creq_vblank: creq priority during vertical blanking 351 * @danger_vblank: danger priority during vertical blanking 352 * @maxdwnscale: max downscale ratio supported(without DECIMATION) 353 * @maxupscale: maxupscale ratio supported 354 * @smart_dma_priority: hw priority of rect1 of multirect pipe 355 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 356 * @qseed_ver: qseed version 357 * @src_blk: 358 * @scaler_blk: 359 * @csc_blk: 360 * @hsic: 361 * @memcolor: 362 * @pcc_blk: 363 * @igc_blk: 364 * @format_list: Pointer to list of supported formats 365 * @num_formats: Number of supported formats 366 * @virt_format_list: Pointer to list of supported formats for virtual planes 367 * @virt_num_formats: Number of supported formats for virtual planes 368 */ 369 struct dpu_sspp_sub_blks { 370 u32 creq_vblank; 371 u32 danger_vblank; 372 u32 maxdwnscale; 373 u32 maxupscale; 374 u32 smart_dma_priority; 375 u32 max_per_pipe_bw; 376 u32 qseed_ver; 377 struct dpu_src_blk src_blk; 378 struct dpu_scaler_blk scaler_blk; 379 struct dpu_pp_blk csc_blk; 380 struct dpu_pp_blk hsic_blk; 381 struct dpu_pp_blk memcolor_blk; 382 struct dpu_pp_blk pcc_blk; 383 struct dpu_pp_blk igc_blk; 384 385 const u32 *format_list; 386 u32 num_formats; 387 const u32 *virt_format_list; 388 u32 virt_num_formats; 389 }; 390 391 /** 392 * struct dpu_lm_sub_blks: information of mixer block 393 * @maxwidth: Max pixel width supported by this mixer 394 * @maxblendstages: Max number of blend-stages supported 395 * @blendstage_base: Blend-stage register base offset 396 * @gc: gamma correction block 397 */ 398 struct dpu_lm_sub_blks { 399 u32 maxwidth; 400 u32 maxblendstages; 401 u32 blendstage_base[MAX_BLOCKS]; 402 struct dpu_pp_blk gc; 403 }; 404 405 /** 406 * struct dpu_dspp_sub_blks: Information of DSPP block 407 * @gc : gamma correction block 408 * @pcc: pixel color correction block 409 */ 410 struct dpu_dspp_sub_blks { 411 struct dpu_pp_blk gc; 412 struct dpu_pp_blk pcc; 413 }; 414 415 struct dpu_pingpong_sub_blks { 416 struct dpu_pp_blk te; 417 struct dpu_pp_blk te2; 418 struct dpu_pp_blk dither; 419 }; 420 421 /** 422 * dpu_clk_ctrl_type - Defines top level clock control signals 423 */ 424 enum dpu_clk_ctrl_type { 425 DPU_CLK_CTRL_NONE, 426 DPU_CLK_CTRL_VIG0, 427 DPU_CLK_CTRL_VIG1, 428 DPU_CLK_CTRL_VIG2, 429 DPU_CLK_CTRL_VIG3, 430 DPU_CLK_CTRL_VIG4, 431 DPU_CLK_CTRL_RGB0, 432 DPU_CLK_CTRL_RGB1, 433 DPU_CLK_CTRL_RGB2, 434 DPU_CLK_CTRL_RGB3, 435 DPU_CLK_CTRL_DMA0, 436 DPU_CLK_CTRL_DMA1, 437 DPU_CLK_CTRL_CURSOR0, 438 DPU_CLK_CTRL_CURSOR1, 439 DPU_CLK_CTRL_INLINE_ROT0_SSPP, 440 DPU_CLK_CTRL_REG_DMA, 441 DPU_CLK_CTRL_MAX, 442 }; 443 444 /* struct dpu_clk_ctrl_reg : Clock control register 445 * @reg_off: register offset 446 * @bit_off: bit offset 447 */ 448 struct dpu_clk_ctrl_reg { 449 u32 reg_off; 450 u32 bit_off; 451 }; 452 453 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info 454 * @id: index identifying this block 455 * @base: register base offset to mdss 456 * @features bit mask identifying sub-blocks/features 457 * @highest_bank_bit: UBWC parameter 458 * @ubwc_static: ubwc static configuration 459 * @ubwc_swizzle: ubwc default swizzle setting 460 * @clk_ctrls clock control register definition 461 */ 462 struct dpu_mdp_cfg { 463 DPU_HW_BLK_INFO; 464 u32 highest_bank_bit; 465 u32 ubwc_swizzle; 466 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; 467 }; 468 469 /* struct dpu_ctl_cfg : MDP CTL instance info 470 * @id: index identifying this block 471 * @base: register base offset to mdss 472 * @features bit mask identifying sub-blocks/features 473 * @intr_start: interrupt index for CTL_START 474 */ 475 struct dpu_ctl_cfg { 476 DPU_HW_BLK_INFO; 477 s32 intr_start; 478 }; 479 480 /** 481 * struct dpu_sspp_cfg - information of source pipes 482 * @id: index identifying this block 483 * @base register offset of this block 484 * @features bit mask identifying sub-blocks/features 485 * @sblk: SSPP sub-blocks information 486 * @xin_id: bus client identifier 487 * @clk_ctrl clock control identifier 488 * @type sspp type identifier 489 */ 490 struct dpu_sspp_cfg { 491 DPU_HW_BLK_INFO; 492 const struct dpu_sspp_sub_blks *sblk; 493 u32 xin_id; 494 enum dpu_clk_ctrl_type clk_ctrl; 495 u32 type; 496 }; 497 498 /** 499 * struct dpu_lm_cfg - information of layer mixer blocks 500 * @id: index identifying this block 501 * @base register offset of this block 502 * @features bit mask identifying sub-blocks/features 503 * @sblk: LM Sub-blocks information 504 * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported 505 * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL 506 */ 507 struct dpu_lm_cfg { 508 DPU_HW_BLK_INFO; 509 const struct dpu_lm_sub_blks *sblk; 510 u32 pingpong; 511 u32 dspp; 512 unsigned long lm_pair_mask; 513 }; 514 515 /** 516 * struct dpu_dspp_cfg - information of DSPP blocks 517 * @id enum identifying this block 518 * @base register offset of this block 519 * @features bit mask identifying sub-blocks/features 520 * supported by this block 521 * @sblk sub-blocks information 522 */ 523 struct dpu_dspp_cfg { 524 DPU_HW_BLK_INFO; 525 const struct dpu_dspp_sub_blks *sblk; 526 }; 527 528 /** 529 * struct dpu_pingpong_cfg - information of PING-PONG blocks 530 * @id enum identifying this block 531 * @base register offset of this block 532 * @features bit mask identifying sub-blocks/features 533 * @intr_done: index for PINGPONG done interrupt 534 * @intr_rdptr: index for PINGPONG readpointer done interrupt 535 * @sblk sub-blocks information 536 */ 537 struct dpu_pingpong_cfg { 538 DPU_HW_BLK_INFO; 539 u32 merge_3d; 540 s32 intr_done; 541 s32 intr_rdptr; 542 const struct dpu_pingpong_sub_blks *sblk; 543 }; 544 545 /** 546 * struct dpu_merge_3d_cfg - information of DSPP blocks 547 * @id enum identifying this block 548 * @base register offset of this block 549 * @features bit mask identifying sub-blocks/features 550 * supported by this block 551 * @sblk sub-blocks information 552 */ 553 struct dpu_merge_3d_cfg { 554 DPU_HW_BLK_INFO; 555 const struct dpu_merge_3d_sub_blks *sblk; 556 }; 557 558 /** 559 * struct dpu_intf_cfg - information of timing engine blocks 560 * @id enum identifying this block 561 * @base register offset of this block 562 * @features bit mask identifying sub-blocks/features 563 * @type: Interface type(DSI, DP, HDMI) 564 * @controller_id: Controller Instance ID in case of multiple of intf type 565 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch 566 * @intr_underrun: index for INTF underrun interrupt 567 * @intr_vsync: index for INTF VSYNC interrupt 568 */ 569 struct dpu_intf_cfg { 570 DPU_HW_BLK_INFO; 571 u32 type; /* interface type*/ 572 u32 controller_id; 573 u32 prog_fetch_lines_worst_case; 574 s32 intr_underrun; 575 s32 intr_vsync; 576 }; 577 578 /** 579 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting 580 * @pps pixel per seconds 581 * @ot_limit OT limit to use up to specified pixel per second 582 */ 583 struct dpu_vbif_dynamic_ot_cfg { 584 u64 pps; 585 u32 ot_limit; 586 }; 587 588 /** 589 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table 590 * @count length of cfg 591 * @cfg pointer to array of configuration settings with 592 * ascending requirements 593 */ 594 struct dpu_vbif_dynamic_ot_tbl { 595 u32 count; 596 const struct dpu_vbif_dynamic_ot_cfg *cfg; 597 }; 598 599 /** 600 * struct dpu_vbif_qos_tbl - QoS priority table 601 * @npriority_lvl num of priority level 602 * @priority_lvl pointer to array of priority level in ascending order 603 */ 604 struct dpu_vbif_qos_tbl { 605 u32 npriority_lvl; 606 const u32 *priority_lvl; 607 }; 608 609 /** 610 * struct dpu_vbif_cfg - information of VBIF blocks 611 * @id enum identifying this block 612 * @base register offset of this block 613 * @features bit mask identifying sub-blocks/features 614 * @ot_rd_limit default OT read limit 615 * @ot_wr_limit default OT write limit 616 * @xin_halt_timeout maximum time (in usec) for xin to halt 617 * @dynamic_ot_rd_tbl dynamic OT read configuration table 618 * @dynamic_ot_wr_tbl dynamic OT write configuration table 619 * @qos_rt_tbl real-time QoS priority table 620 * @qos_nrt_tbl non-real-time QoS priority table 621 * @memtype_count number of defined memtypes 622 * @memtype array of xin memtype definitions 623 */ 624 struct dpu_vbif_cfg { 625 DPU_HW_BLK_INFO; 626 u32 default_ot_rd_limit; 627 u32 default_ot_wr_limit; 628 u32 xin_halt_timeout; 629 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; 630 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; 631 struct dpu_vbif_qos_tbl qos_rt_tbl; 632 struct dpu_vbif_qos_tbl qos_nrt_tbl; 633 u32 memtype_count; 634 u32 memtype[MAX_XIN_COUNT]; 635 }; 636 /** 637 * struct dpu_reg_dma_cfg - information of lut dma blocks 638 * @id enum identifying this block 639 * @base register offset of this block 640 * @features bit mask identifying sub-blocks/features 641 * @version version of lutdma hw block 642 * @trigger_sel_off offset to trigger select registers of lutdma 643 */ 644 struct dpu_reg_dma_cfg { 645 DPU_HW_BLK_INFO; 646 u32 version; 647 u32 trigger_sel_off; 648 u32 xin_id; 649 enum dpu_clk_ctrl_type clk_ctrl; 650 }; 651 652 /** 653 * Define CDP use cases 654 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases 655 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD 656 */ 657 enum { 658 DPU_PERF_CDP_USAGE_RT, 659 DPU_PERF_CDP_USAGE_NRT, 660 DPU_PERF_CDP_USAGE_MAX 661 }; 662 663 /** 664 * struct dpu_perf_cdp_cfg - define CDP use case configuration 665 * @rd_enable: true if read pipe CDP is enabled 666 * @wr_enable: true if write pipe CDP is enabled 667 */ 668 struct dpu_perf_cdp_cfg { 669 bool rd_enable; 670 bool wr_enable; 671 }; 672 673 /** 674 * struct dpu_perf_cfg - performance control settings 675 * @max_bw_low low threshold of maximum bandwidth (kbps) 676 * @max_bw_high high threshold of maximum bandwidth (kbps) 677 * @min_core_ib minimum bandwidth for core (kbps) 678 * @min_core_ib minimum mnoc ib vote in kbps 679 * @min_llcc_ib minimum llcc ib vote in kbps 680 * @min_dram_ib minimum dram ib vote in kbps 681 * @core_ib_ff core instantaneous bandwidth fudge factor 682 * @core_clk_ff core clock fudge factor 683 * @comp_ratio_rt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio> 684 * @comp_ratio_nrt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio> 685 * @undersized_prefill_lines undersized prefill in lines 686 * @xtra_prefill_lines extra prefill latency in lines 687 * @dest_scale_prefill_lines destination scaler latency in lines 688 * @macrotile_perfill_lines macrotile latency in lines 689 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines 690 * @linear_prefill_lines linear latency in lines 691 * @downscaling_prefill_lines downscaling latency in lines 692 * @amortizable_theshold minimum y position for traffic shaping prefill 693 * @min_prefill_lines minimum pipeline latency in lines 694 * @clk_inefficiency_factor DPU src clock inefficiency factor 695 * @bw_inefficiency_factor DPU axi bus bw inefficiency factor 696 * @safe_lut_tbl: LUT tables for safe signals 697 * @danger_lut_tbl: LUT tables for danger signals 698 * @qos_lut_tbl: LUT tables for QoS signals 699 * @cdp_cfg cdp use case configurations 700 */ 701 struct dpu_perf_cfg { 702 u32 max_bw_low; 703 u32 max_bw_high; 704 u32 min_core_ib; 705 u32 min_llcc_ib; 706 u32 min_dram_ib; 707 const char *core_ib_ff; 708 const char *core_clk_ff; 709 const char *comp_ratio_rt; 710 const char *comp_ratio_nrt; 711 u32 undersized_prefill_lines; 712 u32 xtra_prefill_lines; 713 u32 dest_scale_prefill_lines; 714 u32 macrotile_prefill_lines; 715 u32 yuv_nv12_prefill_lines; 716 u32 linear_prefill_lines; 717 u32 downscaling_prefill_lines; 718 u32 amortizable_threshold; 719 u32 min_prefill_lines; 720 u32 clk_inefficiency_factor; 721 u32 bw_inefficiency_factor; 722 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 723 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 724 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 725 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX]; 726 }; 727 728 /** 729 * struct dpu_mdss_cfg - information of MDSS HW 730 * This is the main catalog data structure representing 731 * this HW version. Contains number of instances, 732 * register offsets, capabilities of the all MDSS HW sub-blocks. 733 * 734 * @dma_formats Supported formats for dma pipe 735 * @cursor_formats Supported formats for cursor pipe 736 * @vig_formats Supported formats for vig pipe 737 * @mdss_irqs: Bitmap with the irqs supported by the target 738 */ 739 struct dpu_mdss_cfg { 740 u32 hwversion; 741 742 const struct dpu_caps *caps; 743 744 u32 mdp_count; 745 const struct dpu_mdp_cfg *mdp; 746 747 u32 ctl_count; 748 const struct dpu_ctl_cfg *ctl; 749 750 u32 sspp_count; 751 const struct dpu_sspp_cfg *sspp; 752 753 u32 mixer_count; 754 const struct dpu_lm_cfg *mixer; 755 756 u32 pingpong_count; 757 const struct dpu_pingpong_cfg *pingpong; 758 759 u32 merge_3d_count; 760 const struct dpu_merge_3d_cfg *merge_3d; 761 762 u32 intf_count; 763 const struct dpu_intf_cfg *intf; 764 765 u32 vbif_count; 766 const struct dpu_vbif_cfg *vbif; 767 768 u32 reg_dma_count; 769 struct dpu_reg_dma_cfg dma_cfg; 770 771 u32 ad_count; 772 773 u32 dspp_count; 774 const struct dpu_dspp_cfg *dspp; 775 776 /* Add additional block data structures here */ 777 778 struct dpu_perf_cfg perf; 779 const struct dpu_format_extended *dma_formats; 780 const struct dpu_format_extended *cursor_formats; 781 const struct dpu_format_extended *vig_formats; 782 783 unsigned long mdss_irqs; 784 }; 785 786 struct dpu_mdss_hw_cfg_handler { 787 u32 hw_rev; 788 void (*cfg_init)(struct dpu_mdss_cfg *dpu_cfg); 789 }; 790 791 /* 792 * Access Macros 793 */ 794 #define BLK_MDP(s) ((s)->mdp) 795 #define BLK_CTL(s) ((s)->ctl) 796 #define BLK_VIG(s) ((s)->vig) 797 #define BLK_RGB(s) ((s)->rgb) 798 #define BLK_DMA(s) ((s)->dma) 799 #define BLK_CURSOR(s) ((s)->cursor) 800 #define BLK_MIXER(s) ((s)->mixer) 801 #define BLK_PINGPONG(s) ((s)->pingpong) 802 #define BLK_INTF(s) ((s)->intf) 803 #define BLK_AD(s) ((s)->ad) 804 #define BLK_DSPP(s) ((s)->dspp) 805 #define BLK_MERGE3d(s) ((s)->merge_3d) 806 807 /** 808 * dpu_hw_catalog_init - dpu hardware catalog init API retrieves 809 * hardcoded target specific catalog information in config structure 810 * @hw_rev: caller needs provide the hardware revision. 811 * 812 * Return: dpu config structure 813 */ 814 struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev); 815 816 /** 817 * dpu_hw_catalog_deinit - dpu hardware catalog cleanup 818 * @dpu_cfg: pointer returned from init function 819 */ 820 void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg); 821 822 #endif /* _DPU_HW_CATALOG_H */ 823