1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * core.h - DesignWare USB3 DRD Core Header
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #ifndef __DRIVERS_USB_DWC3_CORE_H
12 #define __DRIVERS_USB_DWC3_CORE_H
13
14 #include <linux/device.h>
15 #include <linux/spinlock.h>
16 #include <linux/mutex.h>
17 #include <linux/ioport.h>
18 #include <linux/list.h>
19 #include <linux/bitops.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/mm.h>
22 #include <linux/debugfs.h>
23 #include <linux/wait.h>
24 #include <linux/workqueue.h>
25 #include <linux/android_kabi.h>
26
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/otg.h>
30 #include <linux/usb/role.h>
31 #include <linux/ulpi/interface.h>
32
33 #include <linux/phy/phy.h>
34
35 #include <linux/power_supply.h>
36
37 #define DWC3_MSG_MAX 500
38
39 /* Global constants */
40 #define DWC3_PULL_UP_TIMEOUT 500 /* ms */
41 #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
42 #define DWC3_EP0_SETUP_SIZE 512
43 #define DWC3_ENDPOINTS_NUM 32
44 #define DWC3_XHCI_RESOURCES_NUM 2
45 #define DWC3_ISOC_MAX_RETRIES 5
46
47 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
48 #define DWC3_EVENT_BUFFERS_SIZE 4096
49 #define DWC3_EVENT_TYPE_MASK 0xfe
50
51 #define DWC3_EVENT_TYPE_DEV 0
52 #define DWC3_EVENT_TYPE_CARKIT 3
53 #define DWC3_EVENT_TYPE_I2C 4
54
55 #define DWC3_DEVICE_EVENT_DISCONNECT 0
56 #define DWC3_DEVICE_EVENT_RESET 1
57 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
58 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
59 #define DWC3_DEVICE_EVENT_WAKEUP 4
60 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
61 #define DWC3_DEVICE_EVENT_SUSPEND 6
62 #define DWC3_DEVICE_EVENT_SOF 7
63 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
64 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
65 #define DWC3_DEVICE_EVENT_OVERFLOW 11
66
67 /* Controller's role while using the OTG block */
68 #define DWC3_OTG_ROLE_IDLE 0
69 #define DWC3_OTG_ROLE_HOST 1
70 #define DWC3_OTG_ROLE_DEVICE 2
71
72 #define DWC3_GEVNTCOUNT_MASK 0xfffc
73 #define DWC3_GEVNTCOUNT_EHB BIT(31)
74 #define DWC3_GSNPSID_MASK 0xffff0000
75 #define DWC3_GSNPSREV_MASK 0xffff
76 #define DWC3_GSNPS_ID(p) (((p) & DWC3_GSNPSID_MASK) >> 16)
77
78 /* DWC3 registers memory space boundries */
79 #define DWC3_XHCI_REGS_START 0x0
80 #define DWC3_XHCI_REGS_END 0x7fff
81 #define DWC3_GLOBALS_REGS_START 0xc100
82 #define DWC3_GLOBALS_REGS_END 0xc6ff
83 #define DWC3_DEVICE_REGS_START 0xc700
84 #define DWC3_DEVICE_REGS_END 0xcbff
85 #define DWC3_OTG_REGS_START 0xcc00
86 #define DWC3_OTG_REGS_END 0xccff
87
88 /* Global Registers */
89 #define DWC3_GSBUSCFG0 0xc100
90 #define DWC3_GSBUSCFG1 0xc104
91 #define DWC3_GTXTHRCFG 0xc108
92 #define DWC3_GRXTHRCFG 0xc10c
93 #define DWC3_GCTL 0xc110
94 #define DWC3_GEVTEN 0xc114
95 #define DWC3_GSTS 0xc118
96 #define DWC3_GUCTL1 0xc11c
97 #define DWC3_GSNPSID 0xc120
98 #define DWC3_GGPIO 0xc124
99 #define DWC3_GUID 0xc128
100 #define DWC3_GUCTL 0xc12c
101 #define DWC3_GBUSERRADDR0 0xc130
102 #define DWC3_GBUSERRADDR1 0xc134
103 #define DWC3_GPRTBIMAP0 0xc138
104 #define DWC3_GPRTBIMAP1 0xc13c
105 #define DWC3_GHWPARAMS0 0xc140
106 #define DWC3_GHWPARAMS1 0xc144
107 #define DWC3_GHWPARAMS2 0xc148
108 #define DWC3_GHWPARAMS3 0xc14c
109 #define DWC3_GHWPARAMS4 0xc150
110 #define DWC3_GHWPARAMS5 0xc154
111 #define DWC3_GHWPARAMS6 0xc158
112 #define DWC3_GHWPARAMS7 0xc15c
113 #define DWC3_GDBGFIFOSPACE 0xc160
114 #define DWC3_GDBGLTSSM 0xc164
115 #define DWC3_GDBGBMU 0xc16c
116 #define DWC3_GDBGLSPMUX 0xc170
117 #define DWC3_GDBGLSP 0xc174
118 #define DWC3_GDBGEPINFO0 0xc178
119 #define DWC3_GDBGEPINFO1 0xc17c
120 #define DWC3_GPRTBIMAP_HS0 0xc180
121 #define DWC3_GPRTBIMAP_HS1 0xc184
122 #define DWC3_GPRTBIMAP_FS0 0xc188
123 #define DWC3_GPRTBIMAP_FS1 0xc18c
124 #define DWC3_GUCTL2 0xc19c
125
126 #define DWC3_VER_NUMBER 0xc1a0
127 #define DWC3_VER_TYPE 0xc1a4
128
129 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
130 #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
131
132 #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
133
134 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
135
136 #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
137 #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
138
139 #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
140 #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
141 #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
142 #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
143
144 #define DWC3_GHWPARAMS8 0xc600
145 #define DWC3_GUCTL3 0xc60c
146 #define DWC3_GFLADJ 0xc630
147 #define DWC3_GHWPARAMS9 0xc6e0
148
149 /* Device Registers */
150 #define DWC3_DCFG 0xc700
151 #define DWC3_DCTL 0xc704
152 #define DWC3_DEVTEN 0xc708
153 #define DWC3_DSTS 0xc70c
154 #define DWC3_DGCMDPAR 0xc710
155 #define DWC3_DGCMD 0xc714
156 #define DWC3_DALEPENA 0xc720
157
158 #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
159 #define DWC3_DEPCMDPAR2 0x00
160 #define DWC3_DEPCMDPAR1 0x04
161 #define DWC3_DEPCMDPAR0 0x08
162 #define DWC3_DEPCMD 0x0c
163
164 #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
165
166 /* OTG Registers */
167 #define DWC3_OCFG 0xcc00
168 #define DWC3_OCTL 0xcc04
169 #define DWC3_OEVT 0xcc08
170 #define DWC3_OEVTEN 0xcc0C
171 #define DWC3_OSTS 0xcc10
172
173 #define DWC3_LLUCTL 0xd024
174
175 /* Bit fields */
176
177 /* Global SoC Bus Configuration INCRx Register 0 */
178 #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
179 #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
180 #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
181 #define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
182 #define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
183 #define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
184 #define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
185 #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
186 #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
187
188 /* Global Debug LSP MUX Select */
189 #define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */
190 #define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff)
191 #define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4)
192 #define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf)
193
194 /* Global Debug Queue/FIFO Space Available Register */
195 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
196 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
197 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
198
199 #define DWC3_TXFIFO 0
200 #define DWC3_RXFIFO 1
201 #define DWC3_TXREQQ 2
202 #define DWC3_RXREQQ 3
203 #define DWC3_RXINFOQ 4
204 #define DWC3_PSTATQ 5
205 #define DWC3_DESCFETCHQ 6
206 #define DWC3_EVENTQ 7
207 #define DWC3_AUXEVENTQ 8
208
209 /* Global RX Threshold Configuration Register */
210 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
211 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
212 #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
213
214 /* Global RX Threshold Configuration Register for DWC_usb31 only */
215 #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
216 #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
217 #define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26)
218 #define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15)
219 #define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
220 #define DWC31_RXTHRNUMPKTSEL_PRD BIT(10)
221 #define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
222 #define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
223
224 /* Global TX Threshold Configuration Register for DWC_usb31 only */
225 #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
226 #define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21)
227 #define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26)
228 #define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15)
229 #define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
230 #define DWC31_TXTHRNUMPKTSEL_PRD BIT(10)
231 #define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
232 #define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f)
233
234 /* Global Configuration Register */
235 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
236 #define DWC3_GCTL_PWRDNSCALE_MASK DWC3_GCTL_PWRDNSCALE(0x1fff)
237 #define DWC3_GCTL_U2RSTECN BIT(16)
238 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
239 #define DWC3_GCTL_CLK_BUS (0)
240 #define DWC3_GCTL_CLK_PIPE (1)
241 #define DWC3_GCTL_CLK_PIPEHALF (2)
242 #define DWC3_GCTL_CLK_MASK (3)
243
244 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
245 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
246 #define DWC3_GCTL_PRTCAP_HOST 1
247 #define DWC3_GCTL_PRTCAP_DEVICE 2
248 #define DWC3_GCTL_PRTCAP_OTG 3
249
250 #define DWC3_GCTL_CORESOFTRESET BIT(11)
251 #define DWC3_GCTL_SOFITPSYNC BIT(10)
252 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
253 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
254 #define DWC3_GCTL_DISSCRAMBLE BIT(3)
255 #define DWC3_GCTL_U2EXIT_LFPS BIT(2)
256 #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
257 #define DWC3_GCTL_DSBLCLKGTNG BIT(0)
258
259 /* Global User Control 1 Register */
260 #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31)
261 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
262 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
263 #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
264
265 /* Global Status Register */
266 #define DWC3_GSTS_OTG_IP BIT(10)
267 #define DWC3_GSTS_BC_IP BIT(9)
268 #define DWC3_GSTS_ADP_IP BIT(8)
269 #define DWC3_GSTS_HOST_IP BIT(7)
270 #define DWC3_GSTS_DEVICE_IP BIT(6)
271 #define DWC3_GSTS_CSR_TIMEOUT BIT(5)
272 #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
273 #define DWC3_GSTS_CURMOD(n) ((n) & 0x3)
274 #define DWC3_GSTS_CURMOD_DEVICE 0
275 #define DWC3_GSTS_CURMOD_HOST 1
276
277 /* Global USB2 PHY Configuration Register */
278 #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
279 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
280 #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
281 #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
282 #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
283 #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
284 #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
285 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
286 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
287 #define USBTRDTIM_UTMI_8_BIT 9
288 #define USBTRDTIM_UTMI_16_BIT 5
289 #define UTMI_PHYIF_16_BIT 1
290 #define UTMI_PHYIF_8_BIT 0
291
292 /* Global USB2 PHY Vendor Control Register */
293 #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
294 #define DWC3_GUSB2PHYACC_DONE BIT(24)
295 #define DWC3_GUSB2PHYACC_BUSY BIT(23)
296 #define DWC3_GUSB2PHYACC_WRITE BIT(22)
297 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
298 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
299 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
300
301 /* Global USB3 PIPE Control Register */
302 #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
303 #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29)
304 #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28)
305 #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27)
306 #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24)
307 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
308 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
309 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
310 #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18)
311 #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17)
312 #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9)
313 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8)
314 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
315 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
316
317 /* Global TX Fifo Size Register */
318 #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */
319 #define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
320 #define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff)
321 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
322
323 /* Global RX Fifo Size Register */
324 #define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
325 #define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff)
326
327 /* Global Event Size Registers */
328 #define DWC3_GEVNTSIZ_INTMASK BIT(31)
329 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
330
331 /* Global HWPARAMS0 Register */
332 #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
333 #define DWC3_GHWPARAMS0_MODE_GADGET 0
334 #define DWC3_GHWPARAMS0_MODE_HOST 1
335 #define DWC3_GHWPARAMS0_MODE_DRD 2
336 #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
337 #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
338 #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
339 #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
340 #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
341
342 /* Global HWPARAMS1 Register */
343 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
344 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
345 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
346 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
347 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
348 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
349 #define DWC3_GHWPARAMS1_ENDBC BIT(31)
350
351 /* Global HWPARAMS3 Register */
352 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
353 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
354 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
355 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */
356 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
357 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
358 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
359 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
360 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
361 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
362 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
363 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
364
365 /* Global HWPARAMS4 Register */
366 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
367 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
368
369 /* Global HWPARAMS6 Register */
370 #define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
371 #define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
372 #define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
373 #define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
374 #define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
375 #define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
376
377 /* DWC_usb32 only */
378 #define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8))
379
380 /* Global HWPARAMS7 Register */
381 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
382 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
383
384 /* Global HWPARAMS9 Register */
385 #define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS BIT(0)
386
387 /* Global Frame Length Adjustment Register */
388 #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7)
389 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
390
391 /* Global User Control Register 2 */
392 #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
393
394 /* Global User Control Register 3 */
395 #define DWC3_GUCTL3_SPLITDISABLE BIT(14)
396
397 /* Device Configuration Register */
398 #define DWC3_DCFG_NUMLANES(n) (((n) & 0x3) << 30) /* DWC_usb32 only */
399
400 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
401 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
402
403 #define DWC3_DCFG_SPEED_MASK (7 << 0)
404 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
405 #define DWC3_DCFG_SUPERSPEED (4 << 0)
406 #define DWC3_DCFG_HIGHSPEED (0 << 0)
407 #define DWC3_DCFG_FULLSPEED BIT(0)
408
409 #define DWC3_DCFG_NUMP_SHIFT 17
410 #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
411 #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
412 #define DWC3_DCFG_LPM_CAP BIT(22)
413 #define DWC3_DCFG_IGNSTRMPP BIT(23)
414
415 /* Device Control Register */
416 #define DWC3_DCTL_RUN_STOP BIT(31)
417 #define DWC3_DCTL_CSFTRST BIT(30)
418 #define DWC3_DCTL_LSFTRST BIT(29)
419
420 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
421 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
422
423 #define DWC3_DCTL_APPL1RES BIT(23)
424
425 /* These apply for core versions 1.87a and earlier */
426 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
427 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
428 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
429 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
430 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
431 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
432 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
433
434 /* These apply for core versions 1.94a and later */
435 #define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20)
436
437 #define DWC3_DCTL_KEEP_CONNECT BIT(19)
438 #define DWC3_DCTL_L1_HIBER_EN BIT(18)
439 #define DWC3_DCTL_CRS BIT(17)
440 #define DWC3_DCTL_CSS BIT(16)
441
442 #define DWC3_DCTL_INITU2ENA BIT(12)
443 #define DWC3_DCTL_ACCEPTU2ENA BIT(11)
444 #define DWC3_DCTL_INITU1ENA BIT(10)
445 #define DWC3_DCTL_ACCEPTU1ENA BIT(9)
446 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
447
448 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
449 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
450
451 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
452 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
453 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
454 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
455 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
456 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
457 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
458
459 /* Device Event Enable Register */
460 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12)
461 #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11)
462 #define DWC3_DEVTEN_CMDCMPLTEN BIT(10)
463 #define DWC3_DEVTEN_ERRTICERREN BIT(9)
464 #define DWC3_DEVTEN_SOFEN BIT(7)
465 #define DWC3_DEVTEN_U3L2L1SUSPEN BIT(6)
466 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5)
467 #define DWC3_DEVTEN_WKUPEVTEN BIT(4)
468 #define DWC3_DEVTEN_ULSTCNGEN BIT(3)
469 #define DWC3_DEVTEN_CONNECTDONEEN BIT(2)
470 #define DWC3_DEVTEN_USBRSTEN BIT(1)
471 #define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
472
473 #define DWC3_DSTS_CONNLANES(n) (((n) >> 30) & 0x3) /* DWC_usb32 only */
474
475 /* Device Status Register */
476 #define DWC3_DSTS_DCNRD BIT(29)
477
478 /* This applies for core versions 1.87a and earlier */
479 #define DWC3_DSTS_PWRUPREQ BIT(24)
480
481 /* These apply for core versions 1.94a and later */
482 #define DWC3_DSTS_RSS BIT(25)
483 #define DWC3_DSTS_SSS BIT(24)
484
485 #define DWC3_DSTS_COREIDLE BIT(23)
486 #define DWC3_DSTS_DEVCTRLHLT BIT(22)
487
488 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
489 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
490
491 #define DWC3_DSTS_RXFIFOEMPTY BIT(17)
492
493 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
494 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
495
496 #define DWC3_DSTS_CONNECTSPD (7 << 0)
497
498 #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
499 #define DWC3_DSTS_SUPERSPEED (4 << 0)
500 #define DWC3_DSTS_HIGHSPEED (0 << 0)
501 #define DWC3_DSTS_FULLSPEED BIT(0)
502
503 /* Device Generic Command Register */
504 #define DWC3_DGCMD_SET_LMP 0x01
505 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
506 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
507
508 /* These apply for core versions 1.94a and later */
509 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
510 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
511
512 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
513 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
514 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
515 #define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d
516 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
517
518 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
519 #define DWC3_DGCMD_CMDACT BIT(10)
520 #define DWC3_DGCMD_CMDIOC BIT(8)
521
522 /* Device Generic Command Parameter Register */
523 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
524 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
525 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
526 #define DWC3_DGCMDPAR_TX_FIFO BIT(5)
527 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
528 #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
529
530 /* Device Endpoint Command Register */
531 #define DWC3_DEPCMD_PARAM_SHIFT 16
532 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
533 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
534 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
535 #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11)
536 #define DWC3_DEPCMD_CLEARPENDIN BIT(11)
537 #define DWC3_DEPCMD_CMDACT BIT(10)
538 #define DWC3_DEPCMD_CMDIOC BIT(8)
539
540 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
541 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
542 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
543 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
544 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
545 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
546 /* This applies for core versions 1.90a and earlier */
547 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
548 /* This applies for core versions 1.94a and later */
549 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
550 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
551 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
552
553 #define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
554
555 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
556 #define DWC3_DALEPENA_EP(n) BIT(n)
557
558 #define DWC3_DEPCMD_TYPE_CONTROL 0
559 #define DWC3_DEPCMD_TYPE_ISOC 1
560 #define DWC3_DEPCMD_TYPE_BULK 2
561 #define DWC3_DEPCMD_TYPE_INTR 3
562
563 #define DWC3_DEV_IMOD_COUNT_SHIFT 16
564 #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
565 #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
566 #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
567
568 /* OTG Configuration Register */
569 #define DWC3_OCFG_DISPWRCUTTOFF BIT(5)
570 #define DWC3_OCFG_HIBDISMASK BIT(4)
571 #define DWC3_OCFG_SFTRSTMASK BIT(3)
572 #define DWC3_OCFG_OTGVERSION BIT(2)
573 #define DWC3_OCFG_HNPCAP BIT(1)
574 #define DWC3_OCFG_SRPCAP BIT(0)
575
576 /* OTG CTL Register */
577 #define DWC3_OCTL_OTG3GOERR BIT(7)
578 #define DWC3_OCTL_PERIMODE BIT(6)
579 #define DWC3_OCTL_PRTPWRCTL BIT(5)
580 #define DWC3_OCTL_HNPREQ BIT(4)
581 #define DWC3_OCTL_SESREQ BIT(3)
582 #define DWC3_OCTL_TERMSELIDPULSE BIT(2)
583 #define DWC3_OCTL_DEVSETHNPEN BIT(1)
584 #define DWC3_OCTL_HSTSETHNPEN BIT(0)
585
586 /* OTG Event Register */
587 #define DWC3_OEVT_DEVICEMODE BIT(31)
588 #define DWC3_OEVT_XHCIRUNSTPSET BIT(27)
589 #define DWC3_OEVT_DEVRUNSTPSET BIT(26)
590 #define DWC3_OEVT_HIBENTRY BIT(25)
591 #define DWC3_OEVT_CONIDSTSCHNG BIT(24)
592 #define DWC3_OEVT_HRRCONFNOTIF BIT(23)
593 #define DWC3_OEVT_HRRINITNOTIF BIT(22)
594 #define DWC3_OEVT_ADEVIDLE BIT(21)
595 #define DWC3_OEVT_ADEVBHOSTEND BIT(20)
596 #define DWC3_OEVT_ADEVHOST BIT(19)
597 #define DWC3_OEVT_ADEVHNPCHNG BIT(18)
598 #define DWC3_OEVT_ADEVSRPDET BIT(17)
599 #define DWC3_OEVT_ADEVSESSENDDET BIT(16)
600 #define DWC3_OEVT_BDEVBHOSTEND BIT(11)
601 #define DWC3_OEVT_BDEVHNPCHNG BIT(10)
602 #define DWC3_OEVT_BDEVSESSVLDDET BIT(9)
603 #define DWC3_OEVT_BDEVVBUSCHNG BIT(8)
604 #define DWC3_OEVT_BSESSVLD BIT(3)
605 #define DWC3_OEVT_HSTNEGSTS BIT(2)
606 #define DWC3_OEVT_SESREQSTS BIT(1)
607 #define DWC3_OEVT_ERROR BIT(0)
608
609 /* OTG Event Enable Register */
610 #define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27)
611 #define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26)
612 #define DWC3_OEVTEN_HIBENTRYEN BIT(25)
613 #define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24)
614 #define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23)
615 #define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22)
616 #define DWC3_OEVTEN_ADEVIDLEEN BIT(21)
617 #define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20)
618 #define DWC3_OEVTEN_ADEVHOSTEN BIT(19)
619 #define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18)
620 #define DWC3_OEVTEN_ADEVSRPDETEN BIT(17)
621 #define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16)
622 #define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11)
623 #define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10)
624 #define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9)
625 #define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8)
626
627 /* OTG Status Register */
628 #define DWC3_OSTS_DEVRUNSTP BIT(13)
629 #define DWC3_OSTS_XHCIRUNSTP BIT(12)
630 #define DWC3_OSTS_PERIPHERALSTATE BIT(4)
631 #define DWC3_OSTS_XHCIPRTPOWER BIT(3)
632 #define DWC3_OSTS_BSESVLD BIT(2)
633 #define DWC3_OSTS_VBUSVLD BIT(1)
634 #define DWC3_OSTS_CONIDSTS BIT(0)
635
636 /* Force Gen1 speed on Gen2 link */
637 #define DWC3_LLUCTL_FORCE_GEN1 BIT(10)
638
639 /* Structures */
640
641 struct dwc3_trb;
642
643 /**
644 * struct dwc3_event_buffer - Software event buffer representation
645 * @buf: _THE_ buffer
646 * @cache: The buffer cache used in the threaded interrupt
647 * @length: size of this buffer
648 * @lpos: event offset
649 * @count: cache of last read event count register
650 * @flags: flags related to this event buffer
651 * @dma: dma_addr_t
652 * @dwc: pointer to DWC controller
653 */
654 struct dwc3_event_buffer {
655 void *buf;
656 void *cache;
657 unsigned int length;
658 unsigned int lpos;
659 unsigned int count;
660 unsigned int flags;
661
662 #define DWC3_EVENT_PENDING BIT(0)
663
664 dma_addr_t dma;
665
666 struct dwc3 *dwc;
667
668 ANDROID_KABI_RESERVE(1);
669 };
670
671 #define DWC3_EP_FLAG_STALLED BIT(0)
672 #define DWC3_EP_FLAG_WEDGED BIT(1)
673
674 #define DWC3_EP_DIRECTION_TX true
675 #define DWC3_EP_DIRECTION_RX false
676
677 #define DWC3_TRB_NUM 256
678
679 /**
680 * struct dwc3_ep - device side endpoint representation
681 * @endpoint: usb endpoint
682 * @cancelled_list: list of cancelled requests for this endpoint
683 * @pending_list: list of pending requests for this endpoint
684 * @started_list: list of started requests on this endpoint
685 * @regs: pointer to first endpoint register
686 * @trb_pool: array of transaction buffers
687 * @trb_pool_dma: dma address of @trb_pool
688 * @trb_enqueue: enqueue 'pointer' into TRB array
689 * @trb_dequeue: dequeue 'pointer' into TRB array
690 * @dwc: pointer to DWC controller
691 * @saved_state: ep state saved during hibernation
692 * @flags: endpoint flags (wedged, stalled, ...)
693 * @number: endpoint number (1 - 15)
694 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
695 * @resource_index: Resource transfer index
696 * @frame_number: set to the frame number we want this transfer to start (ISOC)
697 * @interval: the interval on which the ISOC transfer is started
698 * @name: a human readable name e.g. ep1out-bulk
699 * @direction: true for TX, false for RX
700 * @stream_capable: true when streams are enabled
701 * @combo_num: the test combination BIT[15:14] of the frame number to test
702 * isochronous START TRANSFER command failure workaround
703 * @start_cmd_status: the status of testing START TRANSFER command with
704 * combo_num = 'b00
705 */
706 struct dwc3_ep {
707 struct usb_ep endpoint;
708 struct list_head cancelled_list;
709 struct list_head pending_list;
710 struct list_head started_list;
711
712 void __iomem *regs;
713
714 struct dwc3_trb *trb_pool;
715 dma_addr_t trb_pool_dma;
716 struct dwc3 *dwc;
717
718 u32 saved_state;
719 unsigned int flags;
720 #define DWC3_EP_ENABLED BIT(0)
721 #define DWC3_EP_STALL BIT(1)
722 #define DWC3_EP_WEDGE BIT(2)
723 #define DWC3_EP_TRANSFER_STARTED BIT(3)
724 #define DWC3_EP_END_TRANSFER_PENDING BIT(4)
725 #define DWC3_EP_PENDING_REQUEST BIT(5)
726 #define DWC3_EP_DELAY_START BIT(6)
727 #define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7)
728 #define DWC3_EP_IGNORE_NEXT_NOSTREAM BIT(8)
729 #define DWC3_EP_FORCE_RESTART_STREAM BIT(9)
730 #define DWC3_EP_FIRST_STREAM_PRIMED BIT(10)
731 #define DWC3_EP_PENDING_CLEAR_STALL BIT(11)
732 #define DWC3_EP_TXFIFO_RESIZED BIT(12)
733 #define DWC3_EP_DELAY_STOP BIT(13)
734
735 /* This last one is specific to EP0 */
736 #define DWC3_EP0_DIR_IN BIT(31)
737
738 /*
739 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
740 * use a u8 type here. If anybody decides to increase number of TRBs to
741 * anything larger than 256 - I can't see why people would want to do
742 * this though - then this type needs to be changed.
743 *
744 * By using u8 types we ensure that our % operator when incrementing
745 * enqueue and dequeue get optimized away by the compiler.
746 */
747 u8 trb_enqueue;
748 u8 trb_dequeue;
749
750 u8 number;
751 u8 type;
752 u8 resource_index;
753 u32 frame_number;
754 u32 interval;
755
756 char name[20];
757
758 unsigned direction:1;
759 unsigned stream_capable:1;
760
761 /* For isochronous START TRANSFER workaround only */
762 u8 combo_num;
763 int start_cmd_status;
764
765 ANDROID_KABI_RESERVE(1);
766 ANDROID_KABI_RESERVE(2);
767 };
768
769 enum dwc3_phy {
770 DWC3_PHY_UNKNOWN = 0,
771 DWC3_PHY_USB3,
772 DWC3_PHY_USB2,
773 };
774
775 enum dwc3_ep0_next {
776 DWC3_EP0_UNKNOWN = 0,
777 DWC3_EP0_COMPLETE,
778 DWC3_EP0_NRDY_DATA,
779 DWC3_EP0_NRDY_STATUS,
780 };
781
782 enum dwc3_ep0_state {
783 EP0_UNCONNECTED = 0,
784 EP0_SETUP_PHASE,
785 EP0_DATA_PHASE,
786 EP0_STATUS_PHASE,
787 };
788
789 enum dwc3_link_state {
790 /* In SuperSpeed */
791 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
792 DWC3_LINK_STATE_U1 = 0x01,
793 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
794 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
795 DWC3_LINK_STATE_SS_DIS = 0x04,
796 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
797 DWC3_LINK_STATE_SS_INACT = 0x06,
798 DWC3_LINK_STATE_POLL = 0x07,
799 DWC3_LINK_STATE_RECOV = 0x08,
800 DWC3_LINK_STATE_HRESET = 0x09,
801 DWC3_LINK_STATE_CMPLY = 0x0a,
802 DWC3_LINK_STATE_LPBK = 0x0b,
803 DWC3_LINK_STATE_RESET = 0x0e,
804 DWC3_LINK_STATE_RESUME = 0x0f,
805 DWC3_LINK_STATE_MASK = 0x0f,
806 };
807
808 /* TRB Length, PCM and Status */
809 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
810 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
811 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
812 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
813
814 #define DWC3_TRBSTS_OK 0
815 #define DWC3_TRBSTS_MISSED_ISOC 1
816 #define DWC3_TRBSTS_SETUP_PENDING 2
817 #define DWC3_TRB_STS_XFER_IN_PROG 4
818
819 /* TRB Control */
820 #define DWC3_TRB_CTRL_HWO BIT(0)
821 #define DWC3_TRB_CTRL_LST BIT(1)
822 #define DWC3_TRB_CTRL_CHN BIT(2)
823 #define DWC3_TRB_CTRL_CSP BIT(3)
824 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
825 #define DWC3_TRB_CTRL_ISP_IMI BIT(10)
826 #define DWC3_TRB_CTRL_IOC BIT(11)
827 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
828 #define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14)
829
830 #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
831 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
832 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
833 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
834 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
835 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
836 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
837 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
838 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
839
840 /**
841 * struct dwc3_trb - transfer request block (hw format)
842 * @bpl: DW0-3
843 * @bph: DW4-7
844 * @size: DW8-B
845 * @ctrl: DWC-F
846 */
847 struct dwc3_trb {
848 u32 bpl;
849 u32 bph;
850 u32 size;
851 u32 ctrl;
852 } __packed;
853
854 /**
855 * struct dwc3_hwparams - copy of HWPARAMS registers
856 * @hwparams0: GHWPARAMS0
857 * @hwparams1: GHWPARAMS1
858 * @hwparams2: GHWPARAMS2
859 * @hwparams3: GHWPARAMS3
860 * @hwparams4: GHWPARAMS4
861 * @hwparams5: GHWPARAMS5
862 * @hwparams6: GHWPARAMS6
863 * @hwparams7: GHWPARAMS7
864 * @hwparams8: GHWPARAMS8
865 * @hwparams9: GHWPARAMS9
866 */
867 struct dwc3_hwparams {
868 u32 hwparams0;
869 u32 hwparams1;
870 u32 hwparams2;
871 u32 hwparams3;
872 u32 hwparams4;
873 u32 hwparams5;
874 u32 hwparams6;
875 u32 hwparams7;
876 u32 hwparams8;
877 u32 hwparams9;
878
879 ANDROID_KABI_RESERVE(1);
880 ANDROID_KABI_RESERVE(2);
881 };
882
883 /* HWPARAMS0 */
884 #define DWC3_MODE(n) ((n) & 0x7)
885
886 /* HWPARAMS1 */
887 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
888
889 /* HWPARAMS3 */
890 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
891 #define DWC3_NUM_EPS_MASK (0x3f << 12)
892 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
893 (DWC3_NUM_EPS_MASK)) >> 12)
894 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
895 (DWC3_NUM_IN_EPS_MASK)) >> 18)
896
897 /* HWPARAMS7 */
898 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
899
900 /**
901 * struct dwc3_request - representation of a transfer request
902 * @request: struct usb_request to be transferred
903 * @list: a list_head used for request queueing
904 * @dep: struct dwc3_ep owning this request
905 * @sg: pointer to first incomplete sg
906 * @start_sg: pointer to the sg which should be queued next
907 * @num_pending_sgs: counter to pending sgs
908 * @num_queued_sgs: counter to the number of sgs which already got queued
909 * @remaining: amount of data remaining
910 * @status: internal dwc3 request status tracking
911 * @epnum: endpoint number to which this request refers
912 * @trb: pointer to struct dwc3_trb
913 * @trb_dma: DMA address of @trb
914 * @num_trbs: number of TRBs used by this request
915 * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP
916 * or unaligned OUT)
917 * @direction: IN or OUT direction flag
918 * @mapped: true when request has been dma-mapped
919 */
920 struct dwc3_request {
921 struct usb_request request;
922 struct list_head list;
923 struct dwc3_ep *dep;
924 struct scatterlist *sg;
925 struct scatterlist *start_sg;
926
927 unsigned int num_pending_sgs;
928 unsigned int num_queued_sgs;
929 unsigned int remaining;
930
931 unsigned int status;
932 #define DWC3_REQUEST_STATUS_QUEUED 0
933 #define DWC3_REQUEST_STATUS_STARTED 1
934 #define DWC3_REQUEST_STATUS_DISCONNECTED 2
935 #define DWC3_REQUEST_STATUS_DEQUEUED 3
936 #define DWC3_REQUEST_STATUS_STALLED 4
937 #define DWC3_REQUEST_STATUS_COMPLETED 5
938 #define DWC3_REQUEST_STATUS_UNKNOWN -1
939
940 u8 epnum;
941 struct dwc3_trb *trb;
942 dma_addr_t trb_dma;
943
944 unsigned int num_trbs;
945
946 unsigned int needs_extra_trb:1;
947 unsigned int direction:1;
948 unsigned int mapped:1;
949
950 ANDROID_KABI_RESERVE(1);
951 ANDROID_KABI_RESERVE(2);
952 };
953
954 /*
955 * struct dwc3_scratchpad_array - hibernation scratchpad array
956 * (format defined by hw)
957 */
958 struct dwc3_scratchpad_array {
959 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
960 };
961
962 /**
963 * struct dwc3 - representation of our controller
964 * @drd_work: workqueue used for role swapping
965 * @ep0_trb: trb which is used for the ctrl_req
966 * @bounce: address of bounce buffer
967 * @scratchbuf: address of scratch buffer
968 * @setup_buf: used while precessing STD USB requests
969 * @ep0_trb_addr: dma address of @ep0_trb
970 * @bounce_addr: dma address of @bounce
971 * @ep0_usb_req: dummy req used while handling STD USB requests
972 * @scratch_addr: dma address of scratchbuf
973 * @ep0_in_setup: one control transfer is completed and enter setup phase
974 * @lock: for synchronizing
975 * @mutex: for mode switching
976 * @dev: pointer to our struct device
977 * @sysdev: pointer to the DMA-capable device
978 * @xhci: pointer to our xHCI child
979 * @xhci_resources: struct resources for our @xhci child
980 * @ev_buf: struct dwc3_event_buffer pointer
981 * @eps: endpoint array
982 * @gadget: device side representation of the peripheral controller
983 * @gadget_driver: pointer to the gadget driver
984 * @clks: array of clocks
985 * @num_clks: number of clocks
986 * @reset: reset control
987 * @regs: base address for our registers
988 * @regs_size: address space size
989 * @fladj: frame length adjustment
990 * @irq_gadget: peripheral controller's IRQ number
991 * @otg_irq: IRQ number for OTG IRQs
992 * @current_otg_role: current role of operation while using the OTG block
993 * @desired_otg_role: desired role of operation while using the OTG block
994 * @otg_restart_host: flag that OTG controller needs to restart host
995 * @nr_scratch: number of scratch buffers
996 * @u1u2: only used on revisions <1.83a for workaround
997 * @maximum_speed: maximum speed requested (mainly for testing purposes)
998 * @max_ssp_rate: SuperSpeed Plus maximum signaling rate and lane count
999 * @gadget_max_speed: maximum gadget speed requested
1000 * @gadget_ssp_rate: Gadget driver's maximum supported SuperSpeed Plus signaling
1001 * rate and lane count.
1002 * @ip: controller's ID
1003 * @revision: controller's version of an IP
1004 * @version_type: VERSIONTYPE register contents, a sub release of a revision
1005 * @dr_mode: requested mode of operation
1006 * @current_dr_role: current role of operation when in dual-role mode
1007 * @desired_dr_role: desired role of operation when in dual-role mode
1008 * @edev: extcon handle
1009 * @edev_nb: extcon notifier
1010 * @hsphy_mode: UTMI phy mode, one of following:
1011 * - USBPHY_INTERFACE_MODE_UTMI
1012 * - USBPHY_INTERFACE_MODE_UTMIW
1013 * @role_sw: usb_role_switch handle
1014 * @role_switch_default_mode: default operation mode of controller while
1015 * usb role is USB_ROLE_NONE.
1016 * @usb_psy: pointer to power supply interface.
1017 * @usb2_phy: pointer to USB2 PHY
1018 * @usb3_phy: pointer to USB3 PHY
1019 * @usb2_generic_phy: pointer to USB2 PHY
1020 * @usb3_generic_phy: pointer to USB3 PHY
1021 * @phys_ready: flag to indicate that PHYs are ready
1022 * @ulpi: pointer to ulpi interface
1023 * @ulpi_ready: flag to indicate that ULPI is initialized
1024 * @u2sel: parameter from Set SEL request.
1025 * @u2pel: parameter from Set SEL request.
1026 * @u1sel: parameter from Set SEL request.
1027 * @u1pel: parameter from Set SEL request.
1028 * @num_eps: number of endpoints
1029 * @ep0_next_event: hold the next expected event
1030 * @ep0state: state of endpoint zero
1031 * @link_state: link state
1032 * @speed: device speed (super, high, full, low)
1033 * @hwparams: copy of hwparams registers
1034 * @regset: debugfs pointer to regdump file
1035 * @dbg_lsp_select: current debug lsp mux register selection
1036 * @test_mode: true when we're entering a USB test mode
1037 * @test_mode_nr: test feature selector
1038 * @lpm_nyet_threshold: LPM NYET response threshold
1039 * @hird_threshold: HIRD threshold
1040 * @rx_thr_num_pkt_prd: periodic ESS receive packet count
1041 * @rx_max_burst_prd: max periodic ESS receive burst size
1042 * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
1043 * @tx_max_burst_prd: max periodic ESS transmit burst size
1044 * @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize
1045 * @hsphy_interface: "utmi" or "ulpi"
1046 * @connected: true when we're connected to a host, false otherwise
1047 * @softconnect: true when gadget connect is called, false when disconnect runs
1048 * @delayed_status: true when gadget driver asks for delayed status
1049 * @ep0_bounced: true when we used bounce buffer
1050 * @ep0_expect_in: true when we expect a DATA IN transfer
1051 * @has_hibernation: true when dwc3 was configured with Hibernation
1052 * @sysdev_is_parent: true when dwc3 device has a parent driver
1053 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
1054 * there's now way for software to detect this in runtime.
1055 * @is_utmi_l1_suspend: the core asserts output signal
1056 * 0 - utmi_sleep_n
1057 * 1 - utmi_l1_suspend_n
1058 * @is_fpga: true when we are using the FPGA board
1059 * @pending_events: true when we have pending IRQs to be handled
1060 * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints
1061 * @pullups_connected: true when Run/Stop bit is set
1062 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
1063 * @three_stage_setup: set if we perform a three phase setup
1064 * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is
1065 * not needed for DWC_usb31 version 1.70a-ea06 and below
1066 * @usb3_lpm_capable: set if hadrware supports Link Power Management
1067 * @usb2_lpm_disable: set to disable usb2 lpm for host
1068 * @usb2_gadget_lpm_disable: set to disable usb2 lpm for gadget
1069 * @disable_scramble_quirk: set if we enable the disable scramble quirk
1070 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
1071 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
1072 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
1073 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
1074 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
1075 * @lfps_filter_quirk: set if we enable LFPS filter quirk
1076 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
1077 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
1078 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
1079 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
1080 * disabling the suspend signal to the PHY.
1081 * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled.
1082 * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled.
1083 * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3
1084 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
1085 * in GUSB2PHYCFG, specify that USB2 PHY doesn't
1086 * provide a free-running PHY clock.
1087 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
1088 * change quirk.
1089 * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
1090 * check during HS transmit.
1091 * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
1092 * instances in park mode.
1093 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
1094 * @tx_de_emphasis: Tx de-emphasis value
1095 * 0 - -6dB de-emphasis
1096 * 1 - -3.5dB de-emphasis
1097 * 2 - No de-emphasis
1098 * 3 - Reserved
1099 * @dis_metastability_quirk: set to disable metastability quirk.
1100 * @dis_split_quirk: set to disable split boundary.
1101 * @imod_interval: set the interrupt moderation interval in 250ns
1102 * increments or 0 to disable.
1103 * @max_cfg_eps: current max number of IN eps used across all USB configs.
1104 * @last_fifo_depth: last fifo depth used to determine next fifo ram start
1105 * address.
1106 * @num_ep_resized: carries the current number endpoints which have had its tx
1107 * fifo resized.
1108 * @clear_stall_protocol: endpoint number that requires a delayed status phase.
1109 * @debug_root: root debugfs directory for this device to put its files in.
1110 */
1111 struct dwc3 {
1112 struct work_struct drd_work;
1113 struct dwc3_trb *ep0_trb;
1114 void *bounce;
1115 void *scratchbuf;
1116 u8 *setup_buf;
1117 dma_addr_t ep0_trb_addr;
1118 dma_addr_t bounce_addr;
1119 dma_addr_t scratch_addr;
1120 struct dwc3_request ep0_usb_req;
1121 struct completion ep0_in_setup;
1122
1123 /* device lock */
1124 spinlock_t lock;
1125
1126 /* mode switching lock */
1127 struct mutex mutex;
1128
1129 struct device *dev;
1130 struct device *sysdev;
1131
1132 struct platform_device *xhci;
1133 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
1134
1135 struct dwc3_event_buffer *ev_buf;
1136 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
1137
1138 struct usb_gadget *gadget;
1139 struct usb_gadget_driver *gadget_driver;
1140
1141 struct clk_bulk_data *clks;
1142 int num_clks;
1143
1144 struct reset_control *reset;
1145
1146 struct usb_phy *usb2_phy;
1147 struct usb_phy *usb3_phy;
1148
1149 struct phy *usb2_generic_phy;
1150 struct phy *usb3_generic_phy;
1151
1152 bool phys_ready;
1153
1154 struct ulpi *ulpi;
1155 bool ulpi_ready;
1156
1157 void __iomem *regs;
1158 size_t regs_size;
1159
1160 enum usb_dr_mode dr_mode;
1161 u32 current_dr_role;
1162 u32 desired_dr_role;
1163 struct extcon_dev *edev;
1164 struct notifier_block edev_nb;
1165 enum usb_phy_interface hsphy_mode;
1166 struct usb_role_switch *role_sw;
1167 enum usb_dr_mode role_switch_default_mode;
1168
1169 struct power_supply *usb_psy;
1170
1171 u32 fladj;
1172 u32 irq_gadget;
1173 u32 otg_irq;
1174 u32 current_otg_role;
1175 u32 desired_otg_role;
1176 bool otg_restart_host;
1177 u32 nr_scratch;
1178 u32 u1u2;
1179 u32 maximum_speed;
1180 u32 gadget_max_speed;
1181 enum usb_ssp_rate max_ssp_rate;
1182 enum usb_ssp_rate gadget_ssp_rate;
1183
1184 u32 ip;
1185
1186 #define DWC3_IP 0x5533
1187 #define DWC31_IP 0x3331
1188 #define DWC32_IP 0x3332
1189
1190 u32 revision;
1191
1192 #define DWC3_REVISION_ANY 0x0
1193 #define DWC3_REVISION_173A 0x5533173a
1194 #define DWC3_REVISION_175A 0x5533175a
1195 #define DWC3_REVISION_180A 0x5533180a
1196 #define DWC3_REVISION_183A 0x5533183a
1197 #define DWC3_REVISION_185A 0x5533185a
1198 #define DWC3_REVISION_187A 0x5533187a
1199 #define DWC3_REVISION_188A 0x5533188a
1200 #define DWC3_REVISION_190A 0x5533190a
1201 #define DWC3_REVISION_194A 0x5533194a
1202 #define DWC3_REVISION_200A 0x5533200a
1203 #define DWC3_REVISION_202A 0x5533202a
1204 #define DWC3_REVISION_210A 0x5533210a
1205 #define DWC3_REVISION_220A 0x5533220a
1206 #define DWC3_REVISION_230A 0x5533230a
1207 #define DWC3_REVISION_240A 0x5533240a
1208 #define DWC3_REVISION_250A 0x5533250a
1209 #define DWC3_REVISION_260A 0x5533260a
1210 #define DWC3_REVISION_270A 0x5533270a
1211 #define DWC3_REVISION_280A 0x5533280a
1212 #define DWC3_REVISION_290A 0x5533290a
1213 #define DWC3_REVISION_300A 0x5533300a
1214 #define DWC3_REVISION_310A 0x5533310a
1215 #define DWC3_REVISION_330A 0x5533330a
1216
1217 #define DWC31_REVISION_ANY 0x0
1218 #define DWC31_REVISION_110A 0x3131302a
1219 #define DWC31_REVISION_120A 0x3132302a
1220 #define DWC31_REVISION_160A 0x3136302a
1221 #define DWC31_REVISION_170A 0x3137302a
1222 #define DWC31_REVISION_180A 0x3138302a
1223 #define DWC31_REVISION_190A 0x3139302a
1224
1225 #define DWC32_REVISION_ANY 0x0
1226 #define DWC32_REVISION_100A 0x3130302a
1227
1228 u32 version_type;
1229
1230 #define DWC31_VERSIONTYPE_ANY 0x0
1231 #define DWC31_VERSIONTYPE_EA01 0x65613031
1232 #define DWC31_VERSIONTYPE_EA02 0x65613032
1233 #define DWC31_VERSIONTYPE_EA03 0x65613033
1234 #define DWC31_VERSIONTYPE_EA04 0x65613034
1235 #define DWC31_VERSIONTYPE_EA05 0x65613035
1236 #define DWC31_VERSIONTYPE_EA06 0x65613036
1237
1238 enum dwc3_ep0_next ep0_next_event;
1239 enum dwc3_ep0_state ep0state;
1240 enum dwc3_link_state link_state;
1241
1242 u16 u2sel;
1243 u16 u2pel;
1244 u8 u1sel;
1245 u8 u1pel;
1246
1247 u8 speed;
1248
1249 u8 num_eps;
1250
1251 struct dwc3_hwparams hwparams;
1252 struct debugfs_regset32 *regset;
1253
1254 u32 dbg_lsp_select;
1255
1256 u8 test_mode;
1257 u8 test_mode_nr;
1258 u8 lpm_nyet_threshold;
1259 u8 hird_threshold;
1260 u8 rx_thr_num_pkt_prd;
1261 u8 rx_max_burst_prd;
1262 u8 tx_thr_num_pkt_prd;
1263 u8 tx_max_burst_prd;
1264 u8 tx_fifo_resize_max_num;
1265
1266 const char *hsphy_interface;
1267
1268 unsigned connected:1;
1269 unsigned softconnect:1;
1270 unsigned delayed_status:1;
1271 unsigned ep0_bounced:1;
1272 unsigned ep0_expect_in:1;
1273 unsigned has_hibernation:1;
1274 unsigned sysdev_is_parent:1;
1275 unsigned has_lpm_erratum:1;
1276 unsigned is_utmi_l1_suspend:1;
1277 unsigned is_fpga:1;
1278 unsigned pending_events:1;
1279 unsigned do_fifo_resize:1;
1280 unsigned pullups_connected:1;
1281 unsigned setup_packet_pending:1;
1282 unsigned three_stage_setup:1;
1283 unsigned dis_start_transfer_quirk:1;
1284 unsigned usb3_lpm_capable:1;
1285 unsigned usb2_lpm_disable:1;
1286 unsigned usb2_gadget_lpm_disable:1;
1287
1288 unsigned disable_scramble_quirk:1;
1289 unsigned u2exit_lfps_quirk:1;
1290 unsigned u2ss_inp3_quirk:1;
1291 unsigned req_p1p2p3_quirk:1;
1292 unsigned del_p1p2p3_quirk:1;
1293 unsigned del_phy_power_chg_quirk:1;
1294 unsigned lfps_filter_quirk:1;
1295 unsigned rx_detect_poll_quirk:1;
1296 unsigned dis_u3_susphy_quirk:1;
1297 unsigned dis_u2_susphy_quirk:1;
1298 unsigned dis_enblslpm_quirk:1;
1299 unsigned dis_u1_entry_quirk:1;
1300 unsigned dis_u2_entry_quirk:1;
1301 unsigned dis_rxdet_inp3_quirk:1;
1302 unsigned dis_u2_freeclk_exists_quirk:1;
1303 unsigned dis_del_phy_power_chg_quirk:1;
1304 unsigned dis_tx_ipgap_linecheck_quirk:1;
1305 unsigned parkmode_disable_ss_quirk:1;
1306
1307 unsigned tx_de_emphasis_quirk:1;
1308 unsigned tx_de_emphasis:2;
1309
1310 unsigned dis_metastability_quirk:1;
1311
1312 unsigned dis_split_quirk:1;
1313 unsigned async_callbacks:1;
1314
1315 u16 imod_interval;
1316
1317 int max_cfg_eps;
1318 int last_fifo_depth;
1319 int num_ep_resized;
1320
1321 ANDROID_KABI_USE(1, struct{ u8 clear_stall_protocol; u8 padding1;
1322 u8 padding2; u8 padding3; u8 padding4; u8 padding5;
1323 u8 padding6; u8 padding7; });
1324 ANDROID_KABI_USE(2, struct dentry *debug_root);
1325 ANDROID_KABI_RESERVE(3);
1326 ANDROID_KABI_RESERVE(4);
1327 };
1328
1329 /**
1330 * struct dwc3_vendor - contains parameters without modifying the format of DWC3 core
1331 * @dwc: contains dwc3 core reference
1332 * @suspended: set to track suspend event due to U3/L2.
1333 */
1334 struct dwc3_vendor {
1335 struct dwc3 dwc;
1336 unsigned suspended:1;
1337 };
1338
1339 #define INCRX_BURST_MODE 0
1340 #define INCRX_UNDEF_LENGTH_BURST_MODE 1
1341
1342 #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
1343
1344 /* -------------------------------------------------------------------------- */
1345
1346 struct dwc3_event_type {
1347 u32 is_devspec:1;
1348 u32 type:7;
1349 u32 reserved8_31:24;
1350 } __packed;
1351
1352 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
1353 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
1354 #define DWC3_DEPEVT_XFERNOTREADY 0x03
1355 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
1356 #define DWC3_DEPEVT_STREAMEVT 0x06
1357 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
1358
1359 /**
1360 * struct dwc3_event_depevt - Device Endpoint Events
1361 * @one_bit: indicates this is an endpoint event (not used)
1362 * @endpoint_number: number of the endpoint
1363 * @endpoint_event: The event we have:
1364 * 0x00 - Reserved
1365 * 0x01 - XferComplete
1366 * 0x02 - XferInProgress
1367 * 0x03 - XferNotReady
1368 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1369 * 0x05 - Reserved
1370 * 0x06 - StreamEvt
1371 * 0x07 - EPCmdCmplt
1372 * @reserved11_10: Reserved, don't use.
1373 * @status: Indicates the status of the event. Refer to databook for
1374 * more information.
1375 * @parameters: Parameters of the current event. Refer to databook for
1376 * more information.
1377 */
1378 struct dwc3_event_depevt {
1379 u32 one_bit:1;
1380 u32 endpoint_number:5;
1381 u32 endpoint_event:4;
1382 u32 reserved11_10:2;
1383 u32 status:4;
1384
1385 /* Within XferNotReady */
1386 #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3)
1387
1388 /* Within XferComplete or XferInProgress */
1389 #define DEPEVT_STATUS_BUSERR BIT(0)
1390 #define DEPEVT_STATUS_SHORT BIT(1)
1391 #define DEPEVT_STATUS_IOC BIT(2)
1392 #define DEPEVT_STATUS_LST BIT(3) /* XferComplete */
1393 #define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */
1394
1395 /* Stream event only */
1396 #define DEPEVT_STREAMEVT_FOUND 1
1397 #define DEPEVT_STREAMEVT_NOTFOUND 2
1398
1399 /* Stream event parameter */
1400 #define DEPEVT_STREAM_PRIME 0xfffe
1401 #define DEPEVT_STREAM_NOSTREAM 0x0
1402
1403 /* Control-only Status */
1404 #define DEPEVT_STATUS_CONTROL_DATA 1
1405 #define DEPEVT_STATUS_CONTROL_STATUS 2
1406 #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3)
1407
1408 /* In response to Start Transfer */
1409 #define DEPEVT_TRANSFER_NO_RESOURCE 1
1410 #define DEPEVT_TRANSFER_BUS_EXPIRY 2
1411
1412 u32 parameters:16;
1413
1414 /* For Command Complete Events */
1415 #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1416 } __packed;
1417
1418 /**
1419 * struct dwc3_event_devt - Device Events
1420 * @one_bit: indicates this is a non-endpoint event (not used)
1421 * @device_event: indicates it's a device event. Should read as 0x00
1422 * @type: indicates the type of device event.
1423 * 0 - DisconnEvt
1424 * 1 - USBRst
1425 * 2 - ConnectDone
1426 * 3 - ULStChng
1427 * 4 - WkUpEvt
1428 * 5 - Reserved
1429 * 6 - Suspend (EOPF on revisions 2.10a and prior)
1430 * 7 - SOF
1431 * 8 - Reserved
1432 * 9 - ErrticErr
1433 * 10 - CmdCmplt
1434 * 11 - EvntOverflow
1435 * 12 - VndrDevTstRcved
1436 * @reserved15_12: Reserved, not used
1437 * @event_info: Information about this event
1438 * @reserved31_25: Reserved, not used
1439 */
1440 struct dwc3_event_devt {
1441 u32 one_bit:1;
1442 u32 device_event:7;
1443 u32 type:4;
1444 u32 reserved15_12:4;
1445 u32 event_info:9;
1446 u32 reserved31_25:7;
1447 } __packed;
1448
1449 /**
1450 * struct dwc3_event_gevt - Other Core Events
1451 * @one_bit: indicates this is a non-endpoint event (not used)
1452 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1453 * @phy_port_number: self-explanatory
1454 * @reserved31_12: Reserved, not used.
1455 */
1456 struct dwc3_event_gevt {
1457 u32 one_bit:1;
1458 u32 device_event:7;
1459 u32 phy_port_number:4;
1460 u32 reserved31_12:20;
1461 } __packed;
1462
1463 /**
1464 * union dwc3_event - representation of Event Buffer contents
1465 * @raw: raw 32-bit event
1466 * @type: the type of the event
1467 * @depevt: Device Endpoint Event
1468 * @devt: Device Event
1469 * @gevt: Global Event
1470 */
1471 union dwc3_event {
1472 u32 raw;
1473 struct dwc3_event_type type;
1474 struct dwc3_event_depevt depevt;
1475 struct dwc3_event_devt devt;
1476 struct dwc3_event_gevt gevt;
1477 };
1478
1479 /**
1480 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1481 * parameters
1482 * @param2: third parameter
1483 * @param1: second parameter
1484 * @param0: first parameter
1485 */
1486 struct dwc3_gadget_ep_cmd_params {
1487 u32 param2;
1488 u32 param1;
1489 u32 param0;
1490 };
1491
1492 /*
1493 * DWC3 Features to be used as Driver Data
1494 */
1495
1496 #define DWC3_HAS_PERIPHERAL BIT(0)
1497 #define DWC3_HAS_XHCI BIT(1)
1498 #define DWC3_HAS_OTG BIT(3)
1499
1500 /* prototypes */
1501 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode);
1502 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1503 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1504
1505 #define DWC3_IP_IS(_ip) \
1506 (dwc->ip == _ip##_IP)
1507
1508 #define DWC3_VER_IS(_ip, _ver) \
1509 (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver)
1510
1511 #define DWC3_VER_IS_PRIOR(_ip, _ver) \
1512 (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver)
1513
1514 #define DWC3_VER_IS_WITHIN(_ip, _from, _to) \
1515 (DWC3_IP_IS(_ip) && \
1516 dwc->revision >= _ip##_REVISION_##_from && \
1517 (!(_ip##_REVISION_##_to) || \
1518 dwc->revision <= _ip##_REVISION_##_to))
1519
1520 #define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) \
1521 (DWC3_VER_IS(_ip, _ver) && \
1522 dwc->version_type >= _ip##_VERSIONTYPE_##_from && \
1523 (!(_ip##_VERSIONTYPE_##_to) || \
1524 dwc->version_type <= _ip##_VERSIONTYPE_##_to))
1525
1526 /**
1527 * dwc3_mdwidth - get MDWIDTH value in bits
1528 * @dwc: pointer to our context structure
1529 *
1530 * Return MDWIDTH configuration value in bits.
1531 */
dwc3_mdwidth(struct dwc3 * dwc)1532 static inline u32 dwc3_mdwidth(struct dwc3 *dwc)
1533 {
1534 u32 mdwidth;
1535
1536 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1537 if (DWC3_IP_IS(DWC32))
1538 mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
1539
1540 return mdwidth;
1541 }
1542
1543 bool dwc3_has_imod(struct dwc3 *dwc);
1544
1545 int dwc3_event_buffers_setup(struct dwc3 *dwc);
1546 void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1547
1548 int dwc3_core_soft_reset(struct dwc3 *dwc);
1549
1550 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1551 int dwc3_host_init(struct dwc3 *dwc);
1552 void dwc3_host_exit(struct dwc3 *dwc);
1553 #else
dwc3_host_init(struct dwc3 * dwc)1554 static inline int dwc3_host_init(struct dwc3 *dwc)
1555 { return 0; }
dwc3_host_exit(struct dwc3 * dwc)1556 static inline void dwc3_host_exit(struct dwc3 *dwc)
1557 { }
1558 #endif
1559
1560 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1561 int dwc3_gadget_init(struct dwc3 *dwc);
1562 void dwc3_gadget_exit(struct dwc3 *dwc);
1563 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1564 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1565 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1566 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
1567 struct dwc3_gadget_ep_cmd_params *params);
1568 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
1569 u32 param);
1570 void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc);
1571 void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status);
1572 #else
dwc3_gadget_init(struct dwc3 * dwc)1573 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1574 { return 0; }
dwc3_gadget_exit(struct dwc3 * dwc)1575 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1576 { }
dwc3_gadget_set_test_mode(struct dwc3 * dwc,int mode)1577 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1578 { return 0; }
dwc3_gadget_get_link_state(struct dwc3 * dwc)1579 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1580 { return 0; }
dwc3_gadget_set_link_state(struct dwc3 * dwc,enum dwc3_link_state state)1581 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1582 enum dwc3_link_state state)
1583 { return 0; }
1584
dwc3_send_gadget_ep_cmd(struct dwc3_ep * dep,unsigned int cmd,struct dwc3_gadget_ep_cmd_params * params)1585 static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
1586 struct dwc3_gadget_ep_cmd_params *params)
1587 { return 0; }
dwc3_send_gadget_generic_command(struct dwc3 * dwc,int cmd,u32 param)1588 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1589 int cmd, u32 param)
1590 { return 0; }
dwc3_gadget_clear_tx_fifos(struct dwc3 * dwc)1591 static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
1592 { }
1593 #endif
1594
1595 #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1596 int dwc3_drd_init(struct dwc3 *dwc);
1597 void dwc3_drd_exit(struct dwc3 *dwc);
1598 void dwc3_otg_init(struct dwc3 *dwc);
1599 void dwc3_otg_exit(struct dwc3 *dwc);
1600 void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus);
1601 void dwc3_otg_host_init(struct dwc3 *dwc);
1602 #else
dwc3_drd_init(struct dwc3 * dwc)1603 static inline int dwc3_drd_init(struct dwc3 *dwc)
1604 { return 0; }
dwc3_drd_exit(struct dwc3 * dwc)1605 static inline void dwc3_drd_exit(struct dwc3 *dwc)
1606 { }
dwc3_otg_init(struct dwc3 * dwc)1607 static inline void dwc3_otg_init(struct dwc3 *dwc)
1608 { }
dwc3_otg_exit(struct dwc3 * dwc)1609 static inline void dwc3_otg_exit(struct dwc3 *dwc)
1610 { }
dwc3_otg_update(struct dwc3 * dwc,bool ignore_idstatus)1611 static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
1612 { }
dwc3_otg_host_init(struct dwc3 * dwc)1613 static inline void dwc3_otg_host_init(struct dwc3 *dwc)
1614 { }
1615 #endif
1616
1617 /* power management interface */
1618 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1619 int dwc3_gadget_suspend(struct dwc3 *dwc);
1620 int dwc3_gadget_resume(struct dwc3 *dwc);
1621 void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
1622 #else
dwc3_gadget_suspend(struct dwc3 * dwc)1623 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1624 {
1625 return 0;
1626 }
1627
dwc3_gadget_resume(struct dwc3 * dwc)1628 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1629 {
1630 return 0;
1631 }
1632
dwc3_gadget_process_pending_events(struct dwc3 * dwc)1633 static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1634 {
1635 }
1636 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1637
1638 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1639 int dwc3_ulpi_init(struct dwc3 *dwc);
1640 void dwc3_ulpi_exit(struct dwc3 *dwc);
1641 #else
dwc3_ulpi_init(struct dwc3 * dwc)1642 static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1643 { return 0; }
dwc3_ulpi_exit(struct dwc3 * dwc)1644 static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1645 { }
1646 #endif
1647
1648 #endif /* __DRIVERS_USB_DWC3_CORE_H */
1649