1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
3
4 #ifndef _I40E_H_
5 #define _I40E_H_
6
7 #include <net/tcp.h>
8 #include <net/udp.h>
9 #include <linux/types.h>
10 #include <linux/errno.h>
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/aer.h>
14 #include <linux/netdevice.h>
15 #include <linux/ioport.h>
16 #include <linux/iommu.h>
17 #include <linux/slab.h>
18 #include <linux/list.h>
19 #include <linux/hashtable.h>
20 #include <linux/string.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/sctp.h>
24 #include <linux/pkt_sched.h>
25 #include <linux/ipv6.h>
26 #include <net/checksum.h>
27 #include <net/ip6_checksum.h>
28 #include <linux/ethtool.h>
29 #include <linux/if_vlan.h>
30 #include <linux/if_macvlan.h>
31 #include <linux/if_bridge.h>
32 #include <linux/clocksource.h>
33 #include <linux/net_tstamp.h>
34 #include <linux/ptp_clock_kernel.h>
35 #include <net/pkt_cls.h>
36 #include <net/tc_act/tc_gact.h>
37 #include <net/tc_act/tc_mirred.h>
38 #include <net/udp_tunnel.h>
39 #include <net/xdp_sock.h>
40 #include <linux/bitfield.h>
41 #include "i40e_type.h"
42 #include "i40e_prototype.h"
43 #include <linux/net/intel/i40e_client.h>
44 #include <linux/avf/virtchnl.h>
45 #include "i40e_virtchnl_pf.h"
46 #include "i40e_txrx.h"
47 #include "i40e_dcb.h"
48
49 /* Useful i40e defaults */
50 #define I40E_MAX_VEB 16
51
52 #define I40E_MAX_NUM_DESCRIPTORS 4096
53 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
54 #define I40E_DEFAULT_NUM_DESCRIPTORS 512
55 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32
56 #define I40E_MIN_NUM_DESCRIPTORS 64
57 #define I40E_MIN_MSIX 2
58 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
59 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */
60 /* max 16 qps */
61 #define i40e_default_queues_per_vmdq(pf) \
62 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
63 #define I40E_DEFAULT_QUEUES_PER_VF 4
64 #define I40E_MAX_VF_QUEUES 16
65 #define i40e_pf_get_max_q_per_tc(pf) \
66 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
67 #define I40E_FDIR_RING_COUNT 32
68 #define I40E_MAX_AQ_BUF_SIZE 4096
69 #define I40E_AQ_LEN 256
70 #define I40E_MIN_ARQ_LEN 1
71 #define I40E_MIN_ASQ_LEN 2
72 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
73 #define I40E_MAX_USER_PRIORITY 8
74 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0)
75 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10
76 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
77
78 #define I40E_NVM_VERSION_LO_SHIFT 0
79 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
80 #define I40E_NVM_VERSION_HI_SHIFT 12
81 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
82 #define I40E_OEM_VER_BUILD_MASK 0xffff
83 #define I40E_OEM_VER_PATCH_MASK 0xff
84 #define I40E_OEM_VER_BUILD_SHIFT 8
85 #define I40E_OEM_VER_SHIFT 24
86 #define I40E_PHY_DEBUG_ALL \
87 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
88 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
89
90 #define I40E_OEM_EETRACK_ID 0xffffffff
91 #define I40E_OEM_GEN_SHIFT 24
92 #define I40E_OEM_SNAP_MASK 0x00ff0000
93 #define I40E_OEM_SNAP_SHIFT 16
94 #define I40E_OEM_RELEASE_MASK 0x0000ffff
95
96 #define I40E_RX_DESC(R, i) \
97 (&(((union i40e_rx_desc *)((R)->desc))[i]))
98 #define I40E_TX_DESC(R, i) \
99 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
100 #define I40E_TX_CTXTDESC(R, i) \
101 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
102 #define I40E_TX_FDIRDESC(R, i) \
103 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
104
105 /* BW rate limiting */
106 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */
107 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */
108 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */
109
110 /* driver state flags */
111 enum i40e_state_t {
112 __I40E_TESTING,
113 __I40E_CONFIG_BUSY,
114 __I40E_CONFIG_DONE,
115 __I40E_DOWN,
116 __I40E_SERVICE_SCHED,
117 __I40E_ADMINQ_EVENT_PENDING,
118 __I40E_MDD_EVENT_PENDING,
119 __I40E_VFLR_EVENT_PENDING,
120 __I40E_RESET_RECOVERY_PENDING,
121 __I40E_TIMEOUT_RECOVERY_PENDING,
122 __I40E_MISC_IRQ_REQUESTED,
123 __I40E_RESET_INTR_RECEIVED,
124 __I40E_REINIT_REQUESTED,
125 __I40E_PF_RESET_REQUESTED,
126 __I40E_PF_RESET_AND_REBUILD_REQUESTED,
127 __I40E_CORE_RESET_REQUESTED,
128 __I40E_GLOBAL_RESET_REQUESTED,
129 __I40E_EMP_RESET_INTR_RECEIVED,
130 __I40E_SUSPENDED,
131 __I40E_PTP_TX_IN_PROGRESS,
132 __I40E_BAD_EEPROM,
133 __I40E_DOWN_REQUESTED,
134 __I40E_FD_FLUSH_REQUESTED,
135 __I40E_FD_ATR_AUTO_DISABLED,
136 __I40E_FD_SB_AUTO_DISABLED,
137 __I40E_RESET_FAILED,
138 __I40E_PORT_SUSPENDED,
139 __I40E_VF_DISABLE,
140 __I40E_MACVLAN_SYNC_PENDING,
141 __I40E_TEMP_LINK_POLLING,
142 __I40E_CLIENT_SERVICE_REQUESTED,
143 __I40E_CLIENT_L2_CHANGE,
144 __I40E_CLIENT_RESET,
145 __I40E_VIRTCHNL_OP_PENDING,
146 __I40E_RECOVERY_MODE,
147 __I40E_VF_RESETS_DISABLED, /* disable resets during i40e_remove */
148 __I40E_IN_REMOVE,
149 __I40E_VFS_RELEASING,
150 /* This must be last as it determines the size of the BITMAP */
151 __I40E_STATE_SIZE__,
152 };
153
154 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED)
155 #define I40E_PF_RESET_AND_REBUILD_FLAG \
156 BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED)
157
158 /* VSI state flags */
159 enum i40e_vsi_state_t {
160 __I40E_VSI_DOWN,
161 __I40E_VSI_NEEDS_RESTART,
162 __I40E_VSI_SYNCING_FILTERS,
163 __I40E_VSI_OVERFLOW_PROMISC,
164 __I40E_VSI_REINIT_REQUESTED,
165 __I40E_VSI_DOWN_REQUESTED,
166 __I40E_VSI_RELEASING,
167 /* This must be last as it determines the size of the BITMAP */
168 __I40E_VSI_STATE_SIZE__,
169 };
170
171 enum i40e_interrupt_policy {
172 I40E_INTERRUPT_BEST_CASE,
173 I40E_INTERRUPT_MEDIUM,
174 I40E_INTERRUPT_LOWEST
175 };
176
177 struct i40e_lump_tracking {
178 u16 num_entries;
179 u16 list[0];
180 #define I40E_PILE_VALID_BIT 0x8000
181 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
182 };
183
184 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20
185 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
186 #define I40E_FDIR_BUFFER_FULL_MARGIN 10
187 #define I40E_FDIR_BUFFER_HEAD_ROOM 32
188 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
189
190 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
191 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
192 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
193
194 enum i40e_fd_stat_idx {
195 I40E_FD_STAT_ATR,
196 I40E_FD_STAT_SB,
197 I40E_FD_STAT_ATR_TUNNEL,
198 I40E_FD_STAT_PF_COUNT
199 };
200 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
201 #define I40E_FD_ATR_STAT_IDX(pf_id) \
202 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
203 #define I40E_FD_SB_STAT_IDX(pf_id) \
204 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
205 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
206 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
207
208 /* The following structure contains the data parsed from the user-defined
209 * field of the ethtool_rx_flow_spec structure.
210 */
211 struct i40e_rx_flow_userdef {
212 bool flex_filter;
213 u16 flex_word;
214 u16 flex_offset;
215 };
216
217 struct i40e_fdir_filter {
218 struct hlist_node fdir_node;
219 /* filter ipnut set */
220 u8 flow_type;
221 u8 ipl4_proto;
222 /* TX packet view of src and dst */
223 __be32 dst_ip;
224 __be32 src_ip;
225 __be32 dst_ip6[4];
226 __be32 src_ip6[4];
227 __be16 src_port;
228 __be16 dst_port;
229 __be32 sctp_v_tag;
230
231 __be16 vlan_etype;
232 __be16 vlan_tag;
233 /* Flexible data to match within the packet payload */
234 __be16 flex_word;
235 u16 flex_offset;
236 bool flex_filter;
237
238 /* filter control */
239 u16 q_index;
240 u8 flex_off;
241 u8 pctype;
242 u16 dest_vsi;
243 u8 dest_ctl;
244 u8 fd_status;
245 u16 cnt_index;
246 u32 fd_id;
247 };
248
249 #define I40E_CLOUD_FIELD_OMAC BIT(0)
250 #define I40E_CLOUD_FIELD_IMAC BIT(1)
251 #define I40E_CLOUD_FIELD_IVLAN BIT(2)
252 #define I40E_CLOUD_FIELD_TEN_ID BIT(3)
253 #define I40E_CLOUD_FIELD_IIP BIT(4)
254
255 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC
256 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC
257 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \
258 I40E_CLOUD_FIELD_IVLAN)
259 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
260 I40E_CLOUD_FIELD_TEN_ID)
261 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
262 I40E_CLOUD_FIELD_IMAC | \
263 I40E_CLOUD_FIELD_TEN_ID)
264 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
265 I40E_CLOUD_FIELD_IVLAN | \
266 I40E_CLOUD_FIELD_TEN_ID)
267 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP
268
269 struct i40e_cloud_filter {
270 struct hlist_node cloud_node;
271 unsigned long cookie;
272 /* cloud filter input set follows */
273 u8 dst_mac[ETH_ALEN];
274 u8 src_mac[ETH_ALEN];
275 __be16 vlan_id;
276 u16 seid; /* filter control */
277 __be16 dst_port;
278 __be16 src_port;
279 u32 tenant_id;
280 union {
281 struct {
282 struct in_addr dst_ip;
283 struct in_addr src_ip;
284 } v4;
285 struct {
286 struct in6_addr dst_ip6;
287 struct in6_addr src_ip6;
288 } v6;
289 } ip;
290 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32
291 #define src_ipv6 ip.v6.src_ip6.s6_addr32
292 #define dst_ipv4 ip.v4.dst_ip.s_addr
293 #define src_ipv4 ip.v4.src_ip.s_addr
294 u16 n_proto; /* Ethernet Protocol */
295 u8 ip_proto; /* IPPROTO value */
296 u8 flags;
297 #define I40E_CLOUD_TNL_TYPE_NONE 0xff
298 u8 tunnel_type;
299 };
300
301 #define I40E_DCB_PRIO_TYPE_STRICT 0
302 #define I40E_DCB_PRIO_TYPE_ETS 1
303 #define I40E_DCB_STRICT_PRIO_CREDITS 127
304 /* DCB per TC information data structure */
305 struct i40e_tc_info {
306 u16 qoffset; /* Queue offset from base queue */
307 u16 qcount; /* Total Queues */
308 u8 netdev_tc; /* Netdev TC index if netdev associated */
309 };
310
311 /* TC configuration data structure */
312 struct i40e_tc_configuration {
313 u8 numtc; /* Total number of enabled TCs */
314 u8 enabled_tc; /* TC map */
315 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
316 };
317
318 #define I40E_UDP_PORT_INDEX_UNUSED 255
319 struct i40e_udp_port_config {
320 /* AdminQ command interface expects port number in Host byte order */
321 u16 port;
322 u8 type;
323 u8 filter_index;
324 };
325
326 #define I40_DDP_FLASH_REGION 100
327 #define I40E_PROFILE_INFO_SIZE 48
328 #define I40E_MAX_PROFILE_NUM 16
329 #define I40E_PROFILE_LIST_SIZE \
330 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4)
331 #define I40E_DDP_PROFILE_PATH "intel/i40e/ddp/"
332 #define I40E_DDP_PROFILE_NAME_MAX 64
333
334 int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size,
335 bool is_add);
336 int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash);
337
338 struct i40e_ddp_profile_list {
339 u32 p_count;
340 struct i40e_profile_info p_info[];
341 };
342
343 struct i40e_ddp_old_profile_list {
344 struct list_head list;
345 size_t old_ddp_size;
346 u8 old_ddp_buf[];
347 };
348
349 /* macros related to FLX_PIT */
350 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
351 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
352 I40E_PRTQF_FLX_PIT_FSIZE_MASK)
353 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
354 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
355 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
356 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
357 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
358 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
359 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
360 I40E_FLEX_SET_FSIZE(fsize) | \
361 I40E_FLEX_SET_SRC_WORD(src))
362
363
364 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F
365
366 /* macros related to GLQF_ORT */
367 #define I40E_ORT_SET_IDX(idx) (((idx) << \
368 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
369 I40E_GLQF_ORT_PIT_INDX_MASK)
370
371 #define I40E_ORT_SET_COUNT(count) (((count) << \
372 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
373 I40E_GLQF_ORT_FIELD_CNT_MASK)
374
375 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \
376 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
377 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
378
379 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
380 I40E_ORT_SET_COUNT(count) | \
381 I40E_ORT_SET_PAYLOAD(payload))
382
383 #define I40E_L3_GLQF_ORT_IDX 34
384 #define I40E_L4_GLQF_ORT_IDX 35
385
386 /* Flex PIT register index */
387 #define I40E_FLEX_PIT_IDX_START_L3 3
388 #define I40E_FLEX_PIT_IDX_START_L4 6
389
390 #define I40E_FLEX_PIT_TABLE_SIZE 3
391
392 #define I40E_FLEX_DEST_UNUSED 63
393
394 #define I40E_FLEX_INDEX_ENTRIES 8
395
396 /* Flex MASK to disable all flexible entries */
397 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
398 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
399 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
400 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
401
402 struct i40e_flex_pit {
403 struct list_head list;
404 u16 src_offset;
405 u8 pit_index;
406 };
407
408 struct i40e_fwd_adapter {
409 struct net_device *netdev;
410 int bit_no;
411 };
412
413 struct i40e_channel {
414 struct list_head list;
415 bool initialized;
416 u8 type;
417 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */
418 u16 stat_counter_idx;
419 u16 base_queue;
420 u16 num_queue_pairs; /* Requested by user */
421 u16 seid;
422
423 u8 enabled_tc;
424 struct i40e_aqc_vsi_properties_data info;
425
426 u64 max_tx_rate;
427 struct i40e_fwd_adapter *fwd;
428
429 /* track this channel belongs to which VSI */
430 struct i40e_vsi *parent_vsi;
431 };
432
433 struct i40e_ptp_pins_settings;
434
i40e_is_channel_macvlan(struct i40e_channel * ch)435 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch)
436 {
437 return !!ch->fwd;
438 }
439
i40e_channel_mac(struct i40e_channel * ch)440 static inline const u8 *i40e_channel_mac(struct i40e_channel *ch)
441 {
442 if (i40e_is_channel_macvlan(ch))
443 return ch->fwd->netdev->dev_addr;
444 else
445 return NULL;
446 }
447
448 /* struct that defines the Ethernet device */
449 struct i40e_pf {
450 struct pci_dev *pdev;
451 struct i40e_hw hw;
452 DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
453 struct msix_entry *msix_entries;
454 bool fc_autoneg_status;
455
456 u16 eeprom_version;
457 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
458 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
459 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
460 u16 num_req_vfs; /* num VFs requested for this PF */
461 u16 num_vf_qps; /* num queue pairs per VF */
462 u16 num_lan_qps; /* num lan queues this PF has set up */
463 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
464 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */
465 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
466 int iwarp_base_vector;
467 int queues_left; /* queues left unclaimed */
468 u16 alloc_rss_size; /* allocated RSS queues */
469 u16 rss_size_max; /* HW defined max RSS queues */
470 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
471 u16 num_alloc_vsi; /* num VSIs this driver supports */
472 u8 atr_sample_rate;
473 bool wol_en;
474
475 struct hlist_head fdir_filter_list;
476 u16 fdir_pf_active_filters;
477 unsigned long fd_flush_timestamp;
478 u32 fd_flush_cnt;
479 u32 fd_add_err;
480 u32 fd_atr_cnt;
481
482 /* Book-keeping of side-band filter count per flow-type.
483 * This is used to detect and handle input set changes for
484 * respective flow-type.
485 */
486 u16 fd_tcp4_filter_cnt;
487 u16 fd_udp4_filter_cnt;
488 u16 fd_sctp4_filter_cnt;
489 u16 fd_ip4_filter_cnt;
490
491 u16 fd_tcp6_filter_cnt;
492 u16 fd_udp6_filter_cnt;
493 u16 fd_sctp6_filter_cnt;
494 u16 fd_ip6_filter_cnt;
495
496 /* Flexible filter table values that need to be programmed into
497 * hardware, which expects L3 and L4 to be programmed separately. We
498 * need to ensure that the values are in ascended order and don't have
499 * duplicates, so we track each L3 and L4 values in separate lists.
500 */
501 struct list_head l3_flex_pit_list;
502 struct list_head l4_flex_pit_list;
503
504 struct udp_tunnel_nic_shared udp_tunnel_shared;
505 struct udp_tunnel_nic_info udp_tunnel_nic;
506
507 struct hlist_head cloud_filter_list;
508 u16 num_cloud_filters;
509
510 enum i40e_interrupt_policy int_policy;
511 u16 rx_itr_default;
512 u16 tx_itr_default;
513 u32 msg_enable;
514 char int_name[I40E_INT_NAME_STR_LEN];
515 u16 adminq_work_limit; /* num of admin receive queue desc to process */
516 unsigned long service_timer_period;
517 unsigned long service_timer_previous;
518 struct timer_list service_timer;
519 struct work_struct service_task;
520
521 u32 hw_features;
522 #define I40E_HW_RSS_AQ_CAPABLE BIT(0)
523 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1)
524 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2)
525 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3)
526 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4)
527 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5)
528 #define I40E_HW_100M_SGMII_CAPABLE BIT(6)
529 #define I40E_HW_NO_DCB_SUPPORT BIT(7)
530 #define I40E_HW_USE_SET_LLDP_MIB BIT(8)
531 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9)
532 #define I40E_HW_PTP_L4_CAPABLE BIT(10)
533 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11)
534 #define I40E_HW_HAVE_CRT_RETIMER BIT(13)
535 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14)
536 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15)
537 #define I40E_HW_STOP_FW_LLDP BIT(16)
538 #define I40E_HW_PORT_ID_VALID BIT(17)
539 #define I40E_HW_RESTART_AUTONEG BIT(18)
540
541 u32 flags;
542 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0)
543 #define I40E_FLAG_MSI_ENABLED BIT(1)
544 #define I40E_FLAG_MSIX_ENABLED BIT(2)
545 #define I40E_FLAG_RSS_ENABLED BIT(3)
546 #define I40E_FLAG_VMDQ_ENABLED BIT(4)
547 #define I40E_FLAG_SRIOV_ENABLED BIT(5)
548 #define I40E_FLAG_DCB_CAPABLE BIT(6)
549 #define I40E_FLAG_DCB_ENABLED BIT(7)
550 #define I40E_FLAG_FD_SB_ENABLED BIT(8)
551 #define I40E_FLAG_FD_ATR_ENABLED BIT(9)
552 #define I40E_FLAG_MFP_ENABLED BIT(10)
553 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11)
554 #define I40E_FLAG_VEB_MODE_ENABLED BIT(12)
555 #define I40E_FLAG_VEB_STATS_ENABLED BIT(13)
556 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14)
557 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15)
558 #define I40E_FLAG_LEGACY_RX BIT(16)
559 #define I40E_FLAG_PTP BIT(17)
560 #define I40E_FLAG_IWARP_ENABLED BIT(18)
561 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19)
562 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20)
563 #define I40E_FLAG_TC_MQPRIO BIT(21)
564 #define I40E_FLAG_FD_SB_INACTIVE BIT(22)
565 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23)
566 #define I40E_FLAG_DISABLE_FW_LLDP BIT(24)
567 #define I40E_FLAG_RS_FEC BIT(25)
568 #define I40E_FLAG_BASE_R_FEC BIT(26)
569 /* TOTAL_PORT_SHUTDOWN
570 * Allows to physically disable the link on the NIC's port.
571 * If enabled, (after link down request from the OS)
572 * no link, traffic or led activity is possible on that port.
573 *
574 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED is set, the
575 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED must be explicitly forced to true
576 * and cannot be disabled by system admin at that time.
577 * The functionalities are exclusive in terms of configuration, but they also
578 * have similar behavior (allowing to disable physical link of the port),
579 * with following differences:
580 * - LINK_DOWN_ON_CLOSE_ENABLED is configurable at host OS run-time and is
581 * supported by whole family of 7xx Intel Ethernet Controllers
582 * - TOTAL_PORT_SHUTDOWN may be enabled only before OS loads (in BIOS)
583 * only if motherboard's BIOS and NIC's FW has support of it
584 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought down
585 * by sending phy_type=0 to NIC's FW
586 * - when TOTAL_PORT_SHUTDOWN is used, phy_type is not altered, instead
587 * the link is being brought down by clearing bit (I40E_AQ_PHY_ENABLE_LINK)
588 * in abilities field of i40e_aq_set_phy_config structure
589 */
590 #define I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED BIT(27)
591 #define I40E_FLAG_VF_VLAN_PRUNING BIT(28)
592
593 struct i40e_client_instance *cinst;
594 bool stat_offsets_loaded;
595 struct i40e_hw_port_stats stats;
596 struct i40e_hw_port_stats stats_offsets;
597 u32 tx_timeout_count;
598 u32 tx_timeout_recovery_level;
599 unsigned long tx_timeout_last_recovery;
600 u32 tx_sluggish_count;
601 u32 hw_csum_rx_error;
602 u32 led_status;
603 u16 corer_count; /* Core reset count */
604 u16 globr_count; /* Global reset count */
605 u16 empr_count; /* EMP reset count */
606 u16 pfr_count; /* PF reset count */
607 u16 sw_int_count; /* SW interrupt count */
608
609 struct mutex switch_mutex;
610 u16 lan_vsi; /* our default LAN VSI */
611 u16 lan_veb; /* initial relay, if exists */
612 #define I40E_NO_VEB 0xffff
613 #define I40E_NO_VSI 0xffff
614 u16 next_vsi; /* Next unallocated VSI - 0-based! */
615 struct i40e_vsi **vsi;
616 struct i40e_veb *veb[I40E_MAX_VEB];
617
618 struct i40e_lump_tracking *qp_pile;
619 struct i40e_lump_tracking *irq_pile;
620
621 /* switch config info */
622 u16 pf_seid;
623 u16 main_vsi_seid;
624 u16 mac_seid;
625 struct kobject *switch_kobj;
626 #ifdef CONFIG_DEBUG_FS
627 struct dentry *i40e_dbg_pf;
628 #endif /* CONFIG_DEBUG_FS */
629 bool cur_promisc;
630
631 u16 instance; /* A unique number per i40e_pf instance in the system */
632
633 /* sr-iov config info */
634 struct i40e_vf *vf;
635 int num_alloc_vfs; /* actual number of VFs allocated */
636 u32 vf_aq_requests;
637 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
638
639 /* DCBx/DCBNL capability for PF that indicates
640 * whether DCBx is managed by firmware or host
641 * based agent (LLDPAD). Also, indicates what
642 * flavor of DCBx protocol (IEEE/CEE) is supported
643 * by the device. For now we're supporting IEEE
644 * mode only.
645 */
646 u16 dcbx_cap;
647
648 struct i40e_filter_control_settings filter_settings;
649 struct i40e_rx_pb_config pb_cfg; /* Current Rx packet buffer config */
650 struct i40e_dcbx_config tmp_cfg;
651
652 /* GPIO defines used by PTP */
653 #define I40E_SDP3_2 18
654 #define I40E_SDP3_3 19
655 #define I40E_GPIO_4 20
656 #define I40E_LED2_0 26
657 #define I40E_LED2_1 27
658 #define I40E_LED3_0 28
659 #define I40E_LED3_1 29
660 #define I40E_GLGEN_GPIO_SET_SDP_DATA_HI \
661 (1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)
662 #define I40E_GLGEN_GPIO_SET_DRV_SDP_DATA \
663 (1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)
664 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_0 \
665 (0 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
666 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_1 \
667 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
668 #define I40E_GLGEN_GPIO_CTL_RESERVED BIT(2)
669 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z \
670 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)
671 #define I40E_GLGEN_GPIO_CTL_DIR_OUT \
672 (1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT)
673 #define I40E_GLGEN_GPIO_CTL_TRI_DRV_HI \
674 (1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT)
675 #define I40E_GLGEN_GPIO_CTL_OUT_HI_RST \
676 (1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT)
677 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_0 \
678 (3 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
679 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_1 \
680 (4 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
681 #define I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN \
682 (0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
683 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT \
684 (1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
685 #define I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0 \
686 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
687 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
688 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
689 #define I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0 \
690 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
691 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
692 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
693 #define I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1 \
694 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
695 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
696 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
697 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
698 #define I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1 \
699 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
700 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
701 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
702 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
703 #define I40E_GLGEN_GPIO_CTL_LED_INIT \
704 (I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z | \
705 I40E_GLGEN_GPIO_CTL_DIR_OUT | \
706 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | \
707 I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
708 I40E_GLGEN_GPIO_CTL_OUT_DEFAULT | \
709 I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN)
710 #define I40E_PRTTSYN_AUX_1_INSTNT \
711 (1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT)
712 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE \
713 (1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT)
714 #define I40E_PRTTSYN_AUX_0_OUT_CLK_MOD (3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT)
715 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD \
716 (I40E_PRTTSYN_AUX_0_OUT_ENABLE | I40E_PRTTSYN_AUX_0_OUT_CLK_MOD)
717 #define I40E_PTP_HALF_SECOND 500000000LL /* nano seconds */
718 #define I40E_PTP_2_SEC_DELAY 2
719
720 struct ptp_clock *ptp_clock;
721 struct ptp_clock_info ptp_caps;
722 struct sk_buff *ptp_tx_skb;
723 unsigned long ptp_tx_start;
724 struct hwtstamp_config tstamp_config;
725 struct timespec64 ptp_prev_hw_time;
726 struct work_struct ptp_pps_work;
727 struct work_struct ptp_extts0_work;
728 struct work_struct ptp_extts1_work;
729 ktime_t ptp_reset_start;
730 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
731 u32 ptp_adj_mult;
732 u32 tx_hwtstamp_timeouts;
733 u32 tx_hwtstamp_skipped;
734 u32 rx_hwtstamp_cleared;
735 u32 latch_event_flags;
736 u64 ptp_pps_start;
737 u32 pps_delay;
738 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
739 struct ptp_pin_desc ptp_pin[3];
740 unsigned long latch_events[4];
741 bool ptp_tx;
742 bool ptp_rx;
743 struct i40e_ptp_pins_settings *ptp_pins;
744 u16 rss_table_size; /* HW RSS table size */
745 u32 max_bw;
746 u32 min_bw;
747
748 u32 ioremap_len;
749 u32 fd_inv;
750 u16 phy_led_val;
751
752 u16 override_q_count;
753 u16 last_sw_conf_flags;
754 u16 last_sw_conf_valid_flags;
755 /* List to keep previous DDP profiles to be rolled back in the future */
756 struct list_head ddp_old_prof;
757 };
758
759 /**
760 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
761 * @macaddr: the MAC Address as the base key
762 *
763 * Simply copies the address and returns it as a u64 for hashing
764 **/
i40e_addr_to_hkey(const u8 * macaddr)765 static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
766 {
767 u64 key = 0;
768
769 ether_addr_copy((u8 *)&key, macaddr);
770 return key;
771 }
772
773 enum i40e_filter_state {
774 I40E_FILTER_INVALID = 0, /* Invalid state */
775 I40E_FILTER_NEW, /* New, not sent to FW yet */
776 I40E_FILTER_ACTIVE, /* Added to switch by FW */
777 I40E_FILTER_FAILED, /* Rejected by FW */
778 I40E_FILTER_REMOVE, /* To be removed */
779 /* There is no 'removed' state; the filter struct is freed */
780 };
781 struct i40e_mac_filter {
782 struct hlist_node hlist;
783 u8 macaddr[ETH_ALEN];
784 #define I40E_VLAN_ANY -1
785 s16 vlan;
786 enum i40e_filter_state state;
787 };
788
789 /* Wrapper structure to keep track of filters while we are preparing to send
790 * firmware commands. We cannot send firmware commands while holding a
791 * spinlock, since it might sleep. To avoid this, we wrap the added filters in
792 * a separate structure, which will track the state change and update the real
793 * filter while under lock. We can't simply hold the filters in a separate
794 * list, as this opens a window for a race condition when adding new MAC
795 * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
796 */
797 struct i40e_new_mac_filter {
798 struct hlist_node hlist;
799 struct i40e_mac_filter *f;
800
801 /* Track future changes to state separately */
802 enum i40e_filter_state state;
803 };
804
805 struct i40e_veb {
806 struct i40e_pf *pf;
807 u16 idx;
808 u16 veb_idx; /* index of VEB parent */
809 u16 seid;
810 u16 uplink_seid;
811 u16 stats_idx; /* index of VEB parent */
812 u8 enabled_tc;
813 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
814 u16 flags;
815 u16 bw_limit;
816 u8 bw_max_quanta;
817 bool is_abs_credits;
818 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
819 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
820 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
821 struct kobject *kobj;
822 bool stat_offsets_loaded;
823 struct i40e_eth_stats stats;
824 struct i40e_eth_stats stats_offsets;
825 struct i40e_veb_tc_stats tc_stats;
826 struct i40e_veb_tc_stats tc_stats_offsets;
827 };
828
829 /* struct that defines a VSI, associated with a dev */
830 struct i40e_vsi {
831 struct net_device *netdev;
832 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
833 bool netdev_registered;
834 bool stat_offsets_loaded;
835
836 u32 current_netdev_flags;
837 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
838 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
839 #define I40E_VSI_FLAG_VEB_OWNER BIT(1)
840 unsigned long flags;
841
842 /* Per VSI lock to protect elements/hash (MAC filter) */
843 spinlock_t mac_filter_hash_lock;
844 /* Fixed size hash table with 2^8 buckets for MAC filters */
845 DECLARE_HASHTABLE(mac_filter_hash, 8);
846 bool has_vlan_filter;
847
848 /* VSI stats */
849 struct rtnl_link_stats64 net_stats;
850 struct rtnl_link_stats64 net_stats_offsets;
851 struct i40e_eth_stats eth_stats;
852 struct i40e_eth_stats eth_stats_offsets;
853 u64 tx_restart;
854 u64 tx_busy;
855 u64 tx_linearize;
856 u64 tx_force_wb;
857 u64 rx_buf_failed;
858 u64 rx_page_failed;
859
860 /* These are containers of ring pointers, allocated at run-time */
861 struct i40e_ring **rx_rings;
862 struct i40e_ring **tx_rings;
863 struct i40e_ring **xdp_rings; /* XDP Tx rings */
864
865 u32 active_filters;
866 u32 promisc_threshold;
867
868 u16 work_limit;
869 u16 int_rate_limit; /* value in usecs */
870
871 u16 rss_table_size; /* HW RSS table size */
872 u16 rss_size; /* Allocated RSS queues */
873 u8 *rss_hkey_user; /* User configured hash keys */
874 u8 *rss_lut_user; /* User configured lookup table entries */
875
876
877 u16 max_frame;
878 u16 rx_buf_len;
879
880 struct bpf_prog *xdp_prog;
881
882 /* List of q_vectors allocated to this VSI */
883 struct i40e_q_vector **q_vectors;
884 int num_q_vectors;
885 int base_vector;
886 bool irqs_ready;
887
888 u16 seid; /* HW index of this VSI (absolute index) */
889 u16 id; /* VSI number */
890 u16 uplink_seid;
891
892 u16 base_queue; /* vsi's first queue in hw array */
893 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
894 u16 req_queue_pairs; /* User requested queue pairs */
895 u16 num_queue_pairs; /* Used tx and rx pairs */
896 u16 num_tx_desc;
897 u16 num_rx_desc;
898 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
899 s16 vf_id; /* Virtual function ID for SRIOV VSIs */
900
901 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
902 struct i40e_tc_configuration tc_config;
903 struct i40e_aqc_vsi_properties_data info;
904
905 /* VSI BW limit (absolute across all TCs) */
906 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
907 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
908
909 /* Relative TC credits across VSIs */
910 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
911 /* TC BW limit credits within VSI */
912 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
913 /* TC BW limit max quanta within VSI */
914 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
915
916 struct i40e_pf *back; /* Backreference to associated PF */
917 u16 idx; /* index in pf->vsi[] */
918 u16 veb_idx; /* index of VEB parent */
919 struct kobject *kobj; /* sysfs object */
920 bool current_isup; /* Sync 'link up' logging */
921 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */
922
923 /* channel specific fields */
924 u16 cnt_q_avail; /* num of queues available for channel usage */
925 u16 orig_rss_size;
926 u16 current_rss_size;
927 bool reconfig_rss;
928
929 u16 next_base_queue; /* next queue to be used for channel setup */
930
931 struct list_head ch_list;
932 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
933
934 /* macvlan fields */
935 #define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */
936 #define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */
937 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS);
938 struct list_head macvlan_list;
939 int macvlan_cnt;
940
941 void *priv; /* client driver data reference. */
942
943 /* VSI specific handlers */
944 irqreturn_t (*irq_handler)(int irq, void *data);
945
946 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */
947 } ____cacheline_internodealigned_in_smp;
948
949 struct i40e_netdev_priv {
950 struct i40e_vsi *vsi;
951 };
952
953 extern struct ida i40e_client_ida;
954
955 /* struct that defines an interrupt vector */
956 struct i40e_q_vector {
957 struct i40e_vsi *vsi;
958
959 u16 v_idx; /* index in the vsi->q_vector array. */
960 u16 reg_idx; /* register index of the interrupt */
961
962 struct napi_struct napi;
963
964 struct i40e_ring_container rx;
965 struct i40e_ring_container tx;
966
967 u8 itr_countdown; /* when 0 should adjust adaptive ITR */
968 u8 num_ringpairs; /* total number of ring pairs in vector */
969
970 cpumask_t affinity_mask;
971 struct irq_affinity_notify affinity_notify;
972
973 struct rcu_head rcu; /* to avoid race with update stats on free */
974 char name[I40E_INT_NAME_STR_LEN];
975 bool arm_wb_state;
976 } ____cacheline_internodealigned_in_smp;
977
978 /* lan device */
979 struct i40e_device {
980 struct list_head list;
981 struct i40e_pf *pf;
982 };
983
984 /**
985 * i40e_nvm_version_str - format the NVM version strings
986 * @hw: ptr to the hardware info
987 **/
i40e_nvm_version_str(struct i40e_hw * hw)988 static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
989 {
990 static char buf[32];
991 u32 full_ver;
992
993 full_ver = hw->nvm.oem_ver;
994
995 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) {
996 u8 gen, snap;
997 u16 release;
998
999 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT);
1000 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >>
1001 I40E_OEM_SNAP_SHIFT);
1002 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK);
1003
1004 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release);
1005 } else {
1006 u8 ver, patch;
1007 u16 build;
1008
1009 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
1010 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
1011 I40E_OEM_VER_BUILD_MASK);
1012 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
1013
1014 snprintf(buf, sizeof(buf),
1015 "%x.%02x 0x%x %d.%d.%d",
1016 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
1017 I40E_NVM_VERSION_HI_SHIFT,
1018 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
1019 I40E_NVM_VERSION_LO_SHIFT,
1020 hw->nvm.eetrack, ver, build, patch);
1021 }
1022
1023 return buf;
1024 }
1025
1026 /**
1027 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
1028 * @netdev: the corresponding netdev
1029 *
1030 * Return the PF struct for the given netdev
1031 **/
i40e_netdev_to_pf(struct net_device * netdev)1032 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
1033 {
1034 struct i40e_netdev_priv *np = netdev_priv(netdev);
1035 struct i40e_vsi *vsi = np->vsi;
1036
1037 return vsi->back;
1038 }
1039
i40e_vsi_setup_irqhandler(struct i40e_vsi * vsi,irqreturn_t (* irq_handler)(int,void *))1040 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
1041 irqreturn_t (*irq_handler)(int, void *))
1042 {
1043 vsi->irq_handler = irq_handler;
1044 }
1045
1046 /**
1047 * i40e_get_fd_cnt_all - get the total FD filter space available
1048 * @pf: pointer to the PF struct
1049 **/
i40e_get_fd_cnt_all(struct i40e_pf * pf)1050 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
1051 {
1052 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
1053 }
1054
1055 /**
1056 * i40e_read_fd_input_set - reads value of flow director input set register
1057 * @pf: pointer to the PF struct
1058 * @addr: register addr
1059 *
1060 * This function reads value of flow director input set register
1061 * specified by 'addr' (which is specific to flow-type)
1062 **/
i40e_read_fd_input_set(struct i40e_pf * pf,u16 addr)1063 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
1064 {
1065 u64 val;
1066
1067 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
1068 val <<= 32;
1069 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
1070
1071 return val;
1072 }
1073
1074 /**
1075 * i40e_write_fd_input_set - writes value into flow director input set register
1076 * @pf: pointer to the PF struct
1077 * @addr: register addr
1078 * @val: value to be written
1079 *
1080 * This function writes specified value to the register specified by 'addr'.
1081 * This register is input set register based on flow-type.
1082 **/
i40e_write_fd_input_set(struct i40e_pf * pf,u16 addr,u64 val)1083 static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
1084 u16 addr, u64 val)
1085 {
1086 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
1087 (u32)(val >> 32));
1088 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
1089 (u32)(val & 0xFFFFFFFFULL));
1090 }
1091
1092 /**
1093 * i40e_get_pf_count - get PCI PF count.
1094 * @hw: pointer to a hw.
1095 *
1096 * Reports the function number of the highest PCI physical
1097 * function plus 1 as it is loaded from the NVM.
1098 *
1099 * Return: PCI PF count.
1100 **/
i40e_get_pf_count(struct i40e_hw * hw)1101 static inline u32 i40e_get_pf_count(struct i40e_hw *hw)
1102 {
1103 return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK,
1104 rd32(hw, I40E_GLGEN_PCIFCNCNT));
1105 }
1106
1107 /* needed by i40e_ethtool.c */
1108 int i40e_up(struct i40e_vsi *vsi);
1109 void i40e_down(struct i40e_vsi *vsi);
1110 extern const char i40e_driver_name[];
1111 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
1112 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
1113 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1114 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1115 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
1116 u16 rss_table_size, u16 rss_size);
1117 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
1118 /**
1119 * i40e_find_vsi_by_type - Find and return Flow Director VSI
1120 * @pf: PF to search for VSI
1121 * @type: Value indicating type of VSI we are looking for
1122 **/
1123 static inline struct i40e_vsi *
i40e_find_vsi_by_type(struct i40e_pf * pf,u16 type)1124 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
1125 {
1126 int i;
1127
1128 for (i = 0; i < pf->num_alloc_vsi; i++) {
1129 struct i40e_vsi *vsi = pf->vsi[i];
1130
1131 if (vsi && vsi->type == type)
1132 return vsi;
1133 }
1134
1135 return NULL;
1136 }
1137 void i40e_update_stats(struct i40e_vsi *vsi);
1138 void i40e_update_veb_stats(struct i40e_veb *veb);
1139 void i40e_update_eth_stats(struct i40e_vsi *vsi);
1140 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
1141 int i40e_fetch_switch_configuration(struct i40e_pf *pf,
1142 bool printconfig);
1143
1144 int i40e_add_del_fdir(struct i40e_vsi *vsi,
1145 struct i40e_fdir_filter *input, bool add);
1146 void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
1147 u32 i40e_get_current_fd_count(struct i40e_pf *pf);
1148 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
1149 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
1150 u32 i40e_get_global_fd_count(struct i40e_pf *pf);
1151 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
1152 void i40e_set_ethtool_ops(struct net_device *netdev);
1153 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1154 const u8 *macaddr, s16 vlan);
1155 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
1156 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
1157 int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
1158 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
1159 u16 uplink, u32 param1);
1160 int i40e_vsi_release(struct i40e_vsi *vsi);
1161 void i40e_service_event_schedule(struct i40e_pf *pf);
1162 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
1163 u8 *msg, u16 len);
1164
1165 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp,
1166 bool enable);
1167 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable);
1168 int i40e_vsi_start_rings(struct i40e_vsi *vsi);
1169 void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
1170 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi);
1171 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
1172 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
1173 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1174 u16 downlink_seid, u8 enabled_tc);
1175 void i40e_veb_release(struct i40e_veb *veb);
1176
1177 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
1178 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
1179 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1180 void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1181 void i40e_pf_reset_stats(struct i40e_pf *pf);
1182 #ifdef CONFIG_DEBUG_FS
1183 void i40e_dbg_pf_init(struct i40e_pf *pf);
1184 void i40e_dbg_pf_exit(struct i40e_pf *pf);
1185 void i40e_dbg_init(void);
1186 void i40e_dbg_exit(void);
1187 #else
i40e_dbg_pf_init(struct i40e_pf * pf)1188 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
i40e_dbg_pf_exit(struct i40e_pf * pf)1189 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
i40e_dbg_init(void)1190 static inline void i40e_dbg_init(void) {}
i40e_dbg_exit(void)1191 static inline void i40e_dbg_exit(void) {}
1192 #endif /* CONFIG_DEBUG_FS*/
1193 /* needed by client drivers */
1194 int i40e_lan_add_device(struct i40e_pf *pf);
1195 int i40e_lan_del_device(struct i40e_pf *pf);
1196 void i40e_client_subtask(struct i40e_pf *pf);
1197 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
1198 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1199 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1200 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
1201 void i40e_client_update_msix_info(struct i40e_pf *pf);
1202 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
1203 /**
1204 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1205 * @vsi: pointer to a vsi
1206 * @vector: enable a particular Hw Interrupt vector, without base_vector
1207 **/
i40e_irq_dynamic_enable(struct i40e_vsi * vsi,int vector)1208 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1209 {
1210 struct i40e_pf *pf = vsi->back;
1211 struct i40e_hw *hw = &pf->hw;
1212 u32 val;
1213
1214 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1215 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1216 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1217 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1218 /* skip the flush */
1219 }
1220
1221 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
1222 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
1223 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
1224 int i40e_open(struct net_device *netdev);
1225 int i40e_close(struct net_device *netdev);
1226 int i40e_vsi_open(struct i40e_vsi *vsi);
1227 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
1228 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1229 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
1230 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1231 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
1232 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1233 const u8 *macaddr);
1234 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
1235 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
1236 int i40e_count_filters(struct i40e_vsi *vsi);
1237 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
1238 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
i40e_is_sw_dcb(struct i40e_pf * pf)1239 static inline bool i40e_is_sw_dcb(struct i40e_pf *pf)
1240 {
1241 return !!(pf->flags & I40E_FLAG_DISABLE_FW_LLDP);
1242 }
1243
1244 #ifdef CONFIG_I40E_DCB
1245 void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
1246 struct i40e_dcbx_config *old_cfg,
1247 struct i40e_dcbx_config *new_cfg);
1248 void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1249 void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1250 bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1251 struct i40e_dcbx_config *old_cfg,
1252 struct i40e_dcbx_config *new_cfg);
1253 int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg);
1254 int i40e_dcb_sw_default_config(struct i40e_pf *pf);
1255 #endif /* CONFIG_I40E_DCB */
1256 void i40e_ptp_rx_hang(struct i40e_pf *pf);
1257 void i40e_ptp_tx_hang(struct i40e_pf *pf);
1258 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1259 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1260 void i40e_ptp_set_increment(struct i40e_pf *pf);
1261 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1262 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1263 void i40e_ptp_save_hw_time(struct i40e_pf *pf);
1264 void i40e_ptp_restore_hw_time(struct i40e_pf *pf);
1265 void i40e_ptp_init(struct i40e_pf *pf);
1266 void i40e_ptp_stop(struct i40e_pf *pf);
1267 int i40e_ptp_alloc_pins(struct i40e_pf *pf);
1268 int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset);
1269 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
1270 int i40e_get_partition_bw_setting(struct i40e_pf *pf);
1271 int i40e_set_partition_bw_setting(struct i40e_pf *pf);
1272 int i40e_commit_partition_bw_setting(struct i40e_pf *pf);
1273 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
1274
1275 void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags);
1276
i40e_enabled_xdp_vsi(struct i40e_vsi * vsi)1277 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1278 {
1279 return !!READ_ONCE(vsi->xdp_prog);
1280 }
1281
1282 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
1283 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
1284 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
1285 struct i40e_cloud_filter *filter,
1286 bool add);
1287 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
1288 struct i40e_cloud_filter *filter,
1289 bool add);
1290
1291 /**
1292 * i40e_is_tc_mqprio_enabled - check if TC MQPRIO is enabled on PF
1293 * @pf: pointer to a pf.
1294 *
1295 * Check and return value of flag I40E_FLAG_TC_MQPRIO.
1296 *
1297 * Return: I40E_FLAG_TC_MQPRIO set state.
1298 **/
i40e_is_tc_mqprio_enabled(struct i40e_pf * pf)1299 static inline u32 i40e_is_tc_mqprio_enabled(struct i40e_pf *pf)
1300 {
1301 return pf->flags & I40E_FLAG_TC_MQPRIO;
1302 }
1303
1304 #endif /* _I40E_H_ */
1305