1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
3
4 #ifndef _ICE_TYPE_H_
5 #define _ICE_TYPE_H_
6
7 #define ICE_BYTES_PER_WORD 2
8 #define ICE_BYTES_PER_DWORD 4
9
10 #include "ice_status.h"
11 #include "ice_hw_autogen.h"
12 #include "ice_osdep.h"
13 #include "ice_controlq.h"
14 #include "ice_lan_tx_rx.h"
15 #include "ice_flex_type.h"
16 #include "ice_protocol_type.h"
17 #include "ice_sbq_cmd.h"
18
ice_is_tc_ena(unsigned long bitmap,u8 tc)19 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc)
20 {
21 return test_bit(tc, &bitmap);
22 }
23
round_up_64bit(u64 a,u32 b)24 static inline u64 round_up_64bit(u64 a, u32 b)
25 {
26 return div64_long(((a) + (b) / 2), (b));
27 }
28
ice_round_to_num(u32 N,u32 R)29 static inline u32 ice_round_to_num(u32 N, u32 R)
30 {
31 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
32 ((((N) + (R) - 1) / (R)) * (R)));
33 }
34
35 /* Driver always calls main vsi_handle first */
36 #define ICE_MAIN_VSI_HANDLE 0
37
38 /* debug masks - set these bits in hw->debug_mask to control output */
39 #define ICE_DBG_INIT BIT_ULL(1)
40 #define ICE_DBG_FW_LOG BIT_ULL(3)
41 #define ICE_DBG_LINK BIT_ULL(4)
42 #define ICE_DBG_PHY BIT_ULL(5)
43 #define ICE_DBG_QCTX BIT_ULL(6)
44 #define ICE_DBG_NVM BIT_ULL(7)
45 #define ICE_DBG_LAN BIT_ULL(8)
46 #define ICE_DBG_FLOW BIT_ULL(9)
47 #define ICE_DBG_SW BIT_ULL(13)
48 #define ICE_DBG_SCHED BIT_ULL(14)
49 #define ICE_DBG_RDMA BIT_ULL(15)
50 #define ICE_DBG_PKG BIT_ULL(16)
51 #define ICE_DBG_RES BIT_ULL(17)
52 #define ICE_DBG_PTP BIT_ULL(19)
53 #define ICE_DBG_AQ_MSG BIT_ULL(24)
54 #define ICE_DBG_AQ_DESC BIT_ULL(25)
55 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
56 #define ICE_DBG_AQ_CMD BIT_ULL(27)
57 #define ICE_DBG_USER BIT_ULL(31)
58
59 enum ice_aq_res_ids {
60 ICE_NVM_RES_ID = 1,
61 ICE_SPD_RES_ID,
62 ICE_CHANGE_LOCK_RES_ID,
63 ICE_GLOBAL_CFG_LOCK_RES_ID
64 };
65
66 /* FW update timeout definitions are in milliseconds */
67 #define ICE_NVM_TIMEOUT 180000
68 #define ICE_CHANGE_LOCK_TIMEOUT 1000
69 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 5000
70
71 enum ice_aq_res_access_type {
72 ICE_RES_READ = 1,
73 ICE_RES_WRITE
74 };
75
76 struct ice_driver_ver {
77 u8 major_ver;
78 u8 minor_ver;
79 u8 build_ver;
80 u8 subbuild_ver;
81 u8 driver_string[32];
82 };
83
84 enum ice_fc_mode {
85 ICE_FC_NONE = 0,
86 ICE_FC_RX_PAUSE,
87 ICE_FC_TX_PAUSE,
88 ICE_FC_FULL,
89 ICE_FC_PFC,
90 ICE_FC_DFLT
91 };
92
93 enum ice_phy_cache_mode {
94 ICE_FC_MODE = 0,
95 ICE_SPEED_MODE,
96 ICE_FEC_MODE
97 };
98
99 enum ice_fec_mode {
100 ICE_FEC_NONE = 0,
101 ICE_FEC_RS,
102 ICE_FEC_BASER,
103 ICE_FEC_AUTO
104 };
105
106 struct ice_phy_cache_mode_data {
107 union {
108 enum ice_fec_mode curr_user_fec_req;
109 enum ice_fc_mode curr_user_fc_req;
110 u16 curr_user_speed_req;
111 } data;
112 };
113
114 enum ice_set_fc_aq_failures {
115 ICE_SET_FC_AQ_FAIL_NONE = 0,
116 ICE_SET_FC_AQ_FAIL_GET,
117 ICE_SET_FC_AQ_FAIL_SET,
118 ICE_SET_FC_AQ_FAIL_UPDATE
119 };
120
121 /* Various MAC types */
122 enum ice_mac_type {
123 ICE_MAC_UNKNOWN = 0,
124 ICE_MAC_E810,
125 ICE_MAC_GENERIC,
126 };
127
128 /* Media Types */
129 enum ice_media_type {
130 ICE_MEDIA_UNKNOWN = 0,
131 ICE_MEDIA_FIBER,
132 ICE_MEDIA_BASET,
133 ICE_MEDIA_BACKPLANE,
134 ICE_MEDIA_DA,
135 };
136
137 enum ice_vsi_type {
138 ICE_VSI_PF = 0,
139 ICE_VSI_VF = 1,
140 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
141 ICE_VSI_LB = 6,
142 };
143
144 struct ice_link_status {
145 /* Refer to ice_aq_phy_type for bits definition */
146 u64 phy_type_low;
147 u64 phy_type_high;
148 u8 topo_media_conflict;
149 u16 max_frame_size;
150 u16 link_speed;
151 u16 req_speeds;
152 u8 link_cfg_err;
153 u8 lse_ena; /* Link Status Event notification */
154 u8 link_info;
155 u8 an_info;
156 u8 ext_info;
157 u8 fec_info;
158 u8 pacing;
159 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
160 * ice_aqc_get_phy_caps structure
161 */
162 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
163 };
164
165 /* Different reset sources for which a disable queue AQ call has to be made in
166 * order to clean the Tx scheduler as a part of the reset
167 */
168 enum ice_disq_rst_src {
169 ICE_NO_RESET = 0,
170 ICE_VM_RESET,
171 ICE_VF_RESET,
172 };
173
174 /* PHY info such as phy_type, etc... */
175 struct ice_phy_info {
176 struct ice_link_status link_info;
177 struct ice_link_status link_info_old;
178 u64 phy_type_low;
179 u64 phy_type_high;
180 enum ice_media_type media_type;
181 u8 get_link_info;
182 /* Please refer to struct ice_aqc_get_link_status_data to get
183 * detail of enable bit in curr_user_speed_req
184 */
185 u16 curr_user_speed_req;
186 enum ice_fec_mode curr_user_fec_req;
187 enum ice_fc_mode curr_user_fc_req;
188 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
189 };
190
191 /* protocol enumeration for filters */
192 enum ice_fltr_ptype {
193 /* NONE - used for undef/error */
194 ICE_FLTR_PTYPE_NONF_NONE = 0,
195 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
196 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
197 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
198 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
199 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
200 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
201 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
202 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
203 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
204 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
205 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
206 ICE_FLTR_PTYPE_NONF_IPV4_ESP,
207 ICE_FLTR_PTYPE_NONF_IPV6_ESP,
208 ICE_FLTR_PTYPE_NONF_IPV4_AH,
209 ICE_FLTR_PTYPE_NONF_IPV6_AH,
210 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
211 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
212 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
213 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
214 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
215 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
216 ICE_FLTR_PTYPE_NON_IP_L2,
217 ICE_FLTR_PTYPE_FRAG_IPV4,
218 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
219 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
220 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
221 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
222 ICE_FLTR_PTYPE_MAX,
223 };
224
225 enum ice_fd_hw_seg {
226 ICE_FD_HW_SEG_NON_TUN = 0,
227 ICE_FD_HW_SEG_TUN,
228 ICE_FD_HW_SEG_MAX,
229 };
230
231 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
232 #define ICE_MAX_FDIR_VSI_PER_FILTER 2
233
234 struct ice_fd_hw_prof {
235 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
236 int cnt;
237 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
238 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
239 };
240
241 /* Common HW capabilities for SW use */
242 struct ice_hw_common_caps {
243 u32 valid_functions;
244 /* DCB capabilities */
245 u32 active_tc_bitmap;
246 u32 maxtc;
247
248 /* Tx/Rx queues */
249 u16 num_rxq; /* Number/Total Rx queues */
250 u16 rxq_first_id; /* First queue ID for Rx queues */
251 u16 num_txq; /* Number/Total Tx queues */
252 u16 txq_first_id; /* First queue ID for Tx queues */
253
254 /* MSI-X vectors */
255 u16 num_msix_vectors;
256 u16 msix_vector_first_id;
257
258 /* Max MTU for function or device */
259 u16 max_mtu;
260
261 /* Virtualization support */
262 u8 sr_iov_1_1; /* SR-IOV enabled */
263
264 /* RSS related capabilities */
265 u16 rss_table_size; /* 512 for PFs and 64 for VFs */
266 u8 rss_table_entry_width; /* RSS Entry width in bits */
267
268 u8 dcb;
269 u8 ieee_1588;
270 u8 rdma;
271
272 bool nvm_update_pending_nvm;
273 bool nvm_update_pending_orom;
274 bool nvm_update_pending_netlist;
275 #define ICE_NVM_PENDING_NVM_IMAGE BIT(0)
276 #define ICE_NVM_PENDING_OROM BIT(1)
277 #define ICE_NVM_PENDING_NETLIST BIT(2)
278 bool nvm_unified_update;
279 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
280 };
281
282 /* IEEE 1588 TIME_SYNC specific info */
283 /* Function specific definitions */
284 #define ICE_TS_FUNC_ENA_M BIT(0)
285 #define ICE_TS_SRC_TMR_OWND_M BIT(1)
286 #define ICE_TS_TMR_ENA_M BIT(2)
287 #define ICE_TS_TMR_IDX_OWND_S 4
288 #define ICE_TS_TMR_IDX_OWND_M BIT(4)
289 #define ICE_TS_CLK_FREQ_S 16
290 #define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S)
291 #define ICE_TS_CLK_SRC_S 20
292 #define ICE_TS_CLK_SRC_M BIT(20)
293 #define ICE_TS_TMR_IDX_ASSOC_S 24
294 #define ICE_TS_TMR_IDX_ASSOC_M BIT(24)
295
296 struct ice_ts_func_info {
297 /* Function specific info */
298 u32 clk_freq;
299 u8 clk_src;
300 u8 tmr_index_assoc;
301 u8 ena;
302 u8 tmr_index_owned;
303 u8 src_tmr_owned;
304 u8 tmr_ena;
305 };
306
307 /* Device specific definitions */
308 #define ICE_TS_TMR0_OWNR_M 0x7
309 #define ICE_TS_TMR0_OWND_M BIT(3)
310 #define ICE_TS_TMR1_OWNR_S 4
311 #define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S)
312 #define ICE_TS_TMR1_OWND_M BIT(7)
313 #define ICE_TS_DEV_ENA_M BIT(24)
314 #define ICE_TS_TMR0_ENA_M BIT(25)
315 #define ICE_TS_TMR1_ENA_M BIT(26)
316
317 struct ice_ts_dev_info {
318 /* Device specific info */
319 u32 ena_ports;
320 u32 tmr_own_map;
321 u32 tmr0_owner;
322 u32 tmr1_owner;
323 u8 tmr0_owned;
324 u8 tmr1_owned;
325 u8 ena;
326 u8 tmr0_ena;
327 u8 tmr1_ena;
328 };
329
330 /* Function specific capabilities */
331 struct ice_hw_func_caps {
332 struct ice_hw_common_caps common_cap;
333 u32 num_allocd_vfs; /* Number of allocated VFs */
334 u32 vf_base_id; /* Logical ID of the first VF */
335 u32 guar_num_vsi;
336 u32 fd_fltr_guar; /* Number of filters guaranteed */
337 u32 fd_fltr_best_effort; /* Number of best effort filters */
338 struct ice_ts_func_info ts_func_info;
339 };
340
341 /* Device wide capabilities */
342 struct ice_hw_dev_caps {
343 struct ice_hw_common_caps common_cap;
344 u32 num_vfs_exposed; /* Total number of VFs exposed */
345 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
346 u32 num_flow_director_fltr; /* Number of FD filters available */
347 struct ice_ts_dev_info ts_dev_info;
348 u32 num_funcs;
349 };
350
351 /* MAC info */
352 struct ice_mac_info {
353 u8 lan_addr[ETH_ALEN];
354 u8 perm_addr[ETH_ALEN];
355 };
356
357 /* Reset types used to determine which kind of reset was requested. These
358 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
359 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
360 * because its reset source is different than the other types listed.
361 */
362 enum ice_reset_req {
363 ICE_RESET_POR = 0,
364 ICE_RESET_INVAL = 0,
365 ICE_RESET_CORER = 1,
366 ICE_RESET_GLOBR = 2,
367 ICE_RESET_EMPR = 3,
368 ICE_RESET_PFR = 4,
369 };
370
371 /* Bus parameters */
372 struct ice_bus_info {
373 u16 device;
374 u8 func;
375 };
376
377 /* Flow control (FC) parameters */
378 struct ice_fc_info {
379 enum ice_fc_mode current_mode; /* FC mode in effect */
380 enum ice_fc_mode req_mode; /* FC mode requested by caller */
381 };
382
383 /* Option ROM version information */
384 struct ice_orom_info {
385 u8 major; /* Major version of OROM */
386 u8 patch; /* Patch version of OROM */
387 u16 build; /* Build version of OROM */
388 };
389
390 /* NVM version information */
391 struct ice_nvm_info {
392 u32 eetrack;
393 u8 major;
394 u8 minor;
395 };
396
397 /* netlist version information */
398 struct ice_netlist_info {
399 u32 major; /* major high/low */
400 u32 minor; /* minor high/low */
401 u32 type; /* type high/low */
402 u32 rev; /* revision high/low */
403 u32 hash; /* SHA-1 hash word */
404 u16 cust_ver; /* customer version */
405 };
406
407 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
408 * of the flash image.
409 */
410 enum ice_flash_bank {
411 ICE_INVALID_FLASH_BANK,
412 ICE_1ST_FLASH_BANK,
413 ICE_2ND_FLASH_BANK,
414 };
415
416 /* Enumeration of which flash bank is desired to read from, either the active
417 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
418 * code which just wants to read the active or inactive flash bank.
419 */
420 enum ice_bank_select {
421 ICE_ACTIVE_FLASH_BANK,
422 ICE_INACTIVE_FLASH_BANK,
423 };
424
425 /* information for accessing NVM, OROM, and Netlist flash banks */
426 struct ice_bank_info {
427 u32 nvm_ptr; /* Pointer to 1st NVM bank */
428 u32 nvm_size; /* Size of NVM bank */
429 u32 orom_ptr; /* Pointer to 1st OROM bank */
430 u32 orom_size; /* Size of OROM bank */
431 u32 netlist_ptr; /* Pointer to 1st Netlist bank */
432 u32 netlist_size; /* Size of Netlist bank */
433 enum ice_flash_bank nvm_bank; /* Active NVM bank */
434 enum ice_flash_bank orom_bank; /* Active OROM bank */
435 enum ice_flash_bank netlist_bank; /* Active Netlist bank */
436 };
437
438 /* Flash Chip Information */
439 struct ice_flash_info {
440 struct ice_orom_info orom; /* Option ROM version info */
441 struct ice_nvm_info nvm; /* NVM version information */
442 struct ice_netlist_info netlist;/* Netlist version info */
443 struct ice_bank_info banks; /* Flash Bank information */
444 u16 sr_words; /* Shadow RAM size in words */
445 u32 flash_size; /* Size of available flash in bytes */
446 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
447 };
448
449 struct ice_link_default_override_tlv {
450 u8 options;
451 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
452 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
453 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
454 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
455 #define ICE_LINK_OVERRIDE_EN BIT(3)
456 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
457 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
458 u8 phy_config;
459 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
460 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
461 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
462 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
463 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
464 u8 fec_options;
465 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
466 u8 rsvd1;
467 u64 phy_type_low;
468 u64 phy_type_high;
469 };
470
471 #define ICE_NVM_VER_LEN 32
472
473 /* Max number of port to queue branches w.r.t topology */
474 #define ICE_MAX_TRAFFIC_CLASS 8
475 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
476
477 #define ice_for_each_traffic_class(_i) \
478 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
479
480 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
481 * to driver defined policy for default aggregator
482 */
483 #define ICE_INVAL_TEID 0xFFFFFFFF
484 #define ICE_DFLT_AGG_ID 0
485
486 struct ice_sched_node {
487 struct ice_sched_node *parent;
488 struct ice_sched_node *sibling; /* next sibling in the same layer */
489 struct ice_sched_node **children;
490 struct ice_aqc_txsched_elem_data info;
491 u32 agg_id; /* aggregator group ID */
492 u16 vsi_handle;
493 u8 in_use; /* suspended or in use */
494 u8 tx_sched_layer; /* Logical Layer (1-9) */
495 u8 num_children;
496 u8 tc_num;
497 u8 owner;
498 #define ICE_SCHED_NODE_OWNER_LAN 0
499 #define ICE_SCHED_NODE_OWNER_RDMA 2
500 };
501
502 /* Access Macros for Tx Sched Elements data */
503 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
504
505 /* The aggregator type determines if identifier is for a VSI group,
506 * aggregator group, aggregator of queues, or queue group.
507 */
508 enum ice_agg_type {
509 ICE_AGG_TYPE_UNKNOWN = 0,
510 ICE_AGG_TYPE_VSI,
511 ICE_AGG_TYPE_AGG, /* aggregator */
512 ICE_AGG_TYPE_Q,
513 ICE_AGG_TYPE_QG
514 };
515
516 /* Rate limit types */
517 enum ice_rl_type {
518 ICE_UNKNOWN_BW = 0,
519 ICE_MIN_BW, /* for CIR profile */
520 ICE_MAX_BW, /* for EIR profile */
521 ICE_SHARED_BW /* for shared profile */
522 };
523
524 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
525 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
526 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
527 #define ICE_SCHED_DFLT_RL_PROF_ID 0
528 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
529 #define ICE_SCHED_DFLT_BW_WT 4
530 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
531 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
532
533 /* Data structure for saving BW information */
534 enum ice_bw_type {
535 ICE_BW_TYPE_PRIO,
536 ICE_BW_TYPE_CIR,
537 ICE_BW_TYPE_CIR_WT,
538 ICE_BW_TYPE_EIR,
539 ICE_BW_TYPE_EIR_WT,
540 ICE_BW_TYPE_SHARED,
541 ICE_BW_TYPE_CNT /* This must be last */
542 };
543
544 struct ice_bw {
545 u32 bw;
546 u16 bw_alloc;
547 };
548
549 struct ice_bw_type_info {
550 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT);
551 u8 generic;
552 struct ice_bw cir_bw;
553 struct ice_bw eir_bw;
554 u32 shared_bw;
555 };
556
557 /* VSI queue context structure for given TC */
558 struct ice_q_ctx {
559 u16 q_handle;
560 u32 q_teid;
561 /* bw_t_info saves queue BW information */
562 struct ice_bw_type_info bw_t_info;
563 };
564
565 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
566 struct ice_sched_vsi_info {
567 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
568 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
569 struct list_head list_entry;
570 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
571 u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS];
572 };
573
574 /* driver defines the policy */
575 struct ice_sched_tx_policy {
576 u16 max_num_vsis;
577 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
578 u8 rdma_ena;
579 };
580
581 /* CEE or IEEE 802.1Qaz ETS Configuration data */
582 struct ice_dcb_ets_cfg {
583 u8 willing;
584 u8 cbs;
585 u8 maxtcs;
586 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
587 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
588 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
589 };
590
591 /* CEE or IEEE 802.1Qaz PFC Configuration data */
592 struct ice_dcb_pfc_cfg {
593 u8 willing;
594 u8 mbc;
595 u8 pfccap;
596 u8 pfcena;
597 };
598
599 /* CEE or IEEE 802.1Qaz Application Priority data */
600 struct ice_dcb_app_priority_table {
601 u16 prot_id;
602 u8 priority;
603 u8 selector;
604 };
605
606 #define ICE_MAX_USER_PRIORITY 8
607 #define ICE_DCBX_MAX_APPS 32
608 #define ICE_LLDPDU_SIZE 1500
609 #define ICE_TLV_STATUS_OPER 0x1
610 #define ICE_TLV_STATUS_SYNC 0x2
611 #define ICE_TLV_STATUS_ERR 0x4
612 #define ICE_APP_PROT_ID_ISCSI_860 0x035c
613 #define ICE_APP_SEL_ETHTYPE 0x1
614 #define ICE_APP_SEL_TCPIP 0x2
615 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
616 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
617 #define ICE_CEE_APP_SEL_TCPIP 0x1
618
619 struct ice_dcbx_cfg {
620 u32 numapps;
621 u32 tlv_status; /* CEE mode TLV status */
622 struct ice_dcb_ets_cfg etscfg;
623 struct ice_dcb_ets_cfg etsrec;
624 struct ice_dcb_pfc_cfg pfc;
625 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
626 u8 dcbx_mode;
627 #define ICE_DCBX_MODE_CEE 0x1
628 #define ICE_DCBX_MODE_IEEE 0x2
629 u8 app_mode;
630 #define ICE_DCBX_APPS_NON_WILLING 0x1
631 };
632
633 struct ice_qos_cfg {
634 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
635 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
636 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
637 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
638 u8 is_sw_lldp : 1;
639 };
640
641 struct ice_port_info {
642 struct ice_sched_node *root; /* Root Node per Port */
643 struct ice_hw *hw; /* back pointer to HW instance */
644 u32 last_node_teid; /* scheduler last node info */
645 u16 sw_id; /* Initial switch ID belongs to port */
646 u16 pf_vf_num;
647 u8 port_state;
648 #define ICE_SCHED_PORT_STATE_INIT 0x0
649 #define ICE_SCHED_PORT_STATE_READY 0x1
650 u8 lport;
651 #define ICE_LPORT_MASK 0xff
652 u16 dflt_tx_vsi_rule_id;
653 u16 dflt_tx_vsi_num;
654 u16 dflt_rx_vsi_rule_id;
655 u16 dflt_rx_vsi_num;
656 struct ice_fc_info fc;
657 struct ice_mac_info mac;
658 struct ice_phy_info phy;
659 struct mutex sched_lock; /* protect access to TXSched tree */
660 struct ice_sched_node *
661 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
662 /* List contain profile ID(s) and other params per layer */
663 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
664 struct ice_qos_cfg qos_cfg;
665 u8 is_vf:1;
666 };
667
668 struct ice_switch_info {
669 struct list_head vsi_list_map_head;
670 struct ice_sw_recipe *recp_list;
671 };
672
673 /* FW logging configuration */
674 struct ice_fw_log_evnt {
675 u8 cfg : 4; /* New event enables to configure */
676 u8 cur : 4; /* Current/active event enables */
677 };
678
679 struct ice_fw_log_cfg {
680 u8 cq_en : 1; /* FW logging is enabled via the control queue */
681 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */
682 u8 actv_evnts; /* Cumulation of currently enabled log events */
683
684 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
685 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
686 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
687 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
688 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
689 };
690
691 /* Enum defining the different states of the mailbox snapshot in the
692 * PF-VF mailbox overflow detection algorithm. The snapshot can be in
693 * states:
694 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot
695 * within the mailbox buffer.
696 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot
697 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the
698 * mailbox and mark any VFs sending more messages than the threshold limit set.
699 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF.
700 */
701 enum ice_mbx_snapshot_state {
702 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0,
703 ICE_MAL_VF_DETECT_STATE_TRAVERSE,
704 ICE_MAL_VF_DETECT_STATE_DETECT,
705 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF,
706 };
707
708 /* Structure to hold information of the static snapshot and the mailbox
709 * buffer data used to generate and track the snapshot.
710 * 1. state: the state of the mailbox snapshot in the malicious VF
711 * detection state handler ice_mbx_vf_state_handler()
712 * 2. head: head of the mailbox snapshot in a circular mailbox buffer
713 * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer
714 * 4. num_iterations: number of messages traversed in circular mailbox buffer
715 * 5. num_msg_proc: number of messages processed in mailbox
716 * 6. num_pending_arq: number of pending asynchronous messages
717 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently
718 * serviced work item or interrupt.
719 */
720 struct ice_mbx_snap_buffer_data {
721 enum ice_mbx_snapshot_state state;
722 u32 head;
723 u32 tail;
724 u32 num_iterations;
725 u16 num_msg_proc;
726 u16 num_pending_arq;
727 u16 max_num_msgs_mbx;
728 };
729
730 /* Structure to track messages sent by VFs on mailbox:
731 * 1. vf_cntr: a counter array of VFs to track the number of
732 * asynchronous messages sent by each VF
733 * 2. vfcntr_len: number of entries in VF counter array
734 */
735 struct ice_mbx_vf_counter {
736 u32 *vf_cntr;
737 u32 vfcntr_len;
738 };
739
740 /* Structure to hold data relevant to the captured static snapshot
741 * of the PF-VF mailbox.
742 */
743 struct ice_mbx_snapshot {
744 struct ice_mbx_snap_buffer_data mbx_buf;
745 struct ice_mbx_vf_counter mbx_vf;
746 };
747
748 /* Structure to hold data to be used for capturing or updating a
749 * static snapshot.
750 * 1. num_msg_proc: number of messages processed in mailbox
751 * 2. num_pending_arq: number of pending asynchronous messages
752 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently
753 * serviced work item or interrupt.
754 * 4. async_watermark_val: An upper threshold set by caller to determine
755 * if the pending arq count is large enough to assume that there is
756 * the possibility of a mailicious VF.
757 */
758 struct ice_mbx_data {
759 u16 num_msg_proc;
760 u16 num_pending_arq;
761 u16 max_num_msgs_mbx;
762 u16 async_watermark_val;
763 };
764
765 /* Port hardware description */
766 struct ice_hw {
767 u8 __iomem *hw_addr;
768 void *back;
769 struct ice_aqc_layer_props *layer_info;
770 struct ice_port_info *port_info;
771 /* PSM clock frequency for calculating RL profile params */
772 u32 psm_clk_freq;
773 u64 debug_mask; /* bitmap for debug mask */
774 enum ice_mac_type mac_type;
775
776 u16 fd_ctr_base; /* FD counter base index */
777
778 /* pci info */
779 u16 device_id;
780 u16 vendor_id;
781 u16 subsystem_device_id;
782 u16 subsystem_vendor_id;
783 u8 revision_id;
784
785 u8 pf_id; /* device profile info */
786
787 u16 max_burst_size; /* driver sets this value */
788
789 /* Tx Scheduler values */
790 u8 num_tx_sched_layers;
791 u8 num_tx_sched_phys_layers;
792 u8 flattened_layers;
793 u8 max_cgds;
794 u8 sw_entry_point_layer;
795 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
796 struct list_head agg_list; /* lists all aggregator */
797
798 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
799 u8 evb_veb; /* true for VEB, false for VEPA */
800 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
801 struct ice_bus_info bus;
802 struct ice_flash_info flash;
803 struct ice_hw_dev_caps dev_caps; /* device capabilities */
804 struct ice_hw_func_caps func_caps; /* function capabilities */
805
806 struct ice_switch_info *switch_info; /* switch filter lists */
807
808 /* Control Queue info */
809 struct ice_ctl_q_info adminq;
810 struct ice_ctl_q_info sbq;
811 struct ice_ctl_q_info mailboxq;
812
813 u8 api_branch; /* API branch version */
814 u8 api_maj_ver; /* API major version */
815 u8 api_min_ver; /* API minor version */
816 u8 api_patch; /* API patch version */
817 u8 fw_branch; /* firmware branch version */
818 u8 fw_maj_ver; /* firmware major version */
819 u8 fw_min_ver; /* firmware minor version */
820 u8 fw_patch; /* firmware patch version */
821 u32 fw_build; /* firmware build number */
822
823 struct ice_fw_log_cfg fw_log;
824
825 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
826 * register. Used for determining the ITR/INTRL granularity during
827 * initialization.
828 */
829 #define ICE_MAX_AGG_BW_200G 0x0
830 #define ICE_MAX_AGG_BW_100G 0X1
831 #define ICE_MAX_AGG_BW_50G 0x2
832 #define ICE_MAX_AGG_BW_25G 0x3
833 /* ITR granularity for different speeds */
834 #define ICE_ITR_GRAN_ABOVE_25 2
835 #define ICE_ITR_GRAN_MAX_25 4
836 /* ITR granularity in 1 us */
837 u8 itr_gran;
838 /* INTRL granularity for different speeds */
839 #define ICE_INTRL_GRAN_ABOVE_25 4
840 #define ICE_INTRL_GRAN_MAX_25 8
841 /* INTRL granularity in 1 us */
842 u8 intrl_gran;
843
844 u8 ucast_shared; /* true if VSIs can share unicast addr */
845
846 #define ICE_PHY_PER_NAC 1
847 #define ICE_MAX_QUAD 2
848 #define ICE_NUM_QUAD_TYPE 2
849 #define ICE_PORTS_PER_QUAD 4
850 #define ICE_PHY_0_LAST_QUAD 1
851 #define ICE_PORTS_PER_PHY 8
852 #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY
853
854 /* Active package version (currently active) */
855 struct ice_pkg_ver active_pkg_ver;
856 u32 active_track_id;
857 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
858 u8 active_pkg_in_nvm;
859
860 enum ice_aq_err pkg_dwnld_status;
861
862 /* Driver's package ver - (from the Ice Metadata section) */
863 struct ice_pkg_ver pkg_ver;
864 u8 pkg_name[ICE_PKG_NAME_SIZE];
865
866 /* Driver's Ice segment format version and ID (from the Ice seg) */
867 struct ice_pkg_ver ice_seg_fmt_ver;
868 u8 ice_seg_id[ICE_SEG_ID_SIZE];
869
870 /* Pointer to the ice segment */
871 struct ice_seg *seg;
872
873 /* Pointer to allocated copy of pkg memory */
874 u8 *pkg_copy;
875 u32 pkg_size;
876
877 /* tunneling info */
878 struct mutex tnl_lock;
879 struct ice_tunnel_table tnl;
880
881 struct udp_tunnel_nic_shared udp_tunnel_shared;
882 struct udp_tunnel_nic_info udp_tunnel_nic;
883
884 /* HW block tables */
885 struct ice_blk_info blk[ICE_BLK_COUNT];
886 struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
887 struct list_head fl_profs[ICE_BLK_COUNT];
888
889 /* Flow Director filter info */
890 int fdir_active_fltr;
891
892 struct mutex fdir_fltr_lock; /* protect Flow Director */
893 struct list_head fdir_list_head;
894
895 /* Book-keeping of side-band filter count per flow-type.
896 * This is used to detect and handle input set changes for
897 * respective flow-type.
898 */
899 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
900
901 struct ice_fd_hw_prof **fdir_prof;
902 DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
903 struct mutex rss_locks; /* protect RSS configuration */
904 struct list_head rss_list_head;
905 struct ice_mbx_snapshot mbx_snapshot;
906 };
907
908 /* Statistics collected by each port, VSI, VEB, and S-channel */
909 struct ice_eth_stats {
910 u64 rx_bytes; /* gorc */
911 u64 rx_unicast; /* uprc */
912 u64 rx_multicast; /* mprc */
913 u64 rx_broadcast; /* bprc */
914 u64 rx_discards; /* rdpc */
915 u64 rx_unknown_protocol; /* rupp */
916 u64 tx_bytes; /* gotc */
917 u64 tx_unicast; /* uptc */
918 u64 tx_multicast; /* mptc */
919 u64 tx_broadcast; /* bptc */
920 u64 tx_discards; /* tdpc */
921 u64 tx_errors; /* tepc */
922 };
923
924 #define ICE_MAX_UP 8
925
926 /* Statistics collected by the MAC */
927 struct ice_hw_port_stats {
928 /* eth stats collected by the port */
929 struct ice_eth_stats eth;
930 /* additional port specific stats */
931 u64 tx_dropped_link_down; /* tdold */
932 u64 crc_errors; /* crcerrs */
933 u64 illegal_bytes; /* illerrc */
934 u64 error_bytes; /* errbc */
935 u64 mac_local_faults; /* mlfc */
936 u64 mac_remote_faults; /* mrfc */
937 u64 rx_len_errors; /* rlec */
938 u64 link_xon_rx; /* lxonrxc */
939 u64 link_xoff_rx; /* lxoffrxc */
940 u64 link_xon_tx; /* lxontxc */
941 u64 link_xoff_tx; /* lxofftxc */
942 u64 priority_xon_rx[8]; /* pxonrxc[8] */
943 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
944 u64 priority_xon_tx[8]; /* pxontxc[8] */
945 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
946 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
947 u64 rx_size_64; /* prc64 */
948 u64 rx_size_127; /* prc127 */
949 u64 rx_size_255; /* prc255 */
950 u64 rx_size_511; /* prc511 */
951 u64 rx_size_1023; /* prc1023 */
952 u64 rx_size_1522; /* prc1522 */
953 u64 rx_size_big; /* prc9522 */
954 u64 rx_undersize; /* ruc */
955 u64 rx_fragments; /* rfc */
956 u64 rx_oversize; /* roc */
957 u64 rx_jabber; /* rjc */
958 u64 tx_size_64; /* ptc64 */
959 u64 tx_size_127; /* ptc127 */
960 u64 tx_size_255; /* ptc255 */
961 u64 tx_size_511; /* ptc511 */
962 u64 tx_size_1023; /* ptc1023 */
963 u64 tx_size_1522; /* ptc1522 */
964 u64 tx_size_big; /* ptc9522 */
965 /* flow director stats */
966 u32 fd_sb_status;
967 u64 fd_sb_match;
968 };
969
970 struct ice_aq_get_set_rss_lut_params {
971 u16 vsi_handle; /* software VSI handle */
972 u16 lut_size; /* size of the LUT buffer */
973 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
974 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */
975 u8 global_lut_id; /* only valid when lut_type is global */
976 };
977
978 /* Checksum and Shadow RAM pointers */
979 #define ICE_SR_NVM_CTRL_WORD 0x00
980 #define ICE_SR_BOOT_CFG_PTR 0x132
981 #define ICE_SR_NVM_WOL_CFG 0x19
982 #define ICE_NVM_OROM_VER_OFF 0x02
983 #define ICE_SR_PBA_BLOCK_PTR 0x16
984 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
985 #define ICE_SR_NVM_EETRACK_LO 0x2D
986 #define ICE_SR_NVM_EETRACK_HI 0x2E
987 #define ICE_NVM_VER_LO_SHIFT 0
988 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
989 #define ICE_NVM_VER_HI_SHIFT 12
990 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
991 #define ICE_OROM_VER_PATCH_SHIFT 0
992 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
993 #define ICE_OROM_VER_BUILD_SHIFT 8
994 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
995 #define ICE_OROM_VER_SHIFT 24
996 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
997 #define ICE_SR_PFA_PTR 0x40
998 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
999 #define ICE_SR_NVM_BANK_SIZE 0x43
1000 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
1001 #define ICE_SR_OROM_BANK_SIZE 0x45
1002 #define ICE_SR_NETLIST_BANK_PTR 0x46
1003 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1004 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1005
1006 /* CSS Header words */
1007 #define ICE_NVM_CSS_SREV_L 0x14
1008 #define ICE_NVM_CSS_SREV_H 0x15
1009
1010 /* Length of CSS header section in words */
1011 #define ICE_CSS_HEADER_LENGTH 330
1012
1013 /* Offset of Shadow RAM copy in the NVM bank area. */
1014 #define ICE_NVM_SR_COPY_WORD_OFFSET roundup(ICE_CSS_HEADER_LENGTH, 32)
1015
1016 /* Size in bytes of Option ROM trailer */
1017 #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH)
1018
1019 /* The Link Topology Netlist section is stored as a series of words. It is
1020 * stored in the NVM as a TLV, with the first two words containing the type
1021 * and length.
1022 */
1023 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B
1024 #define ICE_NETLIST_TYPE_OFFSET 0x0000
1025 #define ICE_NETLIST_LEN_OFFSET 0x0001
1026
1027 /* The Link Topology section follows the TLV header. When reading the netlist
1028 * using ice_read_netlist_module, we need to account for the 2-word TLV
1029 * header.
1030 */
1031 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2)
1032
1033 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000)
1034 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001)
1035
1036 #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0)
1037
1038 /* The Netlist ID Block is located after all of the Link Topology nodes. */
1039 #define ICE_NETLIST_ID_BLK_SIZE 0x30
1040 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))
1041
1042 /* netlist ID block field offsets (word offsets) */
1043 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02
1044 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03
1045 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04
1046 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05
1047 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06
1048 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07
1049 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08
1050 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09
1051 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n))
1052 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F
1053
1054 /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */
1055 #define ICE_SR_CTRL_WORD_1_S 0x06
1056 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1057 #define ICE_SR_CTRL_WORD_VALID 0x1
1058 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
1059 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
1060 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
1061
1062 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
1063
1064 /* Link override related */
1065 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1066 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1067 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1068 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1069 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1070 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1071 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1072 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1073
1074 #define ICE_SR_WORDS_IN_1KB 512
1075
1076 /* Hash redirection LUT for VSI - maximum array size */
1077 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
1078
1079 /* AQ API version for LLDP_FILTER_CONTROL */
1080 #define ICE_FW_API_LLDP_FLTR_MAJ 1
1081 #define ICE_FW_API_LLDP_FLTR_MIN 7
1082 #define ICE_FW_API_LLDP_FLTR_PATCH 1
1083
1084 /* AQ API version for report default configuration */
1085 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
1086 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
1087 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
1088
1089 #endif /* _ICE_TYPE_H_ */
1090