1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * arch/arm/include/asm/assembler.h 4 * 5 * Copyright (C) 1996-2000 Russell King 6 * 7 * This file contains arm architecture specific defines 8 * for the different processors. 9 * 10 * Do not include any C declarations in this file - it is included by 11 * assembler source. 12 */ 13 #ifndef __ASM_ASSEMBLER_H__ 14 #define __ASM_ASSEMBLER_H__ 15 16 #ifndef __ASSEMBLY__ 17 #error "Only include this from assembly code" 18 #endif 19 20 #include <asm/ptrace.h> 21 #include <asm/opcodes-virt.h> 22 #include <asm/asm-offsets.h> 23 #include <asm/page.h> 24 #include <asm/thread_info.h> 25 #include <asm/uaccess-asm.h> 26 27 #define IOMEM(x) (x) 28 29 /* 30 * Endian independent macros for shifting bytes within registers. 31 */ 32 #ifndef __ARMEB__ 33 #define lspull lsr 34 #define lspush lsl 35 #define get_byte_0 lsl #0 36 #define get_byte_1 lsr #8 37 #define get_byte_2 lsr #16 38 #define get_byte_3 lsr #24 39 #define put_byte_0 lsl #0 40 #define put_byte_1 lsl #8 41 #define put_byte_2 lsl #16 42 #define put_byte_3 lsl #24 43 #else 44 #define lspull lsl 45 #define lspush lsr 46 #define get_byte_0 lsr #24 47 #define get_byte_1 lsr #16 48 #define get_byte_2 lsr #8 49 #define get_byte_3 lsl #0 50 #define put_byte_0 lsl #24 51 #define put_byte_1 lsl #16 52 #define put_byte_2 lsl #8 53 #define put_byte_3 lsl #0 54 #endif 55 56 /* Select code for any configuration running in BE8 mode */ 57 #ifdef CONFIG_CPU_ENDIAN_BE8 58 #define ARM_BE8(code...) code 59 #else 60 #define ARM_BE8(code...) 61 #endif 62 63 /* 64 * Data preload for architectures that support it 65 */ 66 #if __LINUX_ARM_ARCH__ >= 5 67 #define PLD(code...) code 68 #else 69 #define PLD(code...) 70 #endif 71 72 /* 73 * This can be used to enable code to cacheline align the destination 74 * pointer when bulk writing to memory. Experiments on StrongARM and 75 * XScale didn't show this a worthwhile thing to do when the cache is not 76 * set to write-allocate (this would need further testing on XScale when WA 77 * is used). 78 * 79 * On Feroceon there is much to gain however, regardless of cache mode. 80 */ 81 #ifdef CONFIG_CPU_FEROCEON 82 #define CALGN(code...) code 83 #else 84 #define CALGN(code...) 85 #endif 86 87 #define IMM12_MASK 0xfff 88 89 /* 90 * Enable and disable interrupts 91 */ 92 #if __LINUX_ARM_ARCH__ >= 6 93 .macro disable_irq_notrace 94 cpsid i 95 .endm 96 97 .macro enable_irq_notrace 98 cpsie i 99 .endm 100 #else 101 .macro disable_irq_notrace 102 msr cpsr_c, #PSR_I_BIT | SVC_MODE 103 .endm 104 105 .macro enable_irq_notrace 106 msr cpsr_c, #SVC_MODE 107 .endm 108 #endif 109 110 #if __LINUX_ARM_ARCH__ < 7 111 .macro dsb, args 112 mcr p15, 0, r0, c7, c10, 4 113 .endm 114 115 .macro isb, args 116 mcr p15, 0, r0, c7, c5, 4 117 .endm 118 #endif 119 120 .macro asm_trace_hardirqs_off, save=1 121 #if defined(CONFIG_TRACE_IRQFLAGS) 122 .if \save 123 stmdb sp!, {r0-r3, ip, lr} 124 .endif 125 bl trace_hardirqs_off 126 .if \save 127 ldmia sp!, {r0-r3, ip, lr} 128 .endif 129 #endif 130 .endm 131 132 .macro asm_trace_hardirqs_on, cond=al, save=1 133 #if defined(CONFIG_TRACE_IRQFLAGS) 134 /* 135 * actually the registers should be pushed and pop'd conditionally, but 136 * after bl the flags are certainly clobbered 137 */ 138 .if \save 139 stmdb sp!, {r0-r3, ip, lr} 140 .endif 141 bl\cond trace_hardirqs_on 142 .if \save 143 ldmia sp!, {r0-r3, ip, lr} 144 .endif 145 #endif 146 .endm 147 148 .macro disable_irq, save=1 149 disable_irq_notrace 150 asm_trace_hardirqs_off \save 151 .endm 152 153 .macro enable_irq 154 asm_trace_hardirqs_on 155 enable_irq_notrace 156 .endm 157 /* 158 * Save the current IRQ state and disable IRQs. Note that this macro 159 * assumes FIQs are enabled, and that the processor is in SVC mode. 160 */ 161 .macro save_and_disable_irqs, oldcpsr 162 #ifdef CONFIG_CPU_V7M 163 mrs \oldcpsr, primask 164 #else 165 mrs \oldcpsr, cpsr 166 #endif 167 disable_irq 168 .endm 169 170 .macro save_and_disable_irqs_notrace, oldcpsr 171 #ifdef CONFIG_CPU_V7M 172 mrs \oldcpsr, primask 173 #else 174 mrs \oldcpsr, cpsr 175 #endif 176 disable_irq_notrace 177 .endm 178 179 /* 180 * Restore interrupt state previously stored in a register. We don't 181 * guarantee that this will preserve the flags. 182 */ 183 .macro restore_irqs_notrace, oldcpsr 184 #ifdef CONFIG_CPU_V7M 185 msr primask, \oldcpsr 186 #else 187 msr cpsr_c, \oldcpsr 188 #endif 189 .endm 190 191 .macro restore_irqs, oldcpsr 192 tst \oldcpsr, #PSR_I_BIT 193 asm_trace_hardirqs_on cond=eq 194 restore_irqs_notrace \oldcpsr 195 .endm 196 197 /* 198 * Assembly version of "adr rd, BSYM(sym)". This should only be used to 199 * reference local symbols in the same assembly file which are to be 200 * resolved by the assembler. Other usage is undefined. 201 */ 202 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 203 .macro badr\c, rd, sym 204 #ifdef CONFIG_THUMB2_KERNEL 205 adr\c \rd, \sym + 1 206 #else 207 adr\c \rd, \sym 208 #endif 209 .endm 210 .endr 211 212 /* 213 * Get current thread_info. 214 */ 215 .macro get_thread_info, rd 216 ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT ) 217 THUMB( mov \rd, sp ) 218 THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT ) 219 mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT 220 .endm 221 222 /* 223 * Increment/decrement the preempt count. 224 */ 225 #ifdef CONFIG_PREEMPT_COUNT 226 .macro inc_preempt_count, ti, tmp 227 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 228 add \tmp, \tmp, #1 @ increment it 229 str \tmp, [\ti, #TI_PREEMPT] 230 .endm 231 232 .macro dec_preempt_count, ti, tmp 233 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count 234 sub \tmp, \tmp, #1 @ decrement it 235 str \tmp, [\ti, #TI_PREEMPT] 236 .endm 237 238 .macro dec_preempt_count_ti, ti, tmp 239 get_thread_info \ti 240 dec_preempt_count \ti, \tmp 241 .endm 242 #else 243 .macro inc_preempt_count, ti, tmp 244 .endm 245 246 .macro dec_preempt_count, ti, tmp 247 .endm 248 249 .macro dec_preempt_count_ti, ti, tmp 250 .endm 251 #endif 252 253 #define USERL(l, x...) \ 254 9999: x; \ 255 .pushsection __ex_table,"a"; \ 256 .align 3; \ 257 .long 9999b,l; \ 258 .popsection 259 260 #define USER(x...) USERL(9001f, x) 261 262 #ifdef CONFIG_SMP 263 #define ALT_SMP(instr...) \ 264 9998: instr 265 /* 266 * Note: if you get assembler errors from ALT_UP() when building with 267 * CONFIG_THUMB2_KERNEL, you almost certainly need to use 268 * ALT_SMP( W(instr) ... ) 269 */ 270 #define ALT_UP(instr...) \ 271 .pushsection ".alt.smp.init", "a" ;\ 272 .align 2 ;\ 273 .long 9998b - . ;\ 274 9997: instr ;\ 275 .if . - 9997b == 2 ;\ 276 nop ;\ 277 .endif ;\ 278 .if . - 9997b != 4 ;\ 279 .error "ALT_UP() content must assemble to exactly 4 bytes";\ 280 .endif ;\ 281 .popsection 282 #define ALT_UP_B(label) \ 283 .pushsection ".alt.smp.init", "a" ;\ 284 .align 2 ;\ 285 .long 9998b - . ;\ 286 W(b) . + (label - 9998b) ;\ 287 .popsection 288 #else 289 #define ALT_SMP(instr...) 290 #define ALT_UP(instr...) instr 291 #define ALT_UP_B(label) b label 292 #endif 293 294 /* 295 * Instruction barrier 296 */ 297 .macro instr_sync 298 #if __LINUX_ARM_ARCH__ >= 7 299 isb 300 #elif __LINUX_ARM_ARCH__ == 6 301 mcr p15, 0, r0, c7, c5, 4 302 #endif 303 .endm 304 305 /* 306 * SMP data memory barrier 307 */ 308 .macro smp_dmb mode 309 #ifdef CONFIG_SMP 310 #if __LINUX_ARM_ARCH__ >= 7 311 .ifeqs "\mode","arm" 312 ALT_SMP(dmb ish) 313 .else 314 ALT_SMP(W(dmb) ish) 315 .endif 316 #elif __LINUX_ARM_ARCH__ == 6 317 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb 318 #else 319 #error Incompatible SMP platform 320 #endif 321 .ifeqs "\mode","arm" 322 ALT_UP(nop) 323 .else 324 ALT_UP(W(nop)) 325 .endif 326 #endif 327 .endm 328 329 /* 330 * Raw SMP data memory barrier 331 */ 332 .macro __smp_dmb mode 333 #if __LINUX_ARM_ARCH__ >= 7 334 .ifeqs "\mode","arm" 335 dmb ish 336 .else 337 W(dmb) ish 338 .endif 339 #elif __LINUX_ARM_ARCH__ == 6 340 mcr p15, 0, r0, c7, c10, 5 @ dmb 341 #else 342 .error "Incompatible SMP platform" 343 #endif 344 .endm 345 346 #if defined(CONFIG_CPU_V7M) 347 /* 348 * setmode is used to assert to be in svc mode during boot. For v7-M 349 * this is done in __v7m_setup, so setmode can be empty here. 350 */ 351 .macro setmode, mode, reg 352 .endm 353 #elif defined(CONFIG_THUMB2_KERNEL) 354 .macro setmode, mode, reg 355 mov \reg, #\mode 356 msr cpsr_c, \reg 357 .endm 358 #else 359 .macro setmode, mode, reg 360 msr cpsr_c, #\mode 361 .endm 362 #endif 363 364 /* 365 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is 366 * a scratch register for the macro to overwrite. 367 * 368 * This macro is intended for forcing the CPU into SVC mode at boot time. 369 * you cannot return to the original mode. 370 */ 371 .macro safe_svcmode_maskall reg:req 372 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M) 373 mrs \reg , cpsr 374 eor \reg, \reg, #HYP_MODE 375 tst \reg, #MODE_MASK 376 bic \reg , \reg , #MODE_MASK 377 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE 378 THUMB( orr \reg , \reg , #PSR_T_BIT ) 379 bne 1f 380 orr \reg, \reg, #PSR_A_BIT 381 badr lr, 2f 382 msr spsr_cxsf, \reg 383 __MSR_ELR_HYP(14) 384 __ERET 385 1: msr cpsr_c, \reg 386 2: 387 #else 388 /* 389 * workaround for possibly broken pre-v6 hardware 390 * (akita, Sharp Zaurus C-1000, PXA270-based) 391 */ 392 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg 393 #endif 394 .endm 395 396 /* 397 * STRT/LDRT access macros with ARM and Thumb-2 variants 398 */ 399 #ifdef CONFIG_THUMB2_KERNEL 400 401 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER() 402 9999: 403 .if \inc == 1 404 \instr\()b\t\cond\().w \reg, [\ptr, #\off] 405 .elseif \inc == 4 406 \instr\t\cond\().w \reg, [\ptr, #\off] 407 .else 408 .error "Unsupported inc macro argument" 409 .endif 410 411 .pushsection __ex_table,"a" 412 .align 3 413 .long 9999b, \abort 414 .popsection 415 .endm 416 417 .macro usracc, instr, reg, ptr, inc, cond, rept, abort 418 @ explicit IT instruction needed because of the label 419 @ introduced by the USER macro 420 .ifnc \cond,al 421 .if \rept == 1 422 itt \cond 423 .elseif \rept == 2 424 ittt \cond 425 .else 426 .error "Unsupported rept macro argument" 427 .endif 428 .endif 429 430 @ Slightly optimised to avoid incrementing the pointer twice 431 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort 432 .if \rept == 2 433 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort 434 .endif 435 436 add\cond \ptr, #\rept * \inc 437 .endm 438 439 #else /* !CONFIG_THUMB2_KERNEL */ 440 441 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER() 442 .rept \rept 443 9999: 444 .if \inc == 1 445 \instr\()b\t\cond \reg, [\ptr], #\inc 446 .elseif \inc == 4 447 \instr\t\cond \reg, [\ptr], #\inc 448 .else 449 .error "Unsupported inc macro argument" 450 .endif 451 452 .pushsection __ex_table,"a" 453 .align 3 454 .long 9999b, \abort 455 .popsection 456 .endr 457 .endm 458 459 #endif /* CONFIG_THUMB2_KERNEL */ 460 461 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 462 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort 463 .endm 464 465 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f 466 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort 467 .endm 468 469 /* Utility macro for declaring string literals */ 470 .macro string name:req, string 471 .type \name , #object 472 \name: 473 .asciz "\string" 474 .size \name , . - \name 475 .endm 476 477 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 478 .macro ret\c, reg 479 #if __LINUX_ARM_ARCH__ < 6 480 mov\c pc, \reg 481 #else 482 .ifeqs "\reg", "lr" 483 bx\c \reg 484 .else 485 mov\c pc, \reg 486 .endif 487 #endif 488 .endm 489 .endr 490 491 .macro ret.w, reg 492 ret \reg 493 #ifdef CONFIG_THUMB2_KERNEL 494 nop 495 #endif 496 .endm 497 498 .macro bug, msg, line 499 #ifdef CONFIG_THUMB2_KERNEL 500 1: .inst 0xde02 501 #else 502 1: .inst 0xe7f001f2 503 #endif 504 #ifdef CONFIG_DEBUG_BUGVERBOSE 505 .pushsection .rodata.str, "aMS", %progbits, 1 506 2: .asciz "\msg" 507 .popsection 508 .pushsection __bug_table, "aw" 509 .align 2 510 .word 1b, 2b 511 .hword \line 512 .popsection 513 #endif 514 .endm 515 516 #ifdef CONFIG_KPROBES 517 #define _ASM_NOKPROBE(entry) \ 518 .pushsection "_kprobe_blacklist", "aw" ; \ 519 .balign 4 ; \ 520 .long entry; \ 521 .popsection 522 #else 523 #define _ASM_NOKPROBE(entry) 524 #endif 525 526 .macro __adldst_l, op, reg, sym, tmp, c 527 .if __LINUX_ARM_ARCH__ < 7 528 ldr\c \tmp, .La\@ 529 .subsection 1 530 .align 2 531 .La\@: .long \sym - .Lpc\@ 532 .previous 533 .else 534 .ifnb \c 535 THUMB( ittt \c ) 536 .endif 537 movw\c \tmp, #:lower16:\sym - .Lpc\@ 538 movt\c \tmp, #:upper16:\sym - .Lpc\@ 539 .endif 540 541 #ifndef CONFIG_THUMB2_KERNEL 542 .set .Lpc\@, . + 8 // PC bias 543 .ifc \op, add 544 add\c \reg, \tmp, pc 545 .else 546 \op\c \reg, [pc, \tmp] 547 .endif 548 #else 549 .Lb\@: add\c \tmp, \tmp, pc 550 /* 551 * In Thumb-2 builds, the PC bias depends on whether we are currently 552 * emitting into a .arm or a .thumb section. The size of the add opcode 553 * above will be 2 bytes when emitting in Thumb mode and 4 bytes when 554 * emitting in ARM mode, so let's use this to account for the bias. 555 */ 556 .set .Lpc\@, . + (. - .Lb\@) 557 558 .ifnc \op, add 559 \op\c \reg, [\tmp] 560 .endif 561 #endif 562 .endm 563 564 /* 565 * mov_l - move a constant value or [relocated] address into a register 566 */ 567 .macro mov_l, dst:req, imm:req 568 .if __LINUX_ARM_ARCH__ < 7 569 ldr \dst, =\imm 570 .else 571 movw \dst, #:lower16:\imm 572 movt \dst, #:upper16:\imm 573 .endif 574 .endm 575 576 /* 577 * adr_l - adr pseudo-op with unlimited range 578 * 579 * @dst: destination register 580 * @sym: name of the symbol 581 * @cond: conditional opcode suffix 582 */ 583 .macro adr_l, dst:req, sym:req, cond 584 __adldst_l add, \dst, \sym, \dst, \cond 585 .endm 586 587 /* 588 * ldr_l - ldr <literal> pseudo-op with unlimited range 589 * 590 * @dst: destination register 591 * @sym: name of the symbol 592 * @cond: conditional opcode suffix 593 */ 594 .macro ldr_l, dst:req, sym:req, cond 595 __adldst_l ldr, \dst, \sym, \dst, \cond 596 .endm 597 598 /* 599 * str_l - str <literal> pseudo-op with unlimited range 600 * 601 * @src: source register 602 * @sym: name of the symbol 603 * @tmp: mandatory scratch register 604 * @cond: conditional opcode suffix 605 */ 606 .macro str_l, src:req, sym:req, tmp:req, cond 607 __adldst_l str, \src, \sym, \tmp, \cond 608 .endm 609 610 /* 611 * rev_l - byte-swap a 32-bit value 612 * 613 * @val: source/destination register 614 * @tmp: scratch register 615 */ 616 .macro rev_l, val:req, tmp:req 617 .if __LINUX_ARM_ARCH__ < 6 618 eor \tmp, \val, \val, ror #16 619 bic \tmp, \tmp, #0x00ff0000 620 mov \val, \val, ror #8 621 eor \val, \val, \tmp, lsr #8 622 .else 623 rev \val, \val 624 .endif 625 .endm 626 627 #endif /* __ASM_ASSEMBLER_H__ */ 628