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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
3  */
4 
5 #ifndef _DPU_HW_INTERRUPTS_H
6 #define _DPU_HW_INTERRUPTS_H
7 
8 #include <linux/types.h>
9 
10 #include "dpu_hwio.h"
11 #include "dpu_hw_catalog.h"
12 #include "dpu_hw_util.h"
13 #include "dpu_hw_mdss.h"
14 
15 /* When making changes be sure to sync with dpu_intr_set */
16 enum dpu_hw_intr_reg {
17 	MDP_SSPP_TOP0_INTR,
18 	MDP_SSPP_TOP0_INTR2,
19 	MDP_SSPP_TOP0_HIST_INTR,
20 	MDP_INTF0_INTR,
21 	MDP_INTF1_INTR,
22 	MDP_INTF2_INTR,
23 	MDP_INTF3_INTR,
24 	MDP_INTF4_INTR,
25 	MDP_INTF5_INTR,
26 	MDP_AD4_0_INTR,
27 	MDP_AD4_1_INTR,
28 	MDP_INTF0_7xxx_INTR,
29 	MDP_INTF1_7xxx_INTR,
30 	MDP_INTF5_7xxx_INTR,
31 	MDP_INTR_MAX,
32 };
33 
34 #define DPU_IRQ_IDX(reg_idx, offset)	(reg_idx * 32 + offset)
35 
36 struct dpu_hw_intr;
37 
38 /**
39  * Interrupt operations.
40  */
41 struct dpu_hw_intr_ops {
42 
43 	/**
44 	 * enable_irq - Enable IRQ based on lookup IRQ index
45 	 * @intr:	HW interrupt handle
46 	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
47 	 * @return:	0 for success, otherwise failure
48 	 */
49 	int (*enable_irq_locked)(
50 			struct dpu_hw_intr *intr,
51 			int irq_idx);
52 
53 	/**
54 	 * disable_irq - Disable IRQ based on lookup IRQ index
55 	 * @intr:	HW interrupt handle
56 	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
57 	 * @return:	0 for success, otherwise failure
58 	 */
59 	int (*disable_irq_locked)(
60 			struct dpu_hw_intr *intr,
61 			int irq_idx);
62 
63 	/**
64 	 * clear_all_irqs - Clears all the interrupts (i.e. acknowledges
65 	 *                  any asserted IRQs). Useful during reset.
66 	 * @intr:	HW interrupt handle
67 	 * @return:	0 for success, otherwise failure
68 	 */
69 	int (*clear_all_irqs)(
70 			struct dpu_hw_intr *intr);
71 
72 	/**
73 	 * disable_all_irqs - Disables all the interrupts. Useful during reset.
74 	 * @intr:	HW interrupt handle
75 	 * @return:	0 for success, otherwise failure
76 	 */
77 	int (*disable_all_irqs)(
78 			struct dpu_hw_intr *intr);
79 
80 	/**
81 	 * dispatch_irqs - IRQ dispatcher will call the given callback
82 	 *                 function when a matching interrupt status bit is
83 	 *                 found in the irq mapping table.
84 	 * @intr:	HW interrupt handle
85 	 * @cbfunc:	Callback function pointer
86 	 * @arg:	Argument to pass back during callback
87 	 */
88 	void (*dispatch_irqs)(
89 			struct dpu_hw_intr *intr,
90 			void (*cbfunc)(void *arg, int irq_idx),
91 			void *arg);
92 
93 	/**
94 	 * get_interrupt_status - Gets HW interrupt status, and clear if set,
95 	 *                        based on given lookup IRQ index.
96 	 * @intr:	HW interrupt handle
97 	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
98 	 * @clear:	True to clear irq after read
99 	 */
100 	u32 (*get_interrupt_status)(
101 			struct dpu_hw_intr *intr,
102 			int irq_idx,
103 			bool clear);
104 
105 	/**
106 	 * lock - take the IRQ lock
107 	 * @intr:	HW interrupt handle
108 	 * @return:	irq_flags for the taken spinlock
109 	 */
110 	unsigned long (*lock)(
111 			struct dpu_hw_intr *intr);
112 
113 	/**
114 	 * unlock - take the IRQ lock
115 	 * @intr:	HW interrupt handle
116 	 * @irq_flags:  the irq_flags returned from lock
117 	 */
118 	void (*unlock)(
119 			struct dpu_hw_intr *intr, unsigned long irq_flags);
120 };
121 
122 /**
123  * struct dpu_hw_intr: hw interrupts handling data structure
124  * @hw:               virtual address mapping
125  * @ops:              function pointer mapping for IRQ handling
126  * @cache_irq_mask:   array of IRQ enable masks reg storage created during init
127  * @save_irq_status:  array of IRQ status reg storage created during init
128  * @total_irqs: total number of irq_idx mapped in the hw_interrupts
129  * @irq_lock:         spinlock for accessing IRQ resources
130  */
131 struct dpu_hw_intr {
132 	struct dpu_hw_blk_reg_map hw;
133 	struct dpu_hw_intr_ops ops;
134 	u32 *cache_irq_mask;
135 	u32 *save_irq_status;
136 	u32 total_irqs;
137 	spinlock_t irq_lock;
138 	unsigned long irq_mask;
139 };
140 
141 /**
142  * dpu_hw_intr_init(): Initializes the interrupts hw object
143  * @addr: mapped register io address of MDP
144  * @m :   pointer to mdss catalog data
145  */
146 struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
147 		struct dpu_mdss_cfg *m);
148 
149 /**
150  * dpu_hw_intr_destroy(): Cleanup interrutps hw object
151  * @intr: pointer to interrupts hw object
152  */
153 void dpu_hw_intr_destroy(struct dpu_hw_intr *intr);
154 #endif
155