1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Performance events: 4 * 5 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de> 6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 8 * 9 * Data type definitions, declarations, prototypes. 10 * 11 * Started by: Thomas Gleixner and Ingo Molnar 12 * 13 * For licencing details see kernel-base/COPYING 14 */ 15 #ifndef _UAPI_LINUX_PERF_EVENT_H 16 #define _UAPI_LINUX_PERF_EVENT_H 17 18 #include <linux/types.h> 19 #include <linux/ioctl.h> 20 #include <asm/byteorder.h> 21 22 /* 23 * User-space ABI bits: 24 */ 25 26 /* 27 * attr.type 28 */ 29 enum perf_type_id { 30 PERF_TYPE_HARDWARE = 0, 31 PERF_TYPE_SOFTWARE = 1, 32 PERF_TYPE_TRACEPOINT = 2, 33 PERF_TYPE_HW_CACHE = 3, 34 PERF_TYPE_RAW = 4, 35 PERF_TYPE_BREAKPOINT = 5, 36 37 PERF_TYPE_MAX, /* non-ABI */ 38 }; 39 40 /* 41 * attr.config layout for type PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE 42 * PERF_TYPE_HARDWARE: 0xEEEEEEEE000000AA 43 * AA: hardware event ID 44 * EEEEEEEE: PMU type ID 45 * PERF_TYPE_HW_CACHE: 0xEEEEEEEE00DDCCBB 46 * BB: hardware cache ID 47 * CC: hardware cache op ID 48 * DD: hardware cache op result ID 49 * EEEEEEEE: PMU type ID 50 * If the PMU type ID is 0, the PERF_TYPE_RAW will be applied. 51 */ 52 #define PERF_PMU_TYPE_SHIFT 32 53 #define PERF_HW_EVENT_MASK 0xffffffff 54 55 /* 56 * Generalized performance event event_id types, used by the 57 * attr.event_id parameter of the sys_perf_event_open() 58 * syscall: 59 */ 60 enum perf_hw_id { 61 /* 62 * Common hardware events, generalized by the kernel: 63 */ 64 PERF_COUNT_HW_CPU_CYCLES = 0, 65 PERF_COUNT_HW_INSTRUCTIONS = 1, 66 PERF_COUNT_HW_CACHE_REFERENCES = 2, 67 PERF_COUNT_HW_CACHE_MISSES = 3, 68 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 69 PERF_COUNT_HW_BRANCH_MISSES = 5, 70 PERF_COUNT_HW_BUS_CYCLES = 6, 71 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 72 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 73 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 74 75 PERF_COUNT_HW_MAX, /* non-ABI */ 76 }; 77 78 /* 79 * Generalized hardware cache events: 80 * 81 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 82 * { read, write, prefetch } x 83 * { accesses, misses } 84 */ 85 enum perf_hw_cache_id { 86 PERF_COUNT_HW_CACHE_L1D = 0, 87 PERF_COUNT_HW_CACHE_L1I = 1, 88 PERF_COUNT_HW_CACHE_LL = 2, 89 PERF_COUNT_HW_CACHE_DTLB = 3, 90 PERF_COUNT_HW_CACHE_ITLB = 4, 91 PERF_COUNT_HW_CACHE_BPU = 5, 92 PERF_COUNT_HW_CACHE_NODE = 6, 93 94 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 95 }; 96 97 enum perf_hw_cache_op_id { 98 PERF_COUNT_HW_CACHE_OP_READ = 0, 99 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 100 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 101 102 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 103 }; 104 105 enum perf_hw_cache_op_result_id { 106 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 107 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 108 109 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 110 }; 111 112 /* 113 * Special "software" events provided by the kernel, even if the hardware 114 * does not support performance events. These events measure various 115 * physical and sw events of the kernel (and allow the profiling of them as 116 * well): 117 */ 118 enum perf_sw_ids { 119 PERF_COUNT_SW_CPU_CLOCK = 0, 120 PERF_COUNT_SW_TASK_CLOCK = 1, 121 PERF_COUNT_SW_PAGE_FAULTS = 2, 122 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 123 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 124 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 125 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 126 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 127 PERF_COUNT_SW_EMULATION_FAULTS = 8, 128 PERF_COUNT_SW_DUMMY = 9, 129 PERF_COUNT_SW_BPF_OUTPUT = 10, 130 PERF_COUNT_SW_CGROUP_SWITCHES = 11, 131 132 PERF_COUNT_SW_MAX, /* non-ABI */ 133 }; 134 135 /* 136 * Bits that can be set in attr.sample_type to request information 137 * in the overflow packets. 138 */ 139 enum perf_event_sample_format { 140 PERF_SAMPLE_IP = 1U << 0, 141 PERF_SAMPLE_TID = 1U << 1, 142 PERF_SAMPLE_TIME = 1U << 2, 143 PERF_SAMPLE_ADDR = 1U << 3, 144 PERF_SAMPLE_READ = 1U << 4, 145 PERF_SAMPLE_CALLCHAIN = 1U << 5, 146 PERF_SAMPLE_ID = 1U << 6, 147 PERF_SAMPLE_CPU = 1U << 7, 148 PERF_SAMPLE_PERIOD = 1U << 8, 149 PERF_SAMPLE_STREAM_ID = 1U << 9, 150 PERF_SAMPLE_RAW = 1U << 10, 151 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 152 PERF_SAMPLE_REGS_USER = 1U << 12, 153 PERF_SAMPLE_STACK_USER = 1U << 13, 154 PERF_SAMPLE_WEIGHT = 1U << 14, 155 PERF_SAMPLE_DATA_SRC = 1U << 15, 156 PERF_SAMPLE_IDENTIFIER = 1U << 16, 157 PERF_SAMPLE_TRANSACTION = 1U << 17, 158 PERF_SAMPLE_REGS_INTR = 1U << 18, 159 PERF_SAMPLE_PHYS_ADDR = 1U << 19, 160 PERF_SAMPLE_AUX = 1U << 20, 161 PERF_SAMPLE_CGROUP = 1U << 21, 162 PERF_SAMPLE_DATA_PAGE_SIZE = 1U << 22, 163 PERF_SAMPLE_CODE_PAGE_SIZE = 1U << 23, 164 PERF_SAMPLE_WEIGHT_STRUCT = 1U << 24, 165 166 PERF_SAMPLE_MAX = 1U << 25, /* non-ABI */ 167 168 __PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */ 169 }; 170 171 #define PERF_SAMPLE_WEIGHT_TYPE (PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT) 172 /* 173 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 174 * 175 * If the user does not pass priv level information via branch_sample_type, 176 * the kernel uses the event's priv level. Branch and event priv levels do 177 * not have to match. Branch priv level is checked for permissions. 178 * 179 * The branch types can be combined, however BRANCH_ANY covers all types 180 * of branches and therefore it supersedes all the other types. 181 */ 182 enum perf_branch_sample_type_shift { 183 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ 184 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ 185 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ 186 187 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ 188 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ 189 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ 190 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ 191 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ 192 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ 193 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ 194 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ 195 196 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ 197 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ 198 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */ 199 200 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */ 201 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */ 202 203 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */ 204 205 PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17, /* save low level index of raw branch records */ 206 207 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ 208 }; 209 210 enum perf_branch_sample_type { 211 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 212 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 213 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 214 215 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 216 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 217 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 218 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 219 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 220 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 221 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 222 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 223 224 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 225 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 226 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 227 228 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 229 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 230 231 PERF_SAMPLE_BRANCH_TYPE_SAVE = 232 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 233 234 PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT, 235 236 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 237 }; 238 239 /* 240 * Common flow change classification 241 */ 242 enum { 243 PERF_BR_UNKNOWN = 0, /* unknown */ 244 PERF_BR_COND = 1, /* conditional */ 245 PERF_BR_UNCOND = 2, /* unconditional */ 246 PERF_BR_IND = 3, /* indirect */ 247 PERF_BR_CALL = 4, /* function call */ 248 PERF_BR_IND_CALL = 5, /* indirect function call */ 249 PERF_BR_RET = 6, /* function return */ 250 PERF_BR_SYSCALL = 7, /* syscall */ 251 PERF_BR_SYSRET = 8, /* syscall return */ 252 PERF_BR_COND_CALL = 9, /* conditional function call */ 253 PERF_BR_COND_RET = 10, /* conditional function return */ 254 PERF_BR_ERET = 11, /* exception return */ 255 PERF_BR_IRQ = 12, /* irq */ 256 PERF_BR_MAX, 257 }; 258 259 #define PERF_SAMPLE_BRANCH_PLM_ALL \ 260 (PERF_SAMPLE_BRANCH_USER|\ 261 PERF_SAMPLE_BRANCH_KERNEL|\ 262 PERF_SAMPLE_BRANCH_HV) 263 264 /* 265 * Values to determine ABI of the registers dump. 266 */ 267 enum perf_sample_regs_abi { 268 PERF_SAMPLE_REGS_ABI_NONE = 0, 269 PERF_SAMPLE_REGS_ABI_32 = 1, 270 PERF_SAMPLE_REGS_ABI_64 = 2, 271 }; 272 273 /* 274 * Values for the memory transaction event qualifier, mostly for 275 * abort events. Multiple bits can be set. 276 */ 277 enum { 278 PERF_TXN_ELISION = (1 << 0), /* From elision */ 279 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ 280 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ 281 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ 282 PERF_TXN_RETRY = (1 << 4), /* Retry possible */ 283 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ 284 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ 285 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ 286 287 PERF_TXN_MAX = (1 << 8), /* non-ABI */ 288 289 /* bits 32..63 are reserved for the abort code */ 290 291 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 292 PERF_TXN_ABORT_SHIFT = 32, 293 }; 294 295 /* 296 * The format of the data returned by read() on a perf event fd, 297 * as specified by attr.read_format: 298 * 299 * struct read_format { 300 * { u64 value; 301 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 302 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 303 * { u64 id; } && PERF_FORMAT_ID 304 * { u64 lost; } && PERF_FORMAT_LOST 305 * } && !PERF_FORMAT_GROUP 306 * 307 * { u64 nr; 308 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 309 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 310 * { u64 value; 311 * { u64 id; } && PERF_FORMAT_ID 312 * { u64 lost; } && PERF_FORMAT_LOST 313 * } cntr[nr]; 314 * } && PERF_FORMAT_GROUP 315 * }; 316 */ 317 enum perf_event_read_format { 318 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 319 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 320 PERF_FORMAT_ID = 1U << 2, 321 PERF_FORMAT_GROUP = 1U << 3, 322 PERF_FORMAT_LOST = 1U << 4, 323 324 PERF_FORMAT_MAX = 1U << 5, /* non-ABI */ 325 }; 326 327 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 328 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 329 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 330 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 331 /* add: sample_stack_user */ 332 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ 333 #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ 334 #define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ 335 #define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */ 336 337 /* 338 * Hardware event_id to monitor via a performance monitoring event: 339 * 340 * @sample_max_stack: Max number of frame pointers in a callchain, 341 * should be < /proc/sys/kernel/perf_event_max_stack 342 */ 343 struct perf_event_attr { 344 345 /* 346 * Major type: hardware/software/tracepoint/etc. 347 */ 348 __u32 type; 349 350 /* 351 * Size of the attr structure, for fwd/bwd compat. 352 */ 353 __u32 size; 354 355 /* 356 * Type specific configuration information. 357 */ 358 __u64 config; 359 360 union { 361 __u64 sample_period; 362 __u64 sample_freq; 363 }; 364 365 __u64 sample_type; 366 __u64 read_format; 367 368 __u64 disabled : 1, /* off by default */ 369 inherit : 1, /* children inherit it */ 370 pinned : 1, /* must always be on PMU */ 371 exclusive : 1, /* only group on PMU */ 372 exclude_user : 1, /* don't count user */ 373 exclude_kernel : 1, /* ditto kernel */ 374 exclude_hv : 1, /* ditto hypervisor */ 375 exclude_idle : 1, /* don't count when idle */ 376 mmap : 1, /* include mmap data */ 377 comm : 1, /* include comm data */ 378 freq : 1, /* use freq, not period */ 379 inherit_stat : 1, /* per task counts */ 380 enable_on_exec : 1, /* next exec enables */ 381 task : 1, /* trace fork/exit */ 382 watermark : 1, /* wakeup_watermark */ 383 /* 384 * precise_ip: 385 * 386 * 0 - SAMPLE_IP can have arbitrary skid 387 * 1 - SAMPLE_IP must have constant skid 388 * 2 - SAMPLE_IP requested to have 0 skid 389 * 3 - SAMPLE_IP must have 0 skid 390 * 391 * See also PERF_RECORD_MISC_EXACT_IP 392 */ 393 precise_ip : 2, /* skid constraint */ 394 mmap_data : 1, /* non-exec mmap data */ 395 sample_id_all : 1, /* sample_type all events */ 396 397 exclude_host : 1, /* don't count in host */ 398 exclude_guest : 1, /* don't count in guest */ 399 400 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 401 exclude_callchain_user : 1, /* exclude user callchains */ 402 mmap2 : 1, /* include mmap with inode data */ 403 comm_exec : 1, /* flag comm events that are due to an exec */ 404 use_clockid : 1, /* use @clockid for time fields */ 405 context_switch : 1, /* context switch data */ 406 write_backward : 1, /* Write ring buffer from end to beginning */ 407 namespaces : 1, /* include namespaces data */ 408 ksymbol : 1, /* include ksymbol events */ 409 bpf_event : 1, /* include bpf events */ 410 aux_output : 1, /* generate AUX records instead of events */ 411 cgroup : 1, /* include cgroup events */ 412 text_poke : 1, /* include text poke events */ 413 build_id : 1, /* use build id in mmap2 events */ 414 inherit_thread : 1, /* children only inherit if cloned with CLONE_THREAD */ 415 remove_on_exec : 1, /* event is removed from task on exec */ 416 sigtrap : 1, /* send synchronous SIGTRAP on event */ 417 __reserved_1 : 26; 418 419 union { 420 __u32 wakeup_events; /* wakeup every n events */ 421 __u32 wakeup_watermark; /* bytes before wakeup */ 422 }; 423 424 __u32 bp_type; 425 union { 426 __u64 bp_addr; 427 __u64 kprobe_func; /* for perf_kprobe */ 428 __u64 uprobe_path; /* for perf_uprobe */ 429 __u64 config1; /* extension of config */ 430 }; 431 union { 432 __u64 bp_len; 433 __u64 kprobe_addr; /* when kprobe_func == NULL */ 434 __u64 probe_offset; /* for perf_[k,u]probe */ 435 __u64 config2; /* extension of config1 */ 436 }; 437 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 438 439 /* 440 * Defines set of user regs to dump on samples. 441 * See asm/perf_regs.h for details. 442 */ 443 __u64 sample_regs_user; 444 445 /* 446 * Defines size of the user stack to dump on samples. 447 */ 448 __u32 sample_stack_user; 449 450 __s32 clockid; 451 /* 452 * Defines set of regs to dump for each sample 453 * state captured on: 454 * - precise = 0: PMU interrupt 455 * - precise > 0: sampled instruction 456 * 457 * See asm/perf_regs.h for details. 458 */ 459 __u64 sample_regs_intr; 460 461 /* 462 * Wakeup watermark for AUX area 463 */ 464 __u32 aux_watermark; 465 __u16 sample_max_stack; 466 __u16 __reserved_2; 467 __u32 aux_sample_size; 468 __u32 __reserved_3; 469 470 /* 471 * User provided data if sigtrap=1, passed back to user via 472 * siginfo_t::si_perf_data, e.g. to permit user to identify the event. 473 */ 474 __u64 sig_data; 475 }; 476 477 /* 478 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command 479 * to query bpf programs attached to the same perf tracepoint 480 * as the given perf event. 481 */ 482 struct perf_event_query_bpf { 483 /* 484 * The below ids array length 485 */ 486 __u32 ids_len; 487 /* 488 * Set by the kernel to indicate the number of 489 * available programs 490 */ 491 __u32 prog_cnt; 492 /* 493 * User provided buffer to store program ids 494 */ 495 __u32 ids[0]; 496 }; 497 498 /* 499 * Ioctls that can be done on a perf event fd: 500 */ 501 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 502 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 503 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 504 #define PERF_EVENT_IOC_RESET _IO ('$', 3) 505 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 506 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 507 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 508 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 509 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 510 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) 511 #define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) 512 #define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) 513 514 enum perf_event_ioc_flags { 515 PERF_IOC_FLAG_GROUP = 1U << 0, 516 }; 517 518 /* 519 * Structure of the page that can be mapped via mmap 520 */ 521 struct perf_event_mmap_page { 522 __u32 version; /* version number of this structure */ 523 __u32 compat_version; /* lowest version this is compat with */ 524 525 /* 526 * Bits needed to read the hw events in user-space. 527 * 528 * u32 seq, time_mult, time_shift, index, width; 529 * u64 count, enabled, running; 530 * u64 cyc, time_offset; 531 * s64 pmc = 0; 532 * 533 * do { 534 * seq = pc->lock; 535 * barrier() 536 * 537 * enabled = pc->time_enabled; 538 * running = pc->time_running; 539 * 540 * if (pc->cap_usr_time && enabled != running) { 541 * cyc = rdtsc(); 542 * time_offset = pc->time_offset; 543 * time_mult = pc->time_mult; 544 * time_shift = pc->time_shift; 545 * } 546 * 547 * index = pc->index; 548 * count = pc->offset; 549 * if (pc->cap_user_rdpmc && index) { 550 * width = pc->pmc_width; 551 * pmc = rdpmc(index - 1); 552 * } 553 * 554 * barrier(); 555 * } while (pc->lock != seq); 556 * 557 * NOTE: for obvious reason this only works on self-monitoring 558 * processes. 559 */ 560 __u32 lock; /* seqlock for synchronization */ 561 __u32 index; /* hardware event identifier */ 562 __s64 offset; /* add to hardware event value */ 563 __u64 time_enabled; /* time event active */ 564 __u64 time_running; /* time event on cpu */ 565 union { 566 __u64 capabilities; 567 struct { 568 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 569 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 570 571 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 572 cap_user_time : 1, /* The time_{shift,mult,offset} fields are used */ 573 cap_user_time_zero : 1, /* The time_zero field is used */ 574 cap_user_time_short : 1, /* the time_{cycle,mask} fields are used */ 575 cap_____res : 58; 576 }; 577 }; 578 579 /* 580 * If cap_user_rdpmc this field provides the bit-width of the value 581 * read using the rdpmc() or equivalent instruction. This can be used 582 * to sign extend the result like: 583 * 584 * pmc <<= 64 - width; 585 * pmc >>= 64 - width; // signed shift right 586 * count += pmc; 587 */ 588 __u16 pmc_width; 589 590 /* 591 * If cap_usr_time the below fields can be used to compute the time 592 * delta since time_enabled (in ns) using rdtsc or similar. 593 * 594 * u64 quot, rem; 595 * u64 delta; 596 * 597 * quot = (cyc >> time_shift); 598 * rem = cyc & (((u64)1 << time_shift) - 1); 599 * delta = time_offset + quot * time_mult + 600 * ((rem * time_mult) >> time_shift); 601 * 602 * Where time_offset,time_mult,time_shift and cyc are read in the 603 * seqcount loop described above. This delta can then be added to 604 * enabled and possible running (if index), improving the scaling: 605 * 606 * enabled += delta; 607 * if (index) 608 * running += delta; 609 * 610 * quot = count / running; 611 * rem = count % running; 612 * count = quot * enabled + (rem * enabled) / running; 613 */ 614 __u16 time_shift; 615 __u32 time_mult; 616 __u64 time_offset; 617 /* 618 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 619 * from sample timestamps. 620 * 621 * time = timestamp - time_zero; 622 * quot = time / time_mult; 623 * rem = time % time_mult; 624 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 625 * 626 * And vice versa: 627 * 628 * quot = cyc >> time_shift; 629 * rem = cyc & (((u64)1 << time_shift) - 1); 630 * timestamp = time_zero + quot * time_mult + 631 * ((rem * time_mult) >> time_shift); 632 */ 633 __u64 time_zero; 634 635 __u32 size; /* Header size up to __reserved[] fields. */ 636 __u32 __reserved_1; 637 638 /* 639 * If cap_usr_time_short, the hardware clock is less than 64bit wide 640 * and we must compute the 'cyc' value, as used by cap_usr_time, as: 641 * 642 * cyc = time_cycles + ((cyc - time_cycles) & time_mask) 643 * 644 * NOTE: this form is explicitly chosen such that cap_usr_time_short 645 * is a correction on top of cap_usr_time, and code that doesn't 646 * know about cap_usr_time_short still works under the assumption 647 * the counter doesn't wrap. 648 */ 649 __u64 time_cycles; 650 __u64 time_mask; 651 652 /* 653 * Hole for extension of the self monitor capabilities 654 */ 655 656 __u8 __reserved[116*8]; /* align to 1k. */ 657 658 /* 659 * Control data for the mmap() data buffer. 660 * 661 * User-space reading the @data_head value should issue an smp_rmb(), 662 * after reading this value. 663 * 664 * When the mapping is PROT_WRITE the @data_tail value should be 665 * written by userspace to reflect the last read data, after issueing 666 * an smp_mb() to separate the data read from the ->data_tail store. 667 * In this case the kernel will not over-write unread data. 668 * 669 * See perf_output_put_handle() for the data ordering. 670 * 671 * data_{offset,size} indicate the location and size of the perf record 672 * buffer within the mmapped area. 673 */ 674 __u64 data_head; /* head in the data section */ 675 __u64 data_tail; /* user-space written tail */ 676 __u64 data_offset; /* where the buffer starts */ 677 __u64 data_size; /* data buffer size */ 678 679 /* 680 * AUX area is defined by aux_{offset,size} fields that should be set 681 * by the userspace, so that 682 * 683 * aux_offset >= data_offset + data_size 684 * 685 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. 686 * 687 * Ring buffer pointers aux_{head,tail} have the same semantics as 688 * data_{head,tail} and same ordering rules apply. 689 */ 690 __u64 aux_head; 691 __u64 aux_tail; 692 __u64 aux_offset; 693 __u64 aux_size; 694 }; 695 696 /* 697 * The current state of perf_event_header::misc bits usage: 698 * ('|' used bit, '-' unused bit) 699 * 700 * 012 CDEF 701 * |||---------|||| 702 * 703 * Where: 704 * 0-2 CPUMODE_MASK 705 * 706 * C PROC_MAP_PARSE_TIMEOUT 707 * D MMAP_DATA / COMM_EXEC / FORK_EXEC / SWITCH_OUT 708 * E MMAP_BUILD_ID / EXACT_IP / SCHED_OUT_PREEMPT 709 * F (reserved) 710 */ 711 712 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 713 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 714 #define PERF_RECORD_MISC_KERNEL (1 << 0) 715 #define PERF_RECORD_MISC_USER (2 << 0) 716 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 717 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 718 #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 719 720 /* 721 * Indicates that /proc/PID/maps parsing are truncated by time out. 722 */ 723 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 724 /* 725 * Following PERF_RECORD_MISC_* are used on different 726 * events, so can reuse the same bit position: 727 * 728 * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events 729 * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event 730 * PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal) 731 * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events 732 */ 733 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 734 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 735 #define PERF_RECORD_MISC_FORK_EXEC (1 << 13) 736 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 737 /* 738 * These PERF_RECORD_MISC_* flags below are safely reused 739 * for the following events: 740 * 741 * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events 742 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events 743 * PERF_RECORD_MISC_MMAP_BUILD_ID - PERF_RECORD_MMAP2 event 744 * 745 * 746 * PERF_RECORD_MISC_EXACT_IP: 747 * Indicates that the content of PERF_SAMPLE_IP points to 748 * the actual instruction that triggered the event. See also 749 * perf_event_attr::precise_ip. 750 * 751 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT: 752 * Indicates that thread was preempted in TASK_RUNNING state. 753 * 754 * PERF_RECORD_MISC_MMAP_BUILD_ID: 755 * Indicates that mmap2 event carries build id data. 756 */ 757 #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 758 #define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) 759 #define PERF_RECORD_MISC_MMAP_BUILD_ID (1 << 14) 760 /* 761 * Reserve the last bit to indicate some extended misc field 762 */ 763 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 764 765 struct perf_event_header { 766 __u32 type; 767 __u16 misc; 768 __u16 size; 769 }; 770 771 struct perf_ns_link_info { 772 __u64 dev; 773 __u64 ino; 774 }; 775 776 enum { 777 NET_NS_INDEX = 0, 778 UTS_NS_INDEX = 1, 779 IPC_NS_INDEX = 2, 780 PID_NS_INDEX = 3, 781 USER_NS_INDEX = 4, 782 MNT_NS_INDEX = 5, 783 CGROUP_NS_INDEX = 6, 784 785 NR_NAMESPACES, /* number of available namespaces */ 786 }; 787 788 enum perf_event_type { 789 790 /* 791 * If perf_event_attr.sample_id_all is set then all event types will 792 * have the sample_type selected fields related to where/when 793 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 794 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 795 * just after the perf_event_header and the fields already present for 796 * the existing fields, i.e. at the end of the payload. That way a newer 797 * perf.data file will be supported by older perf tools, with these new 798 * optional fields being ignored. 799 * 800 * struct sample_id { 801 * { u32 pid, tid; } && PERF_SAMPLE_TID 802 * { u64 time; } && PERF_SAMPLE_TIME 803 * { u64 id; } && PERF_SAMPLE_ID 804 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 805 * { u32 cpu, res; } && PERF_SAMPLE_CPU 806 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 807 * } && perf_event_attr::sample_id_all 808 * 809 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 810 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 811 * relative to header.size. 812 */ 813 814 /* 815 * The MMAP events record the PROT_EXEC mappings so that we can 816 * correlate userspace IPs to code. They have the following structure: 817 * 818 * struct { 819 * struct perf_event_header header; 820 * 821 * u32 pid, tid; 822 * u64 addr; 823 * u64 len; 824 * u64 pgoff; 825 * char filename[]; 826 * struct sample_id sample_id; 827 * }; 828 */ 829 PERF_RECORD_MMAP = 1, 830 831 /* 832 * struct { 833 * struct perf_event_header header; 834 * u64 id; 835 * u64 lost; 836 * struct sample_id sample_id; 837 * }; 838 */ 839 PERF_RECORD_LOST = 2, 840 841 /* 842 * struct { 843 * struct perf_event_header header; 844 * 845 * u32 pid, tid; 846 * char comm[]; 847 * struct sample_id sample_id; 848 * }; 849 */ 850 PERF_RECORD_COMM = 3, 851 852 /* 853 * struct { 854 * struct perf_event_header header; 855 * u32 pid, ppid; 856 * u32 tid, ptid; 857 * u64 time; 858 * struct sample_id sample_id; 859 * }; 860 */ 861 PERF_RECORD_EXIT = 4, 862 863 /* 864 * struct { 865 * struct perf_event_header header; 866 * u64 time; 867 * u64 id; 868 * u64 stream_id; 869 * struct sample_id sample_id; 870 * }; 871 */ 872 PERF_RECORD_THROTTLE = 5, 873 PERF_RECORD_UNTHROTTLE = 6, 874 875 /* 876 * struct { 877 * struct perf_event_header header; 878 * u32 pid, ppid; 879 * u32 tid, ptid; 880 * u64 time; 881 * struct sample_id sample_id; 882 * }; 883 */ 884 PERF_RECORD_FORK = 7, 885 886 /* 887 * struct { 888 * struct perf_event_header header; 889 * u32 pid, tid; 890 * 891 * struct read_format values; 892 * struct sample_id sample_id; 893 * }; 894 */ 895 PERF_RECORD_READ = 8, 896 897 /* 898 * struct { 899 * struct perf_event_header header; 900 * 901 * # 902 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 903 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 904 * # is fixed relative to header. 905 * # 906 * 907 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 908 * { u64 ip; } && PERF_SAMPLE_IP 909 * { u32 pid, tid; } && PERF_SAMPLE_TID 910 * { u64 time; } && PERF_SAMPLE_TIME 911 * { u64 addr; } && PERF_SAMPLE_ADDR 912 * { u64 id; } && PERF_SAMPLE_ID 913 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 914 * { u32 cpu, res; } && PERF_SAMPLE_CPU 915 * { u64 period; } && PERF_SAMPLE_PERIOD 916 * 917 * { struct read_format values; } && PERF_SAMPLE_READ 918 * 919 * { u64 nr, 920 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 921 * 922 * # 923 * # The RAW record below is opaque data wrt the ABI 924 * # 925 * # That is, the ABI doesn't make any promises wrt to 926 * # the stability of its content, it may vary depending 927 * # on event, hardware, kernel version and phase of 928 * # the moon. 929 * # 930 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 931 * # 932 * 933 * { u32 size; 934 * char data[size];}&& PERF_SAMPLE_RAW 935 * 936 * { u64 nr; 937 * { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX 938 * { u64 from, to, flags } lbr[nr]; 939 * } && PERF_SAMPLE_BRANCH_STACK 940 * 941 * { u64 abi; # enum perf_sample_regs_abi 942 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 943 * 944 * { u64 size; 945 * char data[size]; 946 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 947 * 948 * { union perf_sample_weight 949 * { 950 * u64 full; && PERF_SAMPLE_WEIGHT 951 * #if defined(__LITTLE_ENDIAN_BITFIELD) 952 * struct { 953 * u32 var1_dw; 954 * u16 var2_w; 955 * u16 var3_w; 956 * } && PERF_SAMPLE_WEIGHT_STRUCT 957 * #elif defined(__BIG_ENDIAN_BITFIELD) 958 * struct { 959 * u16 var3_w; 960 * u16 var2_w; 961 * u32 var1_dw; 962 * } && PERF_SAMPLE_WEIGHT_STRUCT 963 * #endif 964 * } 965 * } 966 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 967 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION 968 * { u64 abi; # enum perf_sample_regs_abi 969 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR 970 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR 971 * { u64 size; 972 * char data[size]; } && PERF_SAMPLE_AUX 973 * { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE 974 * { u64 code_page_size;} && PERF_SAMPLE_CODE_PAGE_SIZE 975 * }; 976 */ 977 PERF_RECORD_SAMPLE = 9, 978 979 /* 980 * The MMAP2 records are an augmented version of MMAP, they add 981 * maj, min, ino numbers to be used to uniquely identify each mapping 982 * 983 * struct { 984 * struct perf_event_header header; 985 * 986 * u32 pid, tid; 987 * u64 addr; 988 * u64 len; 989 * u64 pgoff; 990 * union { 991 * struct { 992 * u32 maj; 993 * u32 min; 994 * u64 ino; 995 * u64 ino_generation; 996 * }; 997 * struct { 998 * u8 build_id_size; 999 * u8 __reserved_1; 1000 * u16 __reserved_2; 1001 * u8 build_id[20]; 1002 * }; 1003 * }; 1004 * u32 prot, flags; 1005 * char filename[]; 1006 * struct sample_id sample_id; 1007 * }; 1008 */ 1009 PERF_RECORD_MMAP2 = 10, 1010 1011 /* 1012 * Records that new data landed in the AUX buffer part. 1013 * 1014 * struct { 1015 * struct perf_event_header header; 1016 * 1017 * u64 aux_offset; 1018 * u64 aux_size; 1019 * u64 flags; 1020 * struct sample_id sample_id; 1021 * }; 1022 */ 1023 PERF_RECORD_AUX = 11, 1024 1025 /* 1026 * Indicates that instruction trace has started 1027 * 1028 * struct { 1029 * struct perf_event_header header; 1030 * u32 pid; 1031 * u32 tid; 1032 * struct sample_id sample_id; 1033 * }; 1034 */ 1035 PERF_RECORD_ITRACE_START = 12, 1036 1037 /* 1038 * Records the dropped/lost sample number. 1039 * 1040 * struct { 1041 * struct perf_event_header header; 1042 * 1043 * u64 lost; 1044 * struct sample_id sample_id; 1045 * }; 1046 */ 1047 PERF_RECORD_LOST_SAMPLES = 13, 1048 1049 /* 1050 * Records a context switch in or out (flagged by 1051 * PERF_RECORD_MISC_SWITCH_OUT). See also 1052 * PERF_RECORD_SWITCH_CPU_WIDE. 1053 * 1054 * struct { 1055 * struct perf_event_header header; 1056 * struct sample_id sample_id; 1057 * }; 1058 */ 1059 PERF_RECORD_SWITCH = 14, 1060 1061 /* 1062 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and 1063 * next_prev_tid that are the next (switching out) or previous 1064 * (switching in) pid/tid. 1065 * 1066 * struct { 1067 * struct perf_event_header header; 1068 * u32 next_prev_pid; 1069 * u32 next_prev_tid; 1070 * struct sample_id sample_id; 1071 * }; 1072 */ 1073 PERF_RECORD_SWITCH_CPU_WIDE = 15, 1074 1075 /* 1076 * struct { 1077 * struct perf_event_header header; 1078 * u32 pid; 1079 * u32 tid; 1080 * u64 nr_namespaces; 1081 * { u64 dev, inode; } [nr_namespaces]; 1082 * struct sample_id sample_id; 1083 * }; 1084 */ 1085 PERF_RECORD_NAMESPACES = 16, 1086 1087 /* 1088 * Record ksymbol register/unregister events: 1089 * 1090 * struct { 1091 * struct perf_event_header header; 1092 * u64 addr; 1093 * u32 len; 1094 * u16 ksym_type; 1095 * u16 flags; 1096 * char name[]; 1097 * struct sample_id sample_id; 1098 * }; 1099 */ 1100 PERF_RECORD_KSYMBOL = 17, 1101 1102 /* 1103 * Record bpf events: 1104 * enum perf_bpf_event_type { 1105 * PERF_BPF_EVENT_UNKNOWN = 0, 1106 * PERF_BPF_EVENT_PROG_LOAD = 1, 1107 * PERF_BPF_EVENT_PROG_UNLOAD = 2, 1108 * }; 1109 * 1110 * struct { 1111 * struct perf_event_header header; 1112 * u16 type; 1113 * u16 flags; 1114 * u32 id; 1115 * u8 tag[BPF_TAG_SIZE]; 1116 * struct sample_id sample_id; 1117 * }; 1118 */ 1119 PERF_RECORD_BPF_EVENT = 18, 1120 1121 /* 1122 * struct { 1123 * struct perf_event_header header; 1124 * u64 id; 1125 * char path[]; 1126 * struct sample_id sample_id; 1127 * }; 1128 */ 1129 PERF_RECORD_CGROUP = 19, 1130 1131 /* 1132 * Records changes to kernel text i.e. self-modified code. 'old_len' is 1133 * the number of old bytes, 'new_len' is the number of new bytes. Either 1134 * 'old_len' or 'new_len' may be zero to indicate, for example, the 1135 * addition or removal of a trampoline. 'bytes' contains the old bytes 1136 * followed immediately by the new bytes. 1137 * 1138 * struct { 1139 * struct perf_event_header header; 1140 * u64 addr; 1141 * u16 old_len; 1142 * u16 new_len; 1143 * u8 bytes[]; 1144 * struct sample_id sample_id; 1145 * }; 1146 */ 1147 PERF_RECORD_TEXT_POKE = 20, 1148 1149 PERF_RECORD_MAX, /* non-ABI */ 1150 }; 1151 1152 enum perf_record_ksymbol_type { 1153 PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0, 1154 PERF_RECORD_KSYMBOL_TYPE_BPF = 1, 1155 /* 1156 * Out of line code such as kprobe-replaced instructions or optimized 1157 * kprobes or ftrace trampolines. 1158 */ 1159 PERF_RECORD_KSYMBOL_TYPE_OOL = 2, 1160 PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */ 1161 }; 1162 1163 #define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0) 1164 1165 enum perf_bpf_event_type { 1166 PERF_BPF_EVENT_UNKNOWN = 0, 1167 PERF_BPF_EVENT_PROG_LOAD = 1, 1168 PERF_BPF_EVENT_PROG_UNLOAD = 2, 1169 PERF_BPF_EVENT_MAX, /* non-ABI */ 1170 }; 1171 1172 #define PERF_MAX_STACK_DEPTH 127 1173 #define PERF_MAX_CONTEXTS_PER_STACK 8 1174 1175 enum perf_callchain_context { 1176 PERF_CONTEXT_HV = (__u64)-32, 1177 PERF_CONTEXT_KERNEL = (__u64)-128, 1178 PERF_CONTEXT_USER = (__u64)-512, 1179 1180 PERF_CONTEXT_GUEST = (__u64)-2048, 1181 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 1182 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 1183 1184 PERF_CONTEXT_MAX = (__u64)-4095, 1185 }; 1186 1187 /** 1188 * PERF_RECORD_AUX::flags bits 1189 */ 1190 #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ 1191 #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ 1192 #define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ 1193 #define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ 1194 #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */ 1195 1196 /* CoreSight PMU AUX buffer formats */ 1197 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */ 1198 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */ 1199 1200 #define PERF_FLAG_FD_NO_GROUP (1UL << 0) 1201 #define PERF_FLAG_FD_OUTPUT (1UL << 1) 1202 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ 1203 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ 1204 1205 #if defined(__LITTLE_ENDIAN_BITFIELD) 1206 union perf_mem_data_src { 1207 __u64 val; 1208 struct { 1209 __u64 mem_op:5, /* type of opcode */ 1210 mem_lvl:14, /* memory hierarchy level */ 1211 mem_snoop:5, /* snoop mode */ 1212 mem_lock:2, /* lock instr */ 1213 mem_dtlb:7, /* tlb access */ 1214 mem_lvl_num:4, /* memory hierarchy level number */ 1215 mem_remote:1, /* remote */ 1216 mem_snoopx:2, /* snoop mode, ext */ 1217 mem_blk:3, /* access blocked */ 1218 mem_rsvd:21; 1219 }; 1220 }; 1221 #elif defined(__BIG_ENDIAN_BITFIELD) 1222 union perf_mem_data_src { 1223 __u64 val; 1224 struct { 1225 __u64 mem_rsvd:21, 1226 mem_blk:3, /* access blocked */ 1227 mem_snoopx:2, /* snoop mode, ext */ 1228 mem_remote:1, /* remote */ 1229 mem_lvl_num:4, /* memory hierarchy level number */ 1230 mem_dtlb:7, /* tlb access */ 1231 mem_lock:2, /* lock instr */ 1232 mem_snoop:5, /* snoop mode */ 1233 mem_lvl:14, /* memory hierarchy level */ 1234 mem_op:5; /* type of opcode */ 1235 }; 1236 }; 1237 #else 1238 #error "Unknown endianness" 1239 #endif 1240 1241 /* type of opcode (load/store/prefetch,code) */ 1242 #define PERF_MEM_OP_NA 0x01 /* not available */ 1243 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 1244 #define PERF_MEM_OP_STORE 0x04 /* store instruction */ 1245 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 1246 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 1247 #define PERF_MEM_OP_SHIFT 0 1248 1249 /* memory hierarchy (memory level, hit or miss) */ 1250 #define PERF_MEM_LVL_NA 0x01 /* not available */ 1251 #define PERF_MEM_LVL_HIT 0x02 /* hit level */ 1252 #define PERF_MEM_LVL_MISS 0x04 /* miss level */ 1253 #define PERF_MEM_LVL_L1 0x08 /* L1 */ 1254 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 1255 #define PERF_MEM_LVL_L2 0x20 /* L2 */ 1256 #define PERF_MEM_LVL_L3 0x40 /* L3 */ 1257 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 1258 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 1259 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 1260 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 1261 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 1262 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 1263 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 1264 #define PERF_MEM_LVL_SHIFT 5 1265 1266 #define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */ 1267 #define PERF_MEM_REMOTE_SHIFT 37 1268 1269 #define PERF_MEM_LVLNUM_L1 0x01 /* L1 */ 1270 #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ 1271 #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ 1272 #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ 1273 /* 5-0xa available */ 1274 #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ 1275 #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ 1276 #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ 1277 #define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */ 1278 #define PERF_MEM_LVLNUM_NA 0x0f /* N/A */ 1279 1280 #define PERF_MEM_LVLNUM_SHIFT 33 1281 1282 /* snoop mode */ 1283 #define PERF_MEM_SNOOP_NA 0x01 /* not available */ 1284 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 1285 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 1286 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 1287 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 1288 #define PERF_MEM_SNOOP_SHIFT 19 1289 1290 #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ 1291 /* 1 free */ 1292 #define PERF_MEM_SNOOPX_SHIFT 38 1293 1294 /* locked instruction */ 1295 #define PERF_MEM_LOCK_NA 0x01 /* not available */ 1296 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 1297 #define PERF_MEM_LOCK_SHIFT 24 1298 1299 /* TLB access */ 1300 #define PERF_MEM_TLB_NA 0x01 /* not available */ 1301 #define PERF_MEM_TLB_HIT 0x02 /* hit level */ 1302 #define PERF_MEM_TLB_MISS 0x04 /* miss level */ 1303 #define PERF_MEM_TLB_L1 0x08 /* L1 */ 1304 #define PERF_MEM_TLB_L2 0x10 /* L2 */ 1305 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 1306 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 1307 #define PERF_MEM_TLB_SHIFT 26 1308 1309 /* Access blocked */ 1310 #define PERF_MEM_BLK_NA 0x01 /* not available */ 1311 #define PERF_MEM_BLK_DATA 0x02 /* data could not be forwarded */ 1312 #define PERF_MEM_BLK_ADDR 0x04 /* address conflict */ 1313 #define PERF_MEM_BLK_SHIFT 40 1314 1315 #define PERF_MEM_S(a, s) \ 1316 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 1317 1318 /* 1319 * single taken branch record layout: 1320 * 1321 * from: source instruction (may not always be a branch insn) 1322 * to: branch target 1323 * mispred: branch target was mispredicted 1324 * predicted: branch target was predicted 1325 * 1326 * support for mispred, predicted is optional. In case it 1327 * is not supported mispred = predicted = 0. 1328 * 1329 * in_tx: running in a hardware transaction 1330 * abort: aborting a hardware transaction 1331 * cycles: cycles from last branch (or 0 if not supported) 1332 * type: branch type 1333 */ 1334 struct perf_branch_entry { 1335 __u64 from; 1336 __u64 to; 1337 __u64 mispred:1, /* target mispredicted */ 1338 predicted:1,/* target predicted */ 1339 in_tx:1, /* in transaction */ 1340 abort:1, /* transaction abort */ 1341 cycles:16, /* cycle count to last branch */ 1342 type:4, /* branch type */ 1343 reserved:40; 1344 }; 1345 1346 union perf_sample_weight { 1347 __u64 full; 1348 #if defined(__LITTLE_ENDIAN_BITFIELD) 1349 struct { 1350 __u32 var1_dw; 1351 __u16 var2_w; 1352 __u16 var3_w; 1353 }; 1354 #elif defined(__BIG_ENDIAN_BITFIELD) 1355 struct { 1356 __u16 var3_w; 1357 __u16 var2_w; 1358 __u32 var1_dw; 1359 }; 1360 #else 1361 #error "Unknown endianness" 1362 #endif 1363 }; 1364 1365 #endif /* _UAPI_LINUX_PERF_EVENT_H */ 1366