1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * tools/testing/selftests/kvm/include/x86_64/processor.h
4 *
5 * Copyright (C) 2018, Google LLC.
6 */
7
8 #ifndef SELFTEST_KVM_PROCESSOR_H
9 #define SELFTEST_KVM_PROCESSOR_H
10
11 #include <assert.h>
12 #include <stdint.h>
13
14 #include <asm/msr-index.h>
15
16 #include "../kvm_util.h"
17
18 #define X86_EFLAGS_FIXED (1u << 1)
19
20 #define X86_CR4_VME (1ul << 0)
21 #define X86_CR4_PVI (1ul << 1)
22 #define X86_CR4_TSD (1ul << 2)
23 #define X86_CR4_DE (1ul << 3)
24 #define X86_CR4_PSE (1ul << 4)
25 #define X86_CR4_PAE (1ul << 5)
26 #define X86_CR4_MCE (1ul << 6)
27 #define X86_CR4_PGE (1ul << 7)
28 #define X86_CR4_PCE (1ul << 8)
29 #define X86_CR4_OSFXSR (1ul << 9)
30 #define X86_CR4_OSXMMEXCPT (1ul << 10)
31 #define X86_CR4_UMIP (1ul << 11)
32 #define X86_CR4_LA57 (1ul << 12)
33 #define X86_CR4_VMXE (1ul << 13)
34 #define X86_CR4_SMXE (1ul << 14)
35 #define X86_CR4_FSGSBASE (1ul << 16)
36 #define X86_CR4_PCIDE (1ul << 17)
37 #define X86_CR4_OSXSAVE (1ul << 18)
38 #define X86_CR4_SMEP (1ul << 20)
39 #define X86_CR4_SMAP (1ul << 21)
40 #define X86_CR4_PKE (1ul << 22)
41
42 /* CPUID.1.ECX */
43 #define CPUID_VMX (1ul << 5)
44 #define CPUID_SMX (1ul << 6)
45 #define CPUID_PCID (1ul << 17)
46 #define CPUID_XSAVE (1ul << 26)
47
48 /* CPUID.7.EBX */
49 #define CPUID_FSGSBASE (1ul << 0)
50 #define CPUID_SMEP (1ul << 7)
51 #define CPUID_SMAP (1ul << 20)
52
53 /* CPUID.7.ECX */
54 #define CPUID_UMIP (1ul << 2)
55 #define CPUID_PKU (1ul << 3)
56 #define CPUID_LA57 (1ul << 16)
57
58 /* CPUID.0x8000_0001.EDX */
59 #define CPUID_GBPAGES (1ul << 26)
60
61 /* Page table bitfield declarations */
62 #define PTE_PRESENT_MASK BIT_ULL(0)
63 #define PTE_WRITABLE_MASK BIT_ULL(1)
64 #define PTE_USER_MASK BIT_ULL(2)
65 #define PTE_ACCESSED_MASK BIT_ULL(5)
66 #define PTE_DIRTY_MASK BIT_ULL(6)
67 #define PTE_LARGE_MASK BIT_ULL(7)
68 #define PTE_GLOBAL_MASK BIT_ULL(8)
69 #define PTE_NX_MASK BIT_ULL(63)
70
71 #define PAGE_SHIFT 12
72
73 #define PHYSICAL_PAGE_MASK GENMASK_ULL(51, 12)
74 #define PTE_GET_PFN(pte) (((pte) & PHYSICAL_PAGE_MASK) >> PAGE_SHIFT)
75
76 /* General Registers in 64-Bit Mode */
77 struct gpr64_regs {
78 u64 rax;
79 u64 rcx;
80 u64 rdx;
81 u64 rbx;
82 u64 rsp;
83 u64 rbp;
84 u64 rsi;
85 u64 rdi;
86 u64 r8;
87 u64 r9;
88 u64 r10;
89 u64 r11;
90 u64 r12;
91 u64 r13;
92 u64 r14;
93 u64 r15;
94 };
95
96 struct desc64 {
97 uint16_t limit0;
98 uint16_t base0;
99 unsigned base1:8, type:4, s:1, dpl:2, p:1;
100 unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8;
101 uint32_t base3;
102 uint32_t zero1;
103 } __attribute__((packed));
104
105 struct desc_ptr {
106 uint16_t size;
107 uint64_t address;
108 } __attribute__((packed));
109
get_desc64_base(const struct desc64 * desc)110 static inline uint64_t get_desc64_base(const struct desc64 *desc)
111 {
112 return ((uint64_t)desc->base3 << 32) |
113 (desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
114 }
115
rdtsc(void)116 static inline uint64_t rdtsc(void)
117 {
118 uint32_t eax, edx;
119 uint64_t tsc_val;
120 /*
121 * The lfence is to wait (on Intel CPUs) until all previous
122 * instructions have been executed. If software requires RDTSC to be
123 * executed prior to execution of any subsequent instruction, it can
124 * execute LFENCE immediately after RDTSC
125 */
126 __asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx));
127 tsc_val = ((uint64_t)edx) << 32 | eax;
128 return tsc_val;
129 }
130
rdtscp(uint32_t * aux)131 static inline uint64_t rdtscp(uint32_t *aux)
132 {
133 uint32_t eax, edx;
134
135 __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux));
136 return ((uint64_t)edx) << 32 | eax;
137 }
138
rdmsr(uint32_t msr)139 static inline uint64_t rdmsr(uint32_t msr)
140 {
141 uint32_t a, d;
142
143 __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory");
144
145 return a | ((uint64_t) d << 32);
146 }
147
wrmsr(uint32_t msr,uint64_t value)148 static inline void wrmsr(uint32_t msr, uint64_t value)
149 {
150 uint32_t a = value;
151 uint32_t d = value >> 32;
152
153 __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory");
154 }
155
156
inw(uint16_t port)157 static inline uint16_t inw(uint16_t port)
158 {
159 uint16_t tmp;
160
161 __asm__ __volatile__("in %%dx, %%ax"
162 : /* output */ "=a" (tmp)
163 : /* input */ "d" (port));
164
165 return tmp;
166 }
167
get_es(void)168 static inline uint16_t get_es(void)
169 {
170 uint16_t es;
171
172 __asm__ __volatile__("mov %%es, %[es]"
173 : /* output */ [es]"=rm"(es));
174 return es;
175 }
176
get_cs(void)177 static inline uint16_t get_cs(void)
178 {
179 uint16_t cs;
180
181 __asm__ __volatile__("mov %%cs, %[cs]"
182 : /* output */ [cs]"=rm"(cs));
183 return cs;
184 }
185
get_ss(void)186 static inline uint16_t get_ss(void)
187 {
188 uint16_t ss;
189
190 __asm__ __volatile__("mov %%ss, %[ss]"
191 : /* output */ [ss]"=rm"(ss));
192 return ss;
193 }
194
get_ds(void)195 static inline uint16_t get_ds(void)
196 {
197 uint16_t ds;
198
199 __asm__ __volatile__("mov %%ds, %[ds]"
200 : /* output */ [ds]"=rm"(ds));
201 return ds;
202 }
203
get_fs(void)204 static inline uint16_t get_fs(void)
205 {
206 uint16_t fs;
207
208 __asm__ __volatile__("mov %%fs, %[fs]"
209 : /* output */ [fs]"=rm"(fs));
210 return fs;
211 }
212
get_gs(void)213 static inline uint16_t get_gs(void)
214 {
215 uint16_t gs;
216
217 __asm__ __volatile__("mov %%gs, %[gs]"
218 : /* output */ [gs]"=rm"(gs));
219 return gs;
220 }
221
get_tr(void)222 static inline uint16_t get_tr(void)
223 {
224 uint16_t tr;
225
226 __asm__ __volatile__("str %[tr]"
227 : /* output */ [tr]"=rm"(tr));
228 return tr;
229 }
230
get_cr0(void)231 static inline uint64_t get_cr0(void)
232 {
233 uint64_t cr0;
234
235 __asm__ __volatile__("mov %%cr0, %[cr0]"
236 : /* output */ [cr0]"=r"(cr0));
237 return cr0;
238 }
239
get_cr3(void)240 static inline uint64_t get_cr3(void)
241 {
242 uint64_t cr3;
243
244 __asm__ __volatile__("mov %%cr3, %[cr3]"
245 : /* output */ [cr3]"=r"(cr3));
246 return cr3;
247 }
248
get_cr4(void)249 static inline uint64_t get_cr4(void)
250 {
251 uint64_t cr4;
252
253 __asm__ __volatile__("mov %%cr4, %[cr4]"
254 : /* output */ [cr4]"=r"(cr4));
255 return cr4;
256 }
257
set_cr4(uint64_t val)258 static inline void set_cr4(uint64_t val)
259 {
260 __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory");
261 }
262
get_gdt(void)263 static inline struct desc_ptr get_gdt(void)
264 {
265 struct desc_ptr gdt;
266 __asm__ __volatile__("sgdt %[gdt]"
267 : /* output */ [gdt]"=m"(gdt));
268 return gdt;
269 }
270
get_idt(void)271 static inline struct desc_ptr get_idt(void)
272 {
273 struct desc_ptr idt;
274 __asm__ __volatile__("sidt %[idt]"
275 : /* output */ [idt]"=m"(idt));
276 return idt;
277 }
278
outl(uint16_t port,uint32_t value)279 static inline void outl(uint16_t port, uint32_t value)
280 {
281 __asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value));
282 }
283
cpuid(uint32_t * eax,uint32_t * ebx,uint32_t * ecx,uint32_t * edx)284 static inline void cpuid(uint32_t *eax, uint32_t *ebx,
285 uint32_t *ecx, uint32_t *edx)
286 {
287 /* ecx is often an input as well as an output. */
288 asm volatile("cpuid"
289 : "=a" (*eax),
290 "=b" (*ebx),
291 "=c" (*ecx),
292 "=d" (*edx)
293 : "0" (*eax), "2" (*ecx)
294 : "memory");
295 }
296
297 #define SET_XMM(__var, __xmm) \
298 asm volatile("movq %0, %%"#__xmm : : "r"(__var) : #__xmm)
299
set_xmm(int n,unsigned long val)300 static inline void set_xmm(int n, unsigned long val)
301 {
302 switch (n) {
303 case 0:
304 SET_XMM(val, xmm0);
305 break;
306 case 1:
307 SET_XMM(val, xmm1);
308 break;
309 case 2:
310 SET_XMM(val, xmm2);
311 break;
312 case 3:
313 SET_XMM(val, xmm3);
314 break;
315 case 4:
316 SET_XMM(val, xmm4);
317 break;
318 case 5:
319 SET_XMM(val, xmm5);
320 break;
321 case 6:
322 SET_XMM(val, xmm6);
323 break;
324 case 7:
325 SET_XMM(val, xmm7);
326 break;
327 }
328 }
329
330 #define GET_XMM(__xmm) \
331 ({ \
332 unsigned long __val; \
333 asm volatile("movq %%"#__xmm", %0" : "=r"(__val)); \
334 __val; \
335 })
336
get_xmm(int n)337 static inline unsigned long get_xmm(int n)
338 {
339 assert(n >= 0 && n <= 7);
340
341 switch (n) {
342 case 0:
343 return GET_XMM(xmm0);
344 case 1:
345 return GET_XMM(xmm1);
346 case 2:
347 return GET_XMM(xmm2);
348 case 3:
349 return GET_XMM(xmm3);
350 case 4:
351 return GET_XMM(xmm4);
352 case 5:
353 return GET_XMM(xmm5);
354 case 6:
355 return GET_XMM(xmm6);
356 case 7:
357 return GET_XMM(xmm7);
358 }
359
360 /* never reached */
361 return 0;
362 }
363
364 bool is_intel_cpu(void);
365
366 struct kvm_x86_state;
367 struct kvm_x86_state *vcpu_save_state(struct kvm_vm *vm, uint32_t vcpuid);
368 void vcpu_load_state(struct kvm_vm *vm, uint32_t vcpuid,
369 struct kvm_x86_state *state);
370
371 struct kvm_msr_list *kvm_get_msr_index_list(void);
372 uint64_t kvm_get_feature_msr(uint64_t msr_index);
373 struct kvm_cpuid2 *kvm_get_supported_cpuid(void);
374
375 struct kvm_cpuid2 *vcpu_get_cpuid(struct kvm_vm *vm, uint32_t vcpuid);
376 void vcpu_set_cpuid(struct kvm_vm *vm, uint32_t vcpuid,
377 struct kvm_cpuid2 *cpuid);
378
379 struct kvm_cpuid_entry2 *
380 kvm_get_supported_cpuid_index(uint32_t function, uint32_t index);
381
382 static inline struct kvm_cpuid_entry2 *
kvm_get_supported_cpuid_entry(uint32_t function)383 kvm_get_supported_cpuid_entry(uint32_t function)
384 {
385 return kvm_get_supported_cpuid_index(function, 0);
386 }
387
388 uint64_t vcpu_get_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index);
389 int _vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index,
390 uint64_t msr_value);
391 void vcpu_set_msr(struct kvm_vm *vm, uint32_t vcpuid, uint64_t msr_index,
392 uint64_t msr_value);
393
394 uint32_t kvm_get_cpuid_max_basic(void);
395 uint32_t kvm_get_cpuid_max_extended(void);
396 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits);
397
398 struct ex_regs {
399 uint64_t rax, rcx, rdx, rbx;
400 uint64_t rbp, rsi, rdi;
401 uint64_t r8, r9, r10, r11;
402 uint64_t r12, r13, r14, r15;
403 uint64_t vector;
404 uint64_t error_code;
405 uint64_t rip;
406 uint64_t cs;
407 uint64_t rflags;
408 };
409
410 void vm_init_descriptor_tables(struct kvm_vm *vm);
411 void vcpu_init_descriptor_tables(struct kvm_vm *vm, uint32_t vcpuid);
412 void vm_install_exception_handler(struct kvm_vm *vm, int vector,
413 void (*handler)(struct ex_regs *));
414
415 uint64_t vm_get_page_table_entry(struct kvm_vm *vm, int vcpuid, uint64_t vaddr);
416 void vm_set_page_table_entry(struct kvm_vm *vm, int vcpuid, uint64_t vaddr,
417 uint64_t pte);
418
419 /*
420 * set_cpuid() - overwrites a matching cpuid entry with the provided value.
421 * matches based on ent->function && ent->index. returns true
422 * if a match was found and successfully overwritten.
423 * @cpuid: the kvm cpuid list to modify.
424 * @ent: cpuid entry to insert
425 */
426 bool set_cpuid(struct kvm_cpuid2 *cpuid, struct kvm_cpuid_entry2 *ent);
427
428 uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2,
429 uint64_t a3);
430
431 struct kvm_cpuid2 *kvm_get_supported_hv_cpuid(void);
432 void vcpu_set_hv_cpuid(struct kvm_vm *vm, uint32_t vcpuid);
433 struct kvm_cpuid2 *vcpu_get_supported_hv_cpuid(struct kvm_vm *vm, uint32_t vcpuid);
434
435 enum x86_page_size {
436 X86_PAGE_SIZE_4K = 0,
437 X86_PAGE_SIZE_2M,
438 X86_PAGE_SIZE_1G,
439 };
440 void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
441 enum x86_page_size page_size);
442
443 /*
444 * Basic CPU control in CR0
445 */
446 #define X86_CR0_PE (1UL<<0) /* Protection Enable */
447 #define X86_CR0_MP (1UL<<1) /* Monitor Coprocessor */
448 #define X86_CR0_EM (1UL<<2) /* Emulation */
449 #define X86_CR0_TS (1UL<<3) /* Task Switched */
450 #define X86_CR0_ET (1UL<<4) /* Extension Type */
451 #define X86_CR0_NE (1UL<<5) /* Numeric Error */
452 #define X86_CR0_WP (1UL<<16) /* Write Protect */
453 #define X86_CR0_AM (1UL<<18) /* Alignment Mask */
454 #define X86_CR0_NW (1UL<<29) /* Not Write-through */
455 #define X86_CR0_CD (1UL<<30) /* Cache Disable */
456 #define X86_CR0_PG (1UL<<31) /* Paging */
457
458 /* VMX_EPT_VPID_CAP bits */
459 #define VMX_EPT_VPID_CAP_AD_BITS (1ULL << 21)
460
461 #endif /* SELFTEST_KVM_PROCESSOR_H */
462