1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved. 4 * Copyright (c) 2015 System Fabric Works, Inc. All rights reserved. 5 */ 6 7 #ifndef RXE_OPCODE_H 8 #define RXE_OPCODE_H 9 10 /* 11 * contains header bit mask definitions and header lengths 12 * declaration of the rxe_opcode_info struct and 13 * rxe_wr_opcode_info struct 14 */ 15 16 enum rxe_wr_mask { 17 WR_INLINE_MASK = BIT(0), 18 WR_ATOMIC_MASK = BIT(1), 19 WR_SEND_MASK = BIT(2), 20 WR_READ_MASK = BIT(3), 21 WR_WRITE_MASK = BIT(4), 22 WR_LOCAL_OP_MASK = BIT(5), 23 24 WR_READ_OR_WRITE_MASK = WR_READ_MASK | WR_WRITE_MASK, 25 WR_READ_WRITE_OR_SEND_MASK = WR_READ_OR_WRITE_MASK | WR_SEND_MASK, 26 WR_WRITE_OR_SEND_MASK = WR_WRITE_MASK | WR_SEND_MASK, 27 WR_ATOMIC_OR_READ_MASK = WR_ATOMIC_MASK | WR_READ_MASK, 28 }; 29 30 #define WR_MAX_QPT (8) 31 32 struct rxe_wr_opcode_info { 33 char *name; 34 enum rxe_wr_mask mask[WR_MAX_QPT]; 35 }; 36 37 extern struct rxe_wr_opcode_info rxe_wr_opcode_info[]; 38 39 enum rxe_hdr_type { 40 RXE_LRH, 41 RXE_GRH, 42 RXE_BTH, 43 RXE_RETH, 44 RXE_AETH, 45 RXE_ATMETH, 46 RXE_ATMACK, 47 RXE_IETH, 48 RXE_RDETH, 49 RXE_DETH, 50 RXE_IMMDT, 51 RXE_PAYLOAD, 52 NUM_HDR_TYPES 53 }; 54 55 enum rxe_hdr_mask { 56 RXE_LRH_MASK = BIT(RXE_LRH), 57 RXE_GRH_MASK = BIT(RXE_GRH), 58 RXE_BTH_MASK = BIT(RXE_BTH), 59 RXE_IMMDT_MASK = BIT(RXE_IMMDT), 60 RXE_RETH_MASK = BIT(RXE_RETH), 61 RXE_AETH_MASK = BIT(RXE_AETH), 62 RXE_ATMETH_MASK = BIT(RXE_ATMETH), 63 RXE_ATMACK_MASK = BIT(RXE_ATMACK), 64 RXE_IETH_MASK = BIT(RXE_IETH), 65 RXE_RDETH_MASK = BIT(RXE_RDETH), 66 RXE_DETH_MASK = BIT(RXE_DETH), 67 RXE_PAYLOAD_MASK = BIT(RXE_PAYLOAD), 68 69 RXE_REQ_MASK = BIT(NUM_HDR_TYPES + 0), 70 RXE_ACK_MASK = BIT(NUM_HDR_TYPES + 1), 71 RXE_SEND_MASK = BIT(NUM_HDR_TYPES + 2), 72 RXE_WRITE_MASK = BIT(NUM_HDR_TYPES + 3), 73 RXE_READ_MASK = BIT(NUM_HDR_TYPES + 4), 74 RXE_ATOMIC_MASK = BIT(NUM_HDR_TYPES + 5), 75 76 RXE_RWR_MASK = BIT(NUM_HDR_TYPES + 6), 77 RXE_COMP_MASK = BIT(NUM_HDR_TYPES + 7), 78 79 RXE_START_MASK = BIT(NUM_HDR_TYPES + 8), 80 RXE_MIDDLE_MASK = BIT(NUM_HDR_TYPES + 9), 81 RXE_END_MASK = BIT(NUM_HDR_TYPES + 10), 82 83 RXE_LOOPBACK_MASK = BIT(NUM_HDR_TYPES + 12), 84 85 RXE_READ_OR_ATOMIC = (RXE_READ_MASK | RXE_ATOMIC_MASK), 86 RXE_WRITE_OR_SEND = (RXE_WRITE_MASK | RXE_SEND_MASK), 87 }; 88 89 #define OPCODE_NONE (-1) 90 #define RXE_NUM_OPCODE 256 91 92 struct rxe_opcode_info { 93 char *name; 94 enum rxe_hdr_mask mask; 95 int length; 96 int offset[NUM_HDR_TYPES]; 97 }; 98 99 extern struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE]; 100 101 #endif /* RXE_OPCODE_H */ 102