| /drivers/reset/sti/ |
| D | reset-stih407.c | 18 #define STIH407_PDN_0(_bit) \ argument
20 #define STIH407_PDN_1(_bit) \ argument
22 #define STIH407_PDN_ETH(_bit, _stat) \ argument
57 #define STIH407_SRST_CORE(_reg, _bit) \ argument
60 #define STIH407_SRST_SBC(_reg, _bit) \ argument
63 #define STIH407_SRST_LPM(_reg, _bit) \ argument
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| /drivers/clk/meson/ |
| D | clk-regmap.h | 117 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument
132 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument
135 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument
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| D | gxbb-aoclk.c | 24 #define GXBB_AO_GATE(_name, _bit) \ argument
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| D | axg-aoclk.c | 35 #define AXG_AO_GATE(_name, _bit) \ argument
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| D | g12a-aoclk.c | 44 #define AXG_AO_GATE(_name, _reg, _bit) \ argument
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| D | meson8b.c | 2613 #define MESON_GATE(_name, _reg, _bit) \ argument
2688 #define MESON_AIU_GLUE_GATE(_name, _reg, _bit) \ argument
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| D | axg.c | 1837 #define MESON_GATE(_name, _reg, _bit) \ argument
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| D | g12a.c | 4165 #define MESON_GATE(_name, _reg, _bit) \ argument
4168 #define MESON_GATE_RO(_name, _reg, _bit) \ argument
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| D | gxbb.c | 2634 #define MESON_GATE(_name, _reg, _bit) \ argument
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| D | axg-audio.c | 23 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \ argument
69 #define AUD_PCLK_GATE(_name, _reg, _bit) { \ argument
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| /drivers/memory/tegra/ |
| D | tegra114.c | 1076 #define TEGRA114_MC_RESET(_name, _control, _status, _bit) \ argument
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| D | tegra210.c | 1234 #define TEGRA210_MC_RESET(_name, _control, _status, _bit) \ argument
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| D | tegra124.c | 1112 #define TEGRA124_MC_RESET(_name, _control, _status, _bit) \ argument
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| D | tegra30.c | 1189 #define TEGRA30_MC_RESET(_name, _control, _status, _bit) \ argument
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| D | tegra20.c | 250 #define TEGRA20_MC_RESET(_name, _control, _status, _reset, _bit) \ argument
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| /drivers/clk/mvebu/ |
| D | armada-37xx-periph.c | 129 #define PERIPH_GATE(_name, _bit) \ argument
181 #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\ argument
186 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \ argument
191 #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \ argument
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| /drivers/reset/ |
| D | reset-uniphier.c | 28 #define UNIPHIER_RESET(_id, _reg, _bit) \ argument
35 #define UNIPHIER_RESETX(_id, _reg, _bit) \ argument
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| /drivers/clk/renesas/ |
| D | rzg2l-cpg.h | 90 #define DEF_MOD(_name, _id, _parent, _off, _bit) \ argument
110 #define DEF_RST(_id, _off, _bit) \ argument
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| /drivers/clk/bcm/ |
| D | clk-kona.h | 99 #define POLICY(_offset, _bit) \ argument
383 #define TRIGGER(_offset, _bit) \ argument
442 #define CCU_LVM_EN(_offset, _bit) \ argument
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| /drivers/pinctrl/mediatek/ |
| D | pinctrl-mt2701.c | 31 #define MTK_PINMUX_SPEC(_pin, _offset, _bit) \ argument
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| D | pinctrl-mtk-common.h | 109 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ argument
157 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ argument
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| /drivers/clk/ |
| D | clk-oxnas.c | 89 #define OXNAS_GATE(_name, _bit, _parents) \ argument
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| D | clk-k210.c | 50 #define K210_GATE(_reg, _bit) \ argument
60 #define K210_MUX(_reg, _bit) \ argument
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| /drivers/clk/uniphier/ |
| D | clk-uniphier.h | 95 #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \ argument
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| /drivers/input/misc/ |
| D | uinput.c | 837 #define uinput_set_bit(_arg, _bit, _max) \ argument
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