1 // SPDX-License-Identifier: GPL-2.0
2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 */
7
8 #include <linux/clk.h>
9 #include <linux/etherdevice.h>
10 #include <linux/if_vlan.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel.h>
13 #include <linux/kmemleak.h>
14 #include <linux/module.h>
15 #include <linux/netdevice.h>
16 #include <linux/net_tstamp.h>
17 #include <linux/of.h>
18 #include <linux/of_mdio.h>
19 #include <linux/of_net.h>
20 #include <linux/of_device.h>
21 #include <linux/phy.h>
22 #include <linux/phy/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/regmap.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/sys_soc.h>
28 #include <linux/dma/ti-cppi5.h>
29 #include <linux/dma/k3-udma-glue.h>
30 #include <net/switchdev.h>
31
32 #include "cpsw_ale.h"
33 #include "cpsw_sl.h"
34 #include "am65-cpsw-nuss.h"
35 #include "am65-cpsw-switchdev.h"
36 #include "k3-cppi-desc-pool.h"
37 #include "am65-cpts.h"
38
39 #define AM65_CPSW_SS_BASE 0x0
40 #define AM65_CPSW_SGMII_BASE 0x100
41 #define AM65_CPSW_XGMII_BASE 0x2100
42 #define AM65_CPSW_CPSW_NU_BASE 0x20000
43 #define AM65_CPSW_NU_PORTS_BASE 0x1000
44 #define AM65_CPSW_NU_FRAM_BASE 0x12000
45 #define AM65_CPSW_NU_STATS_BASE 0x1a000
46 #define AM65_CPSW_NU_ALE_BASE 0x1e000
47 #define AM65_CPSW_NU_CPTS_BASE 0x1d000
48
49 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000
50 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200
51 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200
52
53 #define AM65_CPSW_MAX_PORTS 8
54
55 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN
56 #define AM65_CPSW_MAX_PACKET_SIZE 2024
57
58 #define AM65_CPSW_REG_CTL 0x004
59 #define AM65_CPSW_REG_STAT_PORT_EN 0x014
60 #define AM65_CPSW_REG_PTYPE 0x018
61
62 #define AM65_CPSW_P0_REG_CTL 0x004
63 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008
64
65 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c
66 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020
67 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024
68
69 #define AM65_CPSW_PORTN_REG_SA_L 0x308
70 #define AM65_CPSW_PORTN_REG_SA_H 0x30c
71 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310
72 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314
73 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318
74 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C
75
76 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1)
77 #define AM65_CPSW_CTL_P0_ENABLE BIT(2)
78 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13)
79 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14)
80
81 /* AM65_CPSW_P0_REG_CTL */
82 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0)
83
84 /* AM65_CPSW_PORT_REG_PRI_CTL */
85 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8)
86
87 /* AM65_CPSW_PN_TS_CTL register fields */
88 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4)
89 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5)
90 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6)
91 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7)
92 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10)
93 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11)
94 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16
95
96 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */
97 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16
98
99 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */
100 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16)
101 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17)
102 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18)
103 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19)
104 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20)
105 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21)
106 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22)
107 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23)
108
109 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
110 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3))
111
112 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e)
113
114 #define AM65_CPSW_TS_TX_ANX_ALL_EN \
115 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \
116 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \
117 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN)
118
119 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30
120 /* Number of TX/RX descriptors */
121 #define AM65_CPSW_MAX_TX_DESC 500
122 #define AM65_CPSW_MAX_RX_DESC 500
123
124 #define AM65_CPSW_NAV_PS_DATA_SIZE 16
125 #define AM65_CPSW_NAV_SW_DATA_SIZE 16
126
127 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \
128 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \
129 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
130
am65_cpsw_port_set_sl_mac(struct am65_cpsw_port * slave,const u8 * dev_addr)131 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave,
132 const u8 *dev_addr)
133 {
134 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) |
135 (dev_addr[2] << 16) | (dev_addr[3] << 24);
136 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8);
137
138 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H);
139 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L);
140 }
141
am65_cpsw_sl_ctl_reset(struct am65_cpsw_port * port)142 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port)
143 {
144 cpsw_sl_reset(port->slave.mac_sl, 100);
145 /* Max length register has to be restored after MAC SL reset */
146 writel(AM65_CPSW_MAX_PACKET_SIZE,
147 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN);
148 }
149
am65_cpsw_nuss_get_ver(struct am65_cpsw_common * common)150 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common)
151 {
152 common->nuss_ver = readl(common->ss_base);
153 common->cpsw_ver = readl(common->cpsw_base);
154 dev_info(common->dev,
155 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n",
156 common->nuss_ver,
157 common->cpsw_ver,
158 common->port_num + 1,
159 common->pdata.quirks);
160 }
161
am65_cpsw_nuss_adjust_link(struct net_device * ndev)162 void am65_cpsw_nuss_adjust_link(struct net_device *ndev)
163 {
164 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
165 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
166 struct phy_device *phy = port->slave.phy;
167 u32 mac_control = 0;
168
169 if (!phy)
170 return;
171
172 if (phy->link) {
173 mac_control = CPSW_SL_CTL_GMII_EN;
174
175 if (phy->speed == 1000)
176 mac_control |= CPSW_SL_CTL_GIG;
177 if (phy->speed == 10 && phy_interface_is_rgmii(phy))
178 /* Can be used with in band mode only */
179 mac_control |= CPSW_SL_CTL_EXT_EN;
180 if (phy->speed == 100 && phy->interface == PHY_INTERFACE_MODE_RMII)
181 mac_control |= CPSW_SL_CTL_IFCTL_A;
182 if (phy->duplex)
183 mac_control |= CPSW_SL_CTL_FULLDUPLEX;
184
185 /* RGMII speed is 100M if !CPSW_SL_CTL_GIG*/
186
187 /* rx_pause/tx_pause */
188 if (port->slave.rx_pause)
189 mac_control |= CPSW_SL_CTL_RX_FLOW_EN;
190
191 if (port->slave.tx_pause)
192 mac_control |= CPSW_SL_CTL_TX_FLOW_EN;
193
194 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control);
195
196 /* enable forwarding */
197 cpsw_ale_control_set(common->ale, port->port_id,
198 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
199
200 am65_cpsw_qos_link_up(ndev, phy->speed);
201 netif_tx_wake_all_queues(ndev);
202 } else {
203 int tmo;
204
205 /* disable forwarding */
206 cpsw_ale_control_set(common->ale, port->port_id,
207 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
208
209 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE);
210
211 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100);
212 dev_dbg(common->dev, "donw msc_sl %08x tmo %d\n",
213 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS),
214 tmo);
215
216 cpsw_sl_ctl_reset(port->slave.mac_sl);
217
218 am65_cpsw_qos_link_down(ndev);
219 netif_tx_stop_all_queues(ndev);
220 }
221
222 phy_print_status(phy);
223 }
224
am65_cpsw_nuss_ndo_slave_add_vid(struct net_device * ndev,__be16 proto,u16 vid)225 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev,
226 __be16 proto, u16 vid)
227 {
228 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
229 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
230 u32 port_mask, unreg_mcast = 0;
231 int ret;
232
233 if (!common->is_emac_mode)
234 return 0;
235
236 if (!netif_running(ndev) || !vid)
237 return 0;
238
239 ret = pm_runtime_get_sync(common->dev);
240 if (ret < 0) {
241 pm_runtime_put_noidle(common->dev);
242 return ret;
243 }
244
245 port_mask = BIT(port->port_id) | ALE_PORT_HOST;
246 if (!vid)
247 unreg_mcast = port_mask;
248 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid);
249 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask,
250 unreg_mcast, port_mask, 0);
251
252 pm_runtime_put(common->dev);
253 return ret;
254 }
255
am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device * ndev,__be16 proto,u16 vid)256 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev,
257 __be16 proto, u16 vid)
258 {
259 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
260 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
261 int ret;
262
263 if (!common->is_emac_mode)
264 return 0;
265
266 if (!netif_running(ndev) || !vid)
267 return 0;
268
269 ret = pm_runtime_get_sync(common->dev);
270 if (ret < 0) {
271 pm_runtime_put_noidle(common->dev);
272 return ret;
273 }
274
275 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid);
276 ret = cpsw_ale_del_vlan(common->ale, vid,
277 BIT(port->port_id) | ALE_PORT_HOST);
278
279 pm_runtime_put(common->dev);
280 return ret;
281 }
282
am65_cpsw_slave_set_promisc(struct am65_cpsw_port * port,bool promisc)283 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port,
284 bool promisc)
285 {
286 struct am65_cpsw_common *common = port->common;
287
288 if (promisc && !common->is_emac_mode) {
289 dev_dbg(common->dev, "promisc mode requested in switch mode");
290 return;
291 }
292
293 if (promisc) {
294 /* Enable promiscuous mode */
295 cpsw_ale_control_set(common->ale, port->port_id,
296 ALE_PORT_MACONLY_CAF, 1);
297 dev_dbg(common->dev, "promisc enabled\n");
298 } else {
299 /* Disable promiscuous mode */
300 cpsw_ale_control_set(common->ale, port->port_id,
301 ALE_PORT_MACONLY_CAF, 0);
302 dev_dbg(common->dev, "promisc disabled\n");
303 }
304 }
305
am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device * ndev)306 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev)
307 {
308 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
309 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
310 u32 port_mask;
311 bool promisc;
312
313 promisc = !!(ndev->flags & IFF_PROMISC);
314 am65_cpsw_slave_set_promisc(port, promisc);
315
316 if (promisc)
317 return;
318
319 /* Restore allmulti on vlans if necessary */
320 cpsw_ale_set_allmulti(common->ale,
321 ndev->flags & IFF_ALLMULTI, port->port_id);
322
323 port_mask = ALE_PORT_HOST;
324 /* Clear all mcast from ALE */
325 cpsw_ale_flush_multicast(common->ale, port_mask, -1);
326
327 if (!netdev_mc_empty(ndev)) {
328 struct netdev_hw_addr *ha;
329
330 /* program multicast address list into ALE register */
331 netdev_for_each_mc_addr(ha, ndev) {
332 cpsw_ale_add_mcast(common->ale, ha->addr,
333 port_mask, 0, 0, 0);
334 }
335 }
336 }
337
am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device * ndev,unsigned int txqueue)338 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev,
339 unsigned int txqueue)
340 {
341 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
342 struct am65_cpsw_tx_chn *tx_chn;
343 struct netdev_queue *netif_txq;
344 unsigned long trans_start;
345
346 netif_txq = netdev_get_tx_queue(ndev, txqueue);
347 tx_chn = &common->tx_chns[txqueue];
348 trans_start = netif_txq->trans_start;
349
350 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n",
351 txqueue,
352 netif_tx_queue_stopped(netif_txq),
353 jiffies_to_msecs(jiffies - trans_start),
354 dql_avail(&netif_txq->dql),
355 k3_cppi_desc_pool_avail(tx_chn->desc_pool));
356
357 if (netif_tx_queue_stopped(netif_txq)) {
358 /* try recover if stopped by us */
359 txq_trans_update(netif_txq);
360 netif_tx_wake_queue(netif_txq);
361 }
362 }
363
am65_cpsw_nuss_rx_push(struct am65_cpsw_common * common,struct sk_buff * skb)364 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common,
365 struct sk_buff *skb)
366 {
367 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns;
368 struct cppi5_host_desc_t *desc_rx;
369 struct device *dev = common->dev;
370 u32 pkt_len = skb_tailroom(skb);
371 dma_addr_t desc_dma;
372 dma_addr_t buf_dma;
373 void *swdata;
374
375 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool);
376 if (!desc_rx) {
377 dev_err(dev, "Failed to allocate RXFDQ descriptor\n");
378 return -ENOMEM;
379 }
380 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx);
381
382 buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len,
383 DMA_FROM_DEVICE);
384 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) {
385 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
386 dev_err(dev, "Failed to map rx skb buffer\n");
387 return -EINVAL;
388 }
389
390 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT,
391 AM65_CPSW_NAV_PS_DATA_SIZE);
392 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma);
393 cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb));
394 swdata = cppi5_hdesc_get_swdata(desc_rx);
395 *((void **)swdata) = skb;
396
397 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma);
398 }
399
am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common * common)400 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common)
401 {
402 struct am65_cpsw_host *host_p = am65_common_get_host(common);
403 u32 val, pri_map;
404
405 /* P0 set Receive Priority Type */
406 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL);
407
408 if (common->pf_p0_rx_ptype_rrobin) {
409 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN;
410 /* Enet Ports fifos works in fixed priority mode only, so
411 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0
412 */
413 pri_map = 0x0;
414 } else {
415 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN;
416 /* restore P0_Rx_Pri_Map */
417 pri_map = 0x76543210;
418 }
419
420 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP);
421 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL);
422 }
423
424 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common);
425 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common);
426 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port);
427 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port);
428
am65_cpsw_nuss_common_open(struct am65_cpsw_common * common,netdev_features_t features)429 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common,
430 netdev_features_t features)
431 {
432 struct am65_cpsw_host *host_p = am65_common_get_host(common);
433 int port_idx, i, ret;
434 struct sk_buff *skb;
435 u32 val, port_mask;
436
437 if (common->usage_count)
438 return 0;
439
440 /* Control register */
441 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE |
442 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD,
443 common->cpsw_base + AM65_CPSW_REG_CTL);
444 /* Max length register */
445 writel(AM65_CPSW_MAX_PACKET_SIZE,
446 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN);
447 /* set base flow_id */
448 writel(common->rx_flow_id_base,
449 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET);
450 /* en tx crc offload */
451 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, host_p->port_base + AM65_CPSW_P0_REG_CTL);
452
453 am65_cpsw_nuss_set_p0_ptype(common);
454
455 /* enable statistic */
456 val = BIT(HOST_PORT_NUM);
457 for (port_idx = 0; port_idx < common->port_num; port_idx++) {
458 struct am65_cpsw_port *port = &common->ports[port_idx];
459
460 if (!port->disabled)
461 val |= BIT(port->port_id);
462 }
463 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN);
464
465 /* disable priority elevation */
466 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE);
467
468 cpsw_ale_start(common->ale);
469
470 /* limit to one RX flow only */
471 cpsw_ale_control_set(common->ale, HOST_PORT_NUM,
472 ALE_DEFAULT_THREAD_ID, 0);
473 cpsw_ale_control_set(common->ale, HOST_PORT_NUM,
474 ALE_DEFAULT_THREAD_ENABLE, 1);
475 /* switch to vlan unaware mode */
476 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1);
477 cpsw_ale_control_set(common->ale, HOST_PORT_NUM,
478 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
479
480 /* default vlan cfg: create mask based on enabled ports */
481 port_mask = GENMASK(common->port_num, 0) &
482 ~common->disabled_ports_mask;
483
484 cpsw_ale_add_vlan(common->ale, 0, port_mask,
485 port_mask, port_mask,
486 port_mask & ~ALE_PORT_HOST);
487
488 if (common->is_emac_mode)
489 am65_cpsw_init_host_port_emac(common);
490 else
491 am65_cpsw_init_host_port_switch(common);
492
493 for (i = 0; i < common->rx_chns.descs_num; i++) {
494 skb = __netdev_alloc_skb_ip_align(NULL,
495 AM65_CPSW_MAX_PACKET_SIZE,
496 GFP_KERNEL);
497 if (!skb) {
498 dev_err(common->dev, "cannot allocate skb\n");
499 return -ENOMEM;
500 }
501
502 ret = am65_cpsw_nuss_rx_push(common, skb);
503 if (ret < 0) {
504 dev_err(common->dev,
505 "cannot submit skb to channel rx, error %d\n",
506 ret);
507 kfree_skb(skb);
508 return ret;
509 }
510 kmemleak_not_leak(skb);
511 }
512 k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn);
513
514 for (i = 0; i < common->tx_ch_num; i++) {
515 ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn);
516 if (ret)
517 return ret;
518 napi_enable(&common->tx_chns[i].napi_tx);
519 }
520
521 napi_enable(&common->napi_rx);
522 if (common->rx_irq_disabled) {
523 common->rx_irq_disabled = false;
524 enable_irq(common->rx_chns.irq);
525 }
526
527 dev_dbg(common->dev, "cpsw_nuss started\n");
528 return 0;
529 }
530
531 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma);
532 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma);
533
am65_cpsw_nuss_common_stop(struct am65_cpsw_common * common)534 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common)
535 {
536 int i;
537
538 if (common->usage_count != 1)
539 return 0;
540
541 cpsw_ale_control_set(common->ale, HOST_PORT_NUM,
542 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
543
544 /* shutdown tx channels */
545 atomic_set(&common->tdown_cnt, common->tx_ch_num);
546 /* ensure new tdown_cnt value is visible */
547 smp_mb__after_atomic();
548 reinit_completion(&common->tdown_complete);
549
550 for (i = 0; i < common->tx_ch_num; i++)
551 k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false);
552
553 i = wait_for_completion_timeout(&common->tdown_complete,
554 msecs_to_jiffies(1000));
555 if (!i)
556 dev_err(common->dev, "tx timeout\n");
557 for (i = 0; i < common->tx_ch_num; i++)
558 napi_disable(&common->tx_chns[i].napi_tx);
559
560 for (i = 0; i < common->tx_ch_num; i++) {
561 k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn,
562 &common->tx_chns[i],
563 am65_cpsw_nuss_tx_cleanup);
564 k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn);
565 }
566
567 reinit_completion(&common->tdown_complete);
568 k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true);
569
570 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) {
571 i = wait_for_completion_timeout(&common->tdown_complete, msecs_to_jiffies(1000));
572 if (!i)
573 dev_err(common->dev, "rx teardown timeout\n");
574 }
575
576 napi_disable(&common->napi_rx);
577
578 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++)
579 k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i,
580 &common->rx_chns,
581 am65_cpsw_nuss_rx_cleanup, !!i);
582
583 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn);
584
585 cpsw_ale_stop(common->ale);
586
587 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL);
588 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN);
589
590 dev_dbg(common->dev, "cpsw_nuss stopped\n");
591 return 0;
592 }
593
am65_cpsw_nuss_ndo_slave_stop(struct net_device * ndev)594 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev)
595 {
596 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
597 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
598 int ret;
599
600 if (port->slave.phy)
601 phy_stop(port->slave.phy);
602
603 netif_tx_stop_all_queues(ndev);
604
605 if (port->slave.phy) {
606 phy_disconnect(port->slave.phy);
607 port->slave.phy = NULL;
608 }
609
610 ret = am65_cpsw_nuss_common_stop(common);
611 if (ret)
612 return ret;
613
614 common->usage_count--;
615 pm_runtime_put(common->dev);
616 return 0;
617 }
618
cpsw_restore_vlans(struct net_device * vdev,int vid,void * arg)619 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg)
620 {
621 struct am65_cpsw_port *port = arg;
622
623 if (!vdev)
624 return 0;
625
626 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid);
627 }
628
am65_cpsw_nuss_ndo_slave_open(struct net_device * ndev)629 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev)
630 {
631 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
632 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
633 int ret, i;
634
635 ret = pm_runtime_get_sync(common->dev);
636 if (ret < 0) {
637 pm_runtime_put_noidle(common->dev);
638 return ret;
639 }
640
641 /* Notify the stack of the actual queue counts. */
642 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num);
643 if (ret) {
644 dev_err(common->dev, "cannot set real number of tx queues\n");
645 return ret;
646 }
647
648 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES);
649 if (ret) {
650 dev_err(common->dev, "cannot set real number of rx queues\n");
651 return ret;
652 }
653
654 for (i = 0; i < common->tx_ch_num; i++)
655 netdev_tx_reset_queue(netdev_get_tx_queue(ndev, i));
656
657 ret = am65_cpsw_nuss_common_open(common, ndev->features);
658 if (ret)
659 return ret;
660
661 common->usage_count++;
662
663 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr);
664
665 if (common->is_emac_mode)
666 am65_cpsw_init_port_emac_ale(port);
667 else
668 am65_cpsw_init_port_switch_ale(port);
669
670 /* mac_sl should be configured via phy-link interface */
671 am65_cpsw_sl_ctl_reset(port);
672
673 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET,
674 port->slave.phy_if);
675 if (ret)
676 goto error_cleanup;
677
678 if (port->slave.phy_node) {
679 port->slave.phy = of_phy_connect(ndev,
680 port->slave.phy_node,
681 &am65_cpsw_nuss_adjust_link,
682 0, port->slave.phy_if);
683 if (!port->slave.phy) {
684 dev_err(common->dev, "phy %pOF not found on slave %d\n",
685 port->slave.phy_node,
686 port->port_id);
687 ret = -ENODEV;
688 goto error_cleanup;
689 }
690 }
691
692 /* restore vlan configurations */
693 vlan_for_each(ndev, cpsw_restore_vlans, port);
694
695 phy_attached_info(port->slave.phy);
696 phy_start(port->slave.phy);
697
698 return 0;
699
700 error_cleanup:
701 am65_cpsw_nuss_ndo_slave_stop(ndev);
702 return ret;
703 }
704
am65_cpsw_nuss_rx_cleanup(void * data,dma_addr_t desc_dma)705 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma)
706 {
707 struct am65_cpsw_rx_chn *rx_chn = data;
708 struct cppi5_host_desc_t *desc_rx;
709 struct sk_buff *skb;
710 dma_addr_t buf_dma;
711 u32 buf_dma_len;
712 void **swdata;
713
714 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma);
715 swdata = cppi5_hdesc_get_swdata(desc_rx);
716 skb = *swdata;
717 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
718 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma);
719
720 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE);
721 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
722
723 dev_kfree_skb_any(skb);
724 }
725
am65_cpsw_nuss_rx_ts(struct sk_buff * skb,u32 * psdata)726 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata)
727 {
728 struct skb_shared_hwtstamps *ssh;
729 u64 ns;
730
731 ns = ((u64)psdata[1] << 32) | psdata[0];
732
733 ssh = skb_hwtstamps(skb);
734 memset(ssh, 0, sizeof(*ssh));
735 ssh->hwtstamp = ns_to_ktime(ns);
736 }
737
738 /* RX psdata[2] word format - checksum information */
739 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0)
740 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16)
741 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17)
742 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18)
743 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19)
744 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20)
745
am65_cpsw_nuss_rx_csum(struct sk_buff * skb,u32 csum_info)746 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info)
747 {
748 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum
749 * csum information provides in psdata[2] word:
750 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error
751 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID
752 * bits - indicates IPv4/IPv6 packet
753 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet
754 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets
755 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR
756 */
757 skb_checksum_none_assert(skb);
758
759 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM)))
760 return;
761
762 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID |
763 AM65_CPSW_RX_PSD_IPV4_VALID)) &&
764 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) {
765 /* csum for fragmented packets is unsupported */
766 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT))
767 skb->ip_summed = CHECKSUM_UNNECESSARY;
768 }
769 }
770
am65_cpsw_nuss_rx_packets(struct am65_cpsw_common * common,u32 flow_idx)771 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common,
772 u32 flow_idx)
773 {
774 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns;
775 u32 buf_dma_len, pkt_len, port_id = 0, csum_info;
776 struct am65_cpsw_ndev_priv *ndev_priv;
777 struct am65_cpsw_ndev_stats *stats;
778 struct cppi5_host_desc_t *desc_rx;
779 struct device *dev = common->dev;
780 struct sk_buff *skb, *new_skb;
781 dma_addr_t desc_dma, buf_dma;
782 struct am65_cpsw_port *port;
783 struct net_device *ndev;
784 void **swdata;
785 u32 *psdata;
786 int ret = 0;
787
788 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma);
789 if (ret) {
790 if (ret != -ENODATA)
791 dev_err(dev, "RX: pop chn fail %d\n", ret);
792 return ret;
793 }
794
795 if (cppi5_desc_is_tdcm(desc_dma)) {
796 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx);
797 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ)
798 complete(&common->tdown_complete);
799 return 0;
800 }
801
802 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma);
803 dev_dbg(dev, "%s flow_idx: %u desc %pad\n",
804 __func__, flow_idx, &desc_dma);
805
806 swdata = cppi5_hdesc_get_swdata(desc_rx);
807 skb = *swdata;
808 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
809 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma);
810 pkt_len = cppi5_hdesc_get_pktlen(desc_rx);
811 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL);
812 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id);
813 port = am65_common_get_port(common, port_id);
814 ndev = port->ndev;
815 skb->dev = ndev;
816
817 psdata = cppi5_hdesc_get_psdata(desc_rx);
818 /* add RX timestamp */
819 if (port->rx_ts_enabled)
820 am65_cpsw_nuss_rx_ts(skb, psdata);
821 csum_info = psdata[2];
822 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info);
823
824 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE);
825
826 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx);
827
828 new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE);
829 if (new_skb) {
830 ndev_priv = netdev_priv(ndev);
831 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark);
832 skb_put(skb, pkt_len);
833 skb->protocol = eth_type_trans(skb, ndev);
834 am65_cpsw_nuss_rx_csum(skb, csum_info);
835 napi_gro_receive(&common->napi_rx, skb);
836
837 stats = this_cpu_ptr(ndev_priv->stats);
838
839 u64_stats_update_begin(&stats->syncp);
840 stats->rx_packets++;
841 stats->rx_bytes += pkt_len;
842 u64_stats_update_end(&stats->syncp);
843 kmemleak_not_leak(new_skb);
844 } else {
845 ndev->stats.rx_dropped++;
846 new_skb = skb;
847 }
848
849 if (netif_dormant(ndev)) {
850 dev_kfree_skb_any(new_skb);
851 ndev->stats.rx_dropped++;
852 return 0;
853 }
854
855 ret = am65_cpsw_nuss_rx_push(common, new_skb);
856 if (WARN_ON(ret < 0)) {
857 dev_kfree_skb_any(new_skb);
858 ndev->stats.rx_errors++;
859 ndev->stats.rx_dropped++;
860 }
861
862 return ret;
863 }
864
am65_cpsw_nuss_rx_poll(struct napi_struct * napi_rx,int budget)865 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget)
866 {
867 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx);
868 int flow = AM65_CPSW_MAX_RX_FLOWS;
869 int cur_budget, ret;
870 int num_rx = 0;
871
872 /* process every flow */
873 while (flow--) {
874 cur_budget = budget - num_rx;
875
876 while (cur_budget--) {
877 ret = am65_cpsw_nuss_rx_packets(common, flow);
878 if (ret)
879 break;
880 num_rx++;
881 }
882
883 if (num_rx >= budget)
884 break;
885 }
886
887 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget);
888
889 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) {
890 if (common->rx_irq_disabled) {
891 common->rx_irq_disabled = false;
892 enable_irq(common->rx_chns.irq);
893 }
894 }
895
896 return num_rx;
897 }
898
am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn * tx_chn,struct cppi5_host_desc_t * desc)899 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn,
900 struct cppi5_host_desc_t *desc)
901 {
902 struct cppi5_host_desc_t *first_desc, *next_desc;
903 dma_addr_t buf_dma, next_desc_dma;
904 u32 buf_dma_len;
905
906 first_desc = desc;
907 next_desc = first_desc;
908
909 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len);
910 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma);
911
912 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE);
913
914 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc);
915 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma);
916 while (next_desc_dma) {
917 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool,
918 next_desc_dma);
919 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len);
920 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma);
921
922 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len,
923 DMA_TO_DEVICE);
924
925 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc);
926 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma);
927
928 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc);
929 }
930
931 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc);
932 }
933
am65_cpsw_nuss_tx_cleanup(void * data,dma_addr_t desc_dma)934 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma)
935 {
936 struct am65_cpsw_tx_chn *tx_chn = data;
937 struct cppi5_host_desc_t *desc_tx;
938 struct sk_buff *skb;
939 void **swdata;
940
941 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma);
942 swdata = cppi5_hdesc_get_swdata(desc_tx);
943 skb = *(swdata);
944 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx);
945
946 dev_kfree_skb_any(skb);
947 }
948
949 static struct sk_buff *
am65_cpsw_nuss_tx_compl_packet(struct am65_cpsw_tx_chn * tx_chn,dma_addr_t desc_dma)950 am65_cpsw_nuss_tx_compl_packet(struct am65_cpsw_tx_chn *tx_chn,
951 dma_addr_t desc_dma)
952 {
953 struct am65_cpsw_ndev_priv *ndev_priv;
954 struct am65_cpsw_ndev_stats *stats;
955 struct cppi5_host_desc_t *desc_tx;
956 struct net_device *ndev;
957 struct sk_buff *skb;
958 void **swdata;
959
960 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool,
961 desc_dma);
962 swdata = cppi5_hdesc_get_swdata(desc_tx);
963 skb = *(swdata);
964 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx);
965
966 ndev = skb->dev;
967
968 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb);
969
970 ndev_priv = netdev_priv(ndev);
971 stats = this_cpu_ptr(ndev_priv->stats);
972 u64_stats_update_begin(&stats->syncp);
973 stats->tx_packets++;
974 stats->tx_bytes += skb->len;
975 u64_stats_update_end(&stats->syncp);
976
977 return skb;
978 }
979
am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn * tx_chn,struct net_device * ndev,struct netdev_queue * netif_txq)980 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev,
981 struct netdev_queue *netif_txq)
982 {
983 if (netif_tx_queue_stopped(netif_txq)) {
984 /* Check whether the queue is stopped due to stalled
985 * tx dma, if the queue is stopped then wake the queue
986 * as we have free desc for tx
987 */
988 __netif_tx_lock(netif_txq, smp_processor_id());
989 if (netif_running(ndev) &&
990 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS))
991 netif_tx_wake_queue(netif_txq);
992
993 __netif_tx_unlock(netif_txq);
994 }
995 }
996
am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common * common,int chn,unsigned int budget)997 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common,
998 int chn, unsigned int budget)
999 {
1000 struct device *dev = common->dev;
1001 struct am65_cpsw_tx_chn *tx_chn;
1002 struct netdev_queue *netif_txq;
1003 unsigned int total_bytes = 0;
1004 struct net_device *ndev;
1005 struct sk_buff *skb;
1006 dma_addr_t desc_dma;
1007 int res, num_tx = 0;
1008
1009 tx_chn = &common->tx_chns[chn];
1010
1011 while (true) {
1012 spin_lock(&tx_chn->lock);
1013 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma);
1014 spin_unlock(&tx_chn->lock);
1015 if (res == -ENODATA)
1016 break;
1017
1018 if (cppi5_desc_is_tdcm(desc_dma)) {
1019 if (atomic_dec_and_test(&common->tdown_cnt))
1020 complete(&common->tdown_complete);
1021 break;
1022 }
1023
1024 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma);
1025 total_bytes = skb->len;
1026 ndev = skb->dev;
1027 napi_consume_skb(skb, budget);
1028 num_tx++;
1029
1030 netif_txq = netdev_get_tx_queue(ndev, chn);
1031
1032 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes);
1033
1034 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq);
1035 }
1036
1037 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx);
1038
1039 return num_tx;
1040 }
1041
am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common * common,int chn,unsigned int budget)1042 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common,
1043 int chn, unsigned int budget)
1044 {
1045 struct device *dev = common->dev;
1046 struct am65_cpsw_tx_chn *tx_chn;
1047 struct netdev_queue *netif_txq;
1048 unsigned int total_bytes = 0;
1049 struct net_device *ndev;
1050 struct sk_buff *skb;
1051 dma_addr_t desc_dma;
1052 int res, num_tx = 0;
1053
1054 tx_chn = &common->tx_chns[chn];
1055
1056 while (true) {
1057 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma);
1058 if (res == -ENODATA)
1059 break;
1060
1061 if (cppi5_desc_is_tdcm(desc_dma)) {
1062 if (atomic_dec_and_test(&common->tdown_cnt))
1063 complete(&common->tdown_complete);
1064 break;
1065 }
1066
1067 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma);
1068
1069 ndev = skb->dev;
1070 total_bytes += skb->len;
1071 napi_consume_skb(skb, budget);
1072 num_tx++;
1073 }
1074
1075 if (!num_tx)
1076 return 0;
1077
1078 netif_txq = netdev_get_tx_queue(ndev, chn);
1079
1080 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes);
1081
1082 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq);
1083
1084 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx);
1085
1086 return num_tx;
1087 }
1088
am65_cpsw_nuss_tx_poll(struct napi_struct * napi_tx,int budget)1089 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget)
1090 {
1091 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx);
1092 int num_tx;
1093
1094 if (AM65_CPSW_IS_CPSW2G(tx_chn->common))
1095 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, budget);
1096 else
1097 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, budget);
1098
1099 if (num_tx >= budget)
1100 return budget;
1101
1102 if (napi_complete_done(napi_tx, num_tx))
1103 enable_irq(tx_chn->irq);
1104
1105 return 0;
1106 }
1107
am65_cpsw_nuss_rx_irq(int irq,void * dev_id)1108 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id)
1109 {
1110 struct am65_cpsw_common *common = dev_id;
1111
1112 common->rx_irq_disabled = true;
1113 disable_irq_nosync(irq);
1114 napi_schedule(&common->napi_rx);
1115
1116 return IRQ_HANDLED;
1117 }
1118
am65_cpsw_nuss_tx_irq(int irq,void * dev_id)1119 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id)
1120 {
1121 struct am65_cpsw_tx_chn *tx_chn = dev_id;
1122
1123 disable_irq_nosync(irq);
1124 napi_schedule(&tx_chn->napi_tx);
1125
1126 return IRQ_HANDLED;
1127 }
1128
am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff * skb,struct net_device * ndev)1129 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb,
1130 struct net_device *ndev)
1131 {
1132 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
1133 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc;
1134 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1135 struct device *dev = common->dev;
1136 struct am65_cpsw_tx_chn *tx_chn;
1137 struct netdev_queue *netif_txq;
1138 dma_addr_t desc_dma, buf_dma;
1139 int ret, q_idx, i;
1140 void **swdata;
1141 u32 *psdata;
1142 u32 pkt_len;
1143
1144 /* padding enabled in hw */
1145 pkt_len = skb_headlen(skb);
1146
1147 /* SKB TX timestamp */
1148 if (port->tx_ts_enabled)
1149 am65_cpts_prep_tx_timestamp(common->cpts, skb);
1150
1151 q_idx = skb_get_queue_mapping(skb);
1152 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx);
1153
1154 tx_chn = &common->tx_chns[q_idx];
1155 netif_txq = netdev_get_tx_queue(ndev, q_idx);
1156
1157 /* Map the linear buffer */
1158 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len,
1159 DMA_TO_DEVICE);
1160 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) {
1161 dev_err(dev, "Failed to map tx skb buffer\n");
1162 ndev->stats.tx_errors++;
1163 goto err_free_skb;
1164 }
1165
1166 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool);
1167 if (!first_desc) {
1168 dev_dbg(dev, "Failed to allocate descriptor\n");
1169 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len,
1170 DMA_TO_DEVICE);
1171 goto busy_stop_q;
1172 }
1173
1174 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT,
1175 AM65_CPSW_NAV_PS_DATA_SIZE);
1176 cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF);
1177 cppi5_hdesc_set_pkttype(first_desc, 0x7);
1178 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id);
1179
1180 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma);
1181 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len);
1182 swdata = cppi5_hdesc_get_swdata(first_desc);
1183 *(swdata) = skb;
1184 psdata = cppi5_hdesc_get_psdata(first_desc);
1185
1186 /* HW csum offload if enabled */
1187 psdata[2] = 0;
1188 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1189 unsigned int cs_start, cs_offset;
1190
1191 cs_start = skb_transport_offset(skb);
1192 cs_offset = cs_start + skb->csum_offset;
1193 /* HW numerates bytes starting from 1 */
1194 psdata[2] = ((cs_offset + 1) << 24) |
1195 ((cs_start + 1) << 16) | (skb->len - cs_start);
1196 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]);
1197 }
1198
1199 if (!skb_is_nonlinear(skb))
1200 goto done_tx;
1201
1202 dev_dbg(dev, "fragmented SKB\n");
1203
1204 /* Handle the case where skb is fragmented in pages */
1205 cur_desc = first_desc;
1206 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1207 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1208 u32 frag_size = skb_frag_size(frag);
1209
1210 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool);
1211 if (!next_desc) {
1212 dev_err(dev, "Failed to allocate descriptor\n");
1213 goto busy_free_descs;
1214 }
1215
1216 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size,
1217 DMA_TO_DEVICE);
1218 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) {
1219 dev_err(dev, "Failed to map tx skb page\n");
1220 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc);
1221 ndev->stats.tx_errors++;
1222 goto err_free_descs;
1223 }
1224
1225 cppi5_hdesc_reset_hbdesc(next_desc);
1226 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma);
1227 cppi5_hdesc_attach_buf(next_desc,
1228 buf_dma, frag_size, buf_dma, frag_size);
1229
1230 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool,
1231 next_desc);
1232 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma);
1233 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma);
1234
1235 pkt_len += frag_size;
1236 cur_desc = next_desc;
1237 }
1238 WARN_ON(pkt_len != skb->len);
1239
1240 done_tx:
1241 skb_tx_timestamp(skb);
1242
1243 /* report bql before sending packet */
1244 netdev_tx_sent_queue(netif_txq, pkt_len);
1245
1246 cppi5_hdesc_set_pktlen(first_desc, pkt_len);
1247 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc);
1248 if (AM65_CPSW_IS_CPSW2G(common)) {
1249 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma);
1250 } else {
1251 spin_lock_bh(&tx_chn->lock);
1252 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma);
1253 spin_unlock_bh(&tx_chn->lock);
1254 }
1255 if (ret) {
1256 dev_err(dev, "can't push desc %d\n", ret);
1257 /* inform bql */
1258 netdev_tx_completed_queue(netif_txq, 1, pkt_len);
1259 ndev->stats.tx_errors++;
1260 goto err_free_descs;
1261 }
1262
1263 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) {
1264 netif_tx_stop_queue(netif_txq);
1265 /* Barrier, so that stop_queue visible to other cpus */
1266 smp_mb__after_atomic();
1267 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx);
1268
1269 /* re-check for smp */
1270 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >=
1271 MAX_SKB_FRAGS) {
1272 netif_tx_wake_queue(netif_txq);
1273 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx);
1274 }
1275 }
1276
1277 return NETDEV_TX_OK;
1278
1279 err_free_descs:
1280 am65_cpsw_nuss_xmit_free(tx_chn, first_desc);
1281 err_free_skb:
1282 ndev->stats.tx_dropped++;
1283 dev_kfree_skb_any(skb);
1284 return NETDEV_TX_OK;
1285
1286 busy_free_descs:
1287 am65_cpsw_nuss_xmit_free(tx_chn, first_desc);
1288 busy_stop_q:
1289 netif_tx_stop_queue(netif_txq);
1290 return NETDEV_TX_BUSY;
1291 }
1292
am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device * ndev,void * addr)1293 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev,
1294 void *addr)
1295 {
1296 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
1297 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1298 struct sockaddr *sockaddr = (struct sockaddr *)addr;
1299 int ret;
1300
1301 ret = eth_prepare_mac_addr_change(ndev, addr);
1302 if (ret < 0)
1303 return ret;
1304
1305 ret = pm_runtime_get_sync(common->dev);
1306 if (ret < 0) {
1307 pm_runtime_put_noidle(common->dev);
1308 return ret;
1309 }
1310
1311 cpsw_ale_del_ucast(common->ale, ndev->dev_addr,
1312 HOST_PORT_NUM, 0, 0);
1313 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data,
1314 HOST_PORT_NUM, ALE_SECURE, 0);
1315
1316 am65_cpsw_port_set_sl_mac(port, addr);
1317 eth_commit_mac_addr_change(ndev, sockaddr);
1318
1319 pm_runtime_put(common->dev);
1320
1321 return 0;
1322 }
1323
am65_cpsw_nuss_hwtstamp_set(struct net_device * ndev,struct ifreq * ifr)1324 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev,
1325 struct ifreq *ifr)
1326 {
1327 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
1328 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1329 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype;
1330 struct hwtstamp_config cfg;
1331
1332 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS))
1333 return -EOPNOTSUPP;
1334
1335 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1336 return -EFAULT;
1337
1338 /* TX HW timestamp */
1339 switch (cfg.tx_type) {
1340 case HWTSTAMP_TX_OFF:
1341 case HWTSTAMP_TX_ON:
1342 break;
1343 default:
1344 return -ERANGE;
1345 }
1346
1347 switch (cfg.rx_filter) {
1348 case HWTSTAMP_FILTER_NONE:
1349 port->rx_ts_enabled = false;
1350 break;
1351 case HWTSTAMP_FILTER_ALL:
1352 case HWTSTAMP_FILTER_SOME:
1353 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1354 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1355 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1356 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1357 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1358 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1359 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1360 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1361 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1362 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1363 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1364 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1365 case HWTSTAMP_FILTER_NTP_ALL:
1366 port->rx_ts_enabled = true;
1367 cfg.rx_filter = HWTSTAMP_FILTER_ALL;
1368 break;
1369 default:
1370 return -ERANGE;
1371 }
1372
1373 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON);
1374
1375 /* cfg TX timestamp */
1376 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET <<
1377 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588;
1378
1379 ts_vlan_ltype = ETH_P_8021Q;
1380
1381 ts_ctrl_ltype2 = ETH_P_1588 |
1382 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 |
1383 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 |
1384 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 |
1385 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 |
1386 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 |
1387 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 |
1388 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 |
1389 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO;
1390
1391 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS <<
1392 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT;
1393
1394 if (port->tx_ts_enabled)
1395 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN |
1396 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN;
1397
1398 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG);
1399 writel(ts_vlan_ltype, port->port_base +
1400 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG);
1401 writel(ts_ctrl_ltype2, port->port_base +
1402 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2);
1403 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL);
1404
1405 /* en/dis RX timestamp */
1406 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled);
1407
1408 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1409 }
1410
am65_cpsw_nuss_hwtstamp_get(struct net_device * ndev,struct ifreq * ifr)1411 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev,
1412 struct ifreq *ifr)
1413 {
1414 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1415 struct hwtstamp_config cfg;
1416
1417 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS))
1418 return -EOPNOTSUPP;
1419
1420 cfg.flags = 0;
1421 cfg.tx_type = port->tx_ts_enabled ?
1422 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1423 cfg.rx_filter = port->rx_ts_enabled ?
1424 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE;
1425
1426 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1427 }
1428
am65_cpsw_nuss_ndo_slave_ioctl(struct net_device * ndev,struct ifreq * req,int cmd)1429 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev,
1430 struct ifreq *req, int cmd)
1431 {
1432 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1433
1434 if (!netif_running(ndev))
1435 return -EINVAL;
1436
1437 switch (cmd) {
1438 case SIOCSHWTSTAMP:
1439 return am65_cpsw_nuss_hwtstamp_set(ndev, req);
1440 case SIOCGHWTSTAMP:
1441 return am65_cpsw_nuss_hwtstamp_get(ndev, req);
1442 }
1443
1444 if (!port->slave.phy)
1445 return -EOPNOTSUPP;
1446
1447 return phy_mii_ioctl(port->slave.phy, req, cmd);
1448 }
1449
am65_cpsw_nuss_ndo_get_stats(struct net_device * dev,struct rtnl_link_stats64 * stats)1450 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev,
1451 struct rtnl_link_stats64 *stats)
1452 {
1453 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev);
1454 unsigned int start;
1455 int cpu;
1456
1457 for_each_possible_cpu(cpu) {
1458 struct am65_cpsw_ndev_stats *cpu_stats;
1459 u64 rx_packets;
1460 u64 rx_bytes;
1461 u64 tx_packets;
1462 u64 tx_bytes;
1463
1464 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu);
1465 do {
1466 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
1467 rx_packets = cpu_stats->rx_packets;
1468 rx_bytes = cpu_stats->rx_bytes;
1469 tx_packets = cpu_stats->tx_packets;
1470 tx_bytes = cpu_stats->tx_bytes;
1471 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
1472
1473 stats->rx_packets += rx_packets;
1474 stats->rx_bytes += rx_bytes;
1475 stats->tx_packets += tx_packets;
1476 stats->tx_bytes += tx_bytes;
1477 }
1478
1479 stats->rx_errors = dev->stats.rx_errors;
1480 stats->rx_dropped = dev->stats.rx_dropped;
1481 stats->tx_dropped = dev->stats.tx_dropped;
1482 }
1483
am65_cpsw_ndo_get_devlink_port(struct net_device * ndev)1484 static struct devlink_port *am65_cpsw_ndo_get_devlink_port(struct net_device *ndev)
1485 {
1486 struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
1487
1488 return &port->devlink_port;
1489 }
1490
1491 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = {
1492 .ndo_open = am65_cpsw_nuss_ndo_slave_open,
1493 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop,
1494 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit,
1495 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode,
1496 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats,
1497 .ndo_validate_addr = eth_validate_addr,
1498 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address,
1499 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout,
1500 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid,
1501 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid,
1502 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl,
1503 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc,
1504 .ndo_get_devlink_port = am65_cpsw_ndo_get_devlink_port,
1505 };
1506
am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port * port)1507 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port)
1508 {
1509 struct am65_cpsw_common *common = port->common;
1510
1511 if (!port->disabled)
1512 return;
1513
1514 cpsw_ale_control_set(common->ale, port->port_id,
1515 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1516
1517 cpsw_sl_reset(port->slave.mac_sl, 100);
1518 cpsw_sl_ctl_reset(port->slave.mac_sl);
1519 }
1520
am65_cpsw_nuss_free_tx_chns(void * data)1521 static void am65_cpsw_nuss_free_tx_chns(void *data)
1522 {
1523 struct am65_cpsw_common *common = data;
1524 int i;
1525
1526 for (i = 0; i < common->tx_ch_num; i++) {
1527 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i];
1528
1529 if (!IS_ERR_OR_NULL(tx_chn->desc_pool))
1530 k3_cppi_desc_pool_destroy(tx_chn->desc_pool);
1531
1532 if (!IS_ERR_OR_NULL(tx_chn->tx_chn))
1533 k3_udma_glue_release_tx_chn(tx_chn->tx_chn);
1534
1535 memset(tx_chn, 0, sizeof(*tx_chn));
1536 }
1537 }
1538
am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common * common)1539 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common)
1540 {
1541 struct device *dev = common->dev;
1542 int i;
1543
1544 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common);
1545
1546 for (i = 0; i < common->tx_ch_num; i++) {
1547 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i];
1548
1549 if (tx_chn->irq)
1550 devm_free_irq(dev, tx_chn->irq, tx_chn);
1551
1552 netif_napi_del(&tx_chn->napi_tx);
1553
1554 if (!IS_ERR_OR_NULL(tx_chn->desc_pool))
1555 k3_cppi_desc_pool_destroy(tx_chn->desc_pool);
1556
1557 if (!IS_ERR_OR_NULL(tx_chn->tx_chn))
1558 k3_udma_glue_release_tx_chn(tx_chn->tx_chn);
1559
1560 memset(tx_chn, 0, sizeof(*tx_chn));
1561 }
1562 }
1563
am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common * common)1564 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common)
1565 {
1566 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS);
1567 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 };
1568 struct device *dev = common->dev;
1569 struct k3_ring_cfg ring_cfg = {
1570 .elm_size = K3_RINGACC_RING_ELSIZE_8,
1571 .mode = K3_RINGACC_RING_MODE_RING,
1572 .flags = 0
1573 };
1574 u32 hdesc_size;
1575 int i, ret = 0;
1576
1577 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE,
1578 AM65_CPSW_NAV_SW_DATA_SIZE);
1579
1580 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE;
1581 tx_cfg.tx_cfg = ring_cfg;
1582 tx_cfg.txcq_cfg = ring_cfg;
1583 tx_cfg.tx_cfg.size = max_desc_num;
1584 tx_cfg.txcq_cfg.size = max_desc_num;
1585
1586 for (i = 0; i < common->tx_ch_num; i++) {
1587 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i];
1588
1589 snprintf(tx_chn->tx_chn_name,
1590 sizeof(tx_chn->tx_chn_name), "tx%d", i);
1591
1592 spin_lock_init(&tx_chn->lock);
1593 tx_chn->common = common;
1594 tx_chn->id = i;
1595 tx_chn->descs_num = max_desc_num;
1596
1597 tx_chn->tx_chn =
1598 k3_udma_glue_request_tx_chn(dev,
1599 tx_chn->tx_chn_name,
1600 &tx_cfg);
1601 if (IS_ERR(tx_chn->tx_chn)) {
1602 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn),
1603 "Failed to request tx dma channel\n");
1604 goto err;
1605 }
1606 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn);
1607
1608 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev,
1609 tx_chn->descs_num,
1610 hdesc_size,
1611 tx_chn->tx_chn_name);
1612 if (IS_ERR(tx_chn->desc_pool)) {
1613 ret = PTR_ERR(tx_chn->desc_pool);
1614 dev_err(dev, "Failed to create poll %d\n", ret);
1615 goto err;
1616 }
1617
1618 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn);
1619 if (tx_chn->irq <= 0) {
1620 dev_err(dev, "Failed to get tx dma irq %d\n",
1621 tx_chn->irq);
1622 ret = tx_chn->irq ?: -ENXIO;
1623 goto err;
1624 }
1625
1626 snprintf(tx_chn->tx_chn_name,
1627 sizeof(tx_chn->tx_chn_name), "%s-tx%d",
1628 dev_name(dev), tx_chn->id);
1629 }
1630
1631 err:
1632 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common);
1633 if (i) {
1634 dev_err(dev, "Failed to add free_tx_chns action %d\n", i);
1635 return i;
1636 }
1637
1638 return ret;
1639 }
1640
am65_cpsw_nuss_free_rx_chns(void * data)1641 static void am65_cpsw_nuss_free_rx_chns(void *data)
1642 {
1643 struct am65_cpsw_common *common = data;
1644 struct am65_cpsw_rx_chn *rx_chn;
1645
1646 rx_chn = &common->rx_chns;
1647
1648 if (!IS_ERR_OR_NULL(rx_chn->desc_pool))
1649 k3_cppi_desc_pool_destroy(rx_chn->desc_pool);
1650
1651 if (!IS_ERR_OR_NULL(rx_chn->rx_chn))
1652 k3_udma_glue_release_rx_chn(rx_chn->rx_chn);
1653 }
1654
am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common * common)1655 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common)
1656 {
1657 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns;
1658 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 };
1659 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC;
1660 struct device *dev = common->dev;
1661 u32 hdesc_size;
1662 u32 fdqring_id;
1663 int i, ret = 0;
1664
1665 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE,
1666 AM65_CPSW_NAV_SW_DATA_SIZE);
1667
1668 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE;
1669 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS;
1670 rx_cfg.flow_id_base = common->rx_flow_id_base;
1671
1672 /* init all flows */
1673 rx_chn->dev = dev;
1674 rx_chn->descs_num = max_desc_num;
1675
1676 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg);
1677 if (IS_ERR(rx_chn->rx_chn)) {
1678 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn),
1679 "Failed to request rx dma channel\n");
1680 goto err;
1681 }
1682 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn);
1683
1684 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev,
1685 rx_chn->descs_num,
1686 hdesc_size, "rx");
1687 if (IS_ERR(rx_chn->desc_pool)) {
1688 ret = PTR_ERR(rx_chn->desc_pool);
1689 dev_err(dev, "Failed to create rx poll %d\n", ret);
1690 goto err;
1691 }
1692
1693 common->rx_flow_id_base =
1694 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn);
1695 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base);
1696
1697 fdqring_id = K3_RINGACC_RING_ID_ANY;
1698 for (i = 0; i < rx_cfg.flow_id_num; i++) {
1699 struct k3_ring_cfg rxring_cfg = {
1700 .elm_size = K3_RINGACC_RING_ELSIZE_8,
1701 .mode = K3_RINGACC_RING_MODE_RING,
1702 .flags = 0,
1703 };
1704 struct k3_ring_cfg fdqring_cfg = {
1705 .elm_size = K3_RINGACC_RING_ELSIZE_8,
1706 .flags = K3_RINGACC_RING_SHARED,
1707 };
1708 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = {
1709 .rx_cfg = rxring_cfg,
1710 .rxfdq_cfg = fdqring_cfg,
1711 .ring_rxq_id = K3_RINGACC_RING_ID_ANY,
1712 .src_tag_lo_sel =
1713 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG,
1714 };
1715
1716 rx_flow_cfg.ring_rxfdq0_id = fdqring_id;
1717 rx_flow_cfg.rx_cfg.size = max_desc_num;
1718 rx_flow_cfg.rxfdq_cfg.size = max_desc_num;
1719 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode;
1720
1721 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn,
1722 i, &rx_flow_cfg);
1723 if (ret) {
1724 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret);
1725 goto err;
1726 }
1727 if (!i)
1728 fdqring_id =
1729 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn,
1730 i);
1731
1732 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i);
1733
1734 if (rx_chn->irq <= 0) {
1735 dev_err(dev, "Failed to get rx dma irq %d\n",
1736 rx_chn->irq);
1737 ret = -ENXIO;
1738 goto err;
1739 }
1740 }
1741
1742 err:
1743 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common);
1744 if (i) {
1745 dev_err(dev, "Failed to add free_rx_chns action %d\n", i);
1746 return i;
1747 }
1748
1749 return ret;
1750 }
1751
am65_cpsw_nuss_init_host_p(struct am65_cpsw_common * common)1752 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common)
1753 {
1754 struct am65_cpsw_host *host_p = am65_common_get_host(common);
1755
1756 host_p->common = common;
1757 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE;
1758 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE;
1759
1760 return 0;
1761 }
1762
am65_cpsw_am654_get_efuse_macid(struct device_node * of_node,int slave,u8 * mac_addr)1763 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node,
1764 int slave, u8 *mac_addr)
1765 {
1766 u32 mac_lo, mac_hi, offset;
1767 struct regmap *syscon;
1768 int ret;
1769
1770 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse");
1771 if (IS_ERR(syscon)) {
1772 if (PTR_ERR(syscon) == -ENODEV)
1773 return 0;
1774 return PTR_ERR(syscon);
1775 }
1776
1777 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1,
1778 &offset);
1779 if (ret)
1780 return ret;
1781
1782 regmap_read(syscon, offset, &mac_lo);
1783 regmap_read(syscon, offset + 4, &mac_hi);
1784
1785 mac_addr[0] = (mac_hi >> 8) & 0xff;
1786 mac_addr[1] = mac_hi & 0xff;
1787 mac_addr[2] = (mac_lo >> 24) & 0xff;
1788 mac_addr[3] = (mac_lo >> 16) & 0xff;
1789 mac_addr[4] = (mac_lo >> 8) & 0xff;
1790 mac_addr[5] = mac_lo & 0xff;
1791
1792 return 0;
1793 }
1794
am65_cpsw_init_cpts(struct am65_cpsw_common * common)1795 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common)
1796 {
1797 struct device *dev = common->dev;
1798 struct device_node *node;
1799 struct am65_cpts *cpts;
1800 void __iomem *reg_base;
1801
1802 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS))
1803 return 0;
1804
1805 node = of_get_child_by_name(dev->of_node, "cpts");
1806 if (!node) {
1807 dev_err(dev, "%s cpts not found\n", __func__);
1808 return -ENOENT;
1809 }
1810
1811 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE;
1812 cpts = am65_cpts_create(dev, reg_base, node);
1813 if (IS_ERR(cpts)) {
1814 int ret = PTR_ERR(cpts);
1815
1816 of_node_put(node);
1817 if (ret == -EOPNOTSUPP) {
1818 dev_info(dev, "cpts disabled\n");
1819 return 0;
1820 }
1821
1822 dev_err(dev, "cpts create err %d\n", ret);
1823 return ret;
1824 }
1825 common->cpts = cpts;
1826 /* Forbid PM runtime if CPTS is running.
1827 * K3 CPSWxG modules may completely lose context during ON->OFF
1828 * transitions depending on integration.
1829 * AM65x/J721E MCU CPSW2G: false
1830 * J721E MAIN_CPSW9G: true
1831 */
1832 pm_runtime_forbid(dev);
1833
1834 return 0;
1835 }
1836
am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common * common)1837 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common)
1838 {
1839 struct device_node *node, *port_np;
1840 struct device *dev = common->dev;
1841 int ret;
1842
1843 node = of_get_child_by_name(dev->of_node, "ethernet-ports");
1844 if (!node)
1845 return -ENOENT;
1846
1847 for_each_child_of_node(node, port_np) {
1848 struct am65_cpsw_port *port;
1849 u32 port_id;
1850
1851 /* it is not a slave port node, continue */
1852 if (strcmp(port_np->name, "port"))
1853 continue;
1854
1855 ret = of_property_read_u32(port_np, "reg", &port_id);
1856 if (ret < 0) {
1857 dev_err(dev, "%pOF error reading port_id %d\n",
1858 port_np, ret);
1859 return ret;
1860 }
1861
1862 if (!port_id || port_id > common->port_num) {
1863 dev_err(dev, "%pOF has invalid port_id %u %s\n",
1864 port_np, port_id, port_np->name);
1865 return -EINVAL;
1866 }
1867
1868 port = am65_common_get_port(common, port_id);
1869 port->port_id = port_id;
1870 port->common = common;
1871 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE +
1872 AM65_CPSW_NU_PORTS_OFFSET * (port_id);
1873 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE +
1874 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id);
1875 port->name = of_get_property(port_np, "label", NULL);
1876 port->fetch_ram_base =
1877 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE +
1878 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1));
1879
1880 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base);
1881 if (IS_ERR(port->slave.mac_sl))
1882 return PTR_ERR(port->slave.mac_sl);
1883
1884 port->disabled = !of_device_is_available(port_np);
1885 if (port->disabled) {
1886 common->disabled_ports_mask |= BIT(port->port_id);
1887 continue;
1888 }
1889
1890 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL);
1891 if (IS_ERR(port->slave.ifphy)) {
1892 ret = PTR_ERR(port->slave.ifphy);
1893 dev_err(dev, "%pOF error retrieving port phy: %d\n",
1894 port_np, ret);
1895 return ret;
1896 }
1897
1898 port->slave.mac_only =
1899 of_property_read_bool(port_np, "ti,mac-only");
1900
1901 /* get phy/link info */
1902 if (of_phy_is_fixed_link(port_np)) {
1903 ret = of_phy_register_fixed_link(port_np);
1904 if (ret)
1905 return dev_err_probe(dev, ret,
1906 "failed to register fixed-link phy %pOF\n",
1907 port_np);
1908 port->slave.phy_node = of_node_get(port_np);
1909 } else {
1910 port->slave.phy_node =
1911 of_parse_phandle(port_np, "phy-handle", 0);
1912 }
1913
1914 if (!port->slave.phy_node) {
1915 dev_err(dev,
1916 "slave[%d] no phy found\n", port_id);
1917 return -ENODEV;
1918 }
1919
1920 ret = of_get_phy_mode(port_np, &port->slave.phy_if);
1921 if (ret) {
1922 dev_err(dev, "%pOF read phy-mode err %d\n",
1923 port_np, ret);
1924 return ret;
1925 }
1926
1927 ret = of_get_mac_address(port_np, port->slave.mac_addr);
1928 if (ret) {
1929 am65_cpsw_am654_get_efuse_macid(port_np,
1930 port->port_id,
1931 port->slave.mac_addr);
1932 if (!is_valid_ether_addr(port->slave.mac_addr)) {
1933 random_ether_addr(port->slave.mac_addr);
1934 dev_err(dev, "Use random MAC address\n");
1935 }
1936 }
1937 }
1938 of_node_put(node);
1939
1940 /* is there at least one ext.port */
1941 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) {
1942 dev_err(dev, "No Ext. port are available\n");
1943 return -ENODEV;
1944 }
1945
1946 return 0;
1947 }
1948
am65_cpsw_pcpu_stats_free(void * data)1949 static void am65_cpsw_pcpu_stats_free(void *data)
1950 {
1951 struct am65_cpsw_ndev_stats __percpu *stats = data;
1952
1953 free_percpu(stats);
1954 }
1955
1956 static int
am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common * common,u32 port_idx)1957 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx)
1958 {
1959 struct am65_cpsw_ndev_priv *ndev_priv;
1960 struct device *dev = common->dev;
1961 struct am65_cpsw_port *port;
1962 int ret;
1963
1964 port = &common->ports[port_idx];
1965
1966 if (port->disabled)
1967 return 0;
1968
1969 /* alloc netdev */
1970 port->ndev = devm_alloc_etherdev_mqs(common->dev,
1971 sizeof(struct am65_cpsw_ndev_priv),
1972 AM65_CPSW_MAX_TX_QUEUES,
1973 AM65_CPSW_MAX_RX_QUEUES);
1974 if (!port->ndev) {
1975 dev_err(dev, "error allocating slave net_device %u\n",
1976 port->port_id);
1977 return -ENOMEM;
1978 }
1979
1980 ndev_priv = netdev_priv(port->ndev);
1981 ndev_priv->port = port;
1982 ndev_priv->msg_enable = AM65_CPSW_DEBUG;
1983 SET_NETDEV_DEV(port->ndev, dev);
1984
1985 eth_hw_addr_set(port->ndev, port->slave.mac_addr);
1986
1987 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE;
1988 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE -
1989 (VLAN_ETH_HLEN + ETH_FCS_LEN);
1990 port->ndev->hw_features = NETIF_F_SG |
1991 NETIF_F_RXCSUM |
1992 NETIF_F_HW_CSUM |
1993 NETIF_F_HW_TC;
1994 port->ndev->features = port->ndev->hw_features |
1995 NETIF_F_HW_VLAN_CTAG_FILTER;
1996 port->ndev->vlan_features |= NETIF_F_SG;
1997 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops;
1998 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave;
1999
2000 /* Disable TX checksum offload by default due to HW bug */
2001 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM)
2002 port->ndev->features &= ~NETIF_F_HW_CSUM;
2003
2004 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats);
2005 if (!ndev_priv->stats)
2006 return -ENOMEM;
2007
2008 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free,
2009 ndev_priv->stats);
2010 if (ret)
2011 dev_err(dev, "failed to add percpu stat free action %d\n", ret);
2012
2013 if (!common->dma_ndev)
2014 common->dma_ndev = port->ndev;
2015
2016 return ret;
2017 }
2018
am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common * common)2019 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common)
2020 {
2021 int ret;
2022 int i;
2023
2024 for (i = 0; i < common->port_num; i++) {
2025 ret = am65_cpsw_nuss_init_port_ndev(common, i);
2026 if (ret)
2027 return ret;
2028 }
2029
2030 netif_napi_add(common->dma_ndev, &common->napi_rx,
2031 am65_cpsw_nuss_rx_poll, NAPI_POLL_WEIGHT);
2032
2033 return ret;
2034 }
2035
am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common * common)2036 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common)
2037 {
2038 struct device *dev = common->dev;
2039 int i, ret = 0;
2040
2041 for (i = 0; i < common->tx_ch_num; i++) {
2042 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i];
2043
2044 netif_tx_napi_add(common->dma_ndev, &tx_chn->napi_tx,
2045 am65_cpsw_nuss_tx_poll, NAPI_POLL_WEIGHT);
2046
2047 ret = devm_request_irq(dev, tx_chn->irq,
2048 am65_cpsw_nuss_tx_irq,
2049 IRQF_TRIGGER_HIGH,
2050 tx_chn->tx_chn_name, tx_chn);
2051 if (ret) {
2052 dev_err(dev, "failure requesting tx%u irq %u, %d\n",
2053 tx_chn->id, tx_chn->irq, ret);
2054 goto err;
2055 }
2056 }
2057
2058 err:
2059 return ret;
2060 }
2061
am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common * common)2062 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common)
2063 {
2064 struct am65_cpsw_port *port;
2065 int i;
2066
2067 for (i = 0; i < common->port_num; i++) {
2068 port = &common->ports[i];
2069 if (port->ndev && port->ndev->reg_state == NETREG_REGISTERED)
2070 unregister_netdev(port->ndev);
2071 }
2072 }
2073
am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common * common)2074 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common)
2075 {
2076 int set_val = 0;
2077 int i;
2078
2079 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask))
2080 set_val = 1;
2081
2082 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val);
2083
2084 for (i = 1; i <= common->port_num; i++) {
2085 struct am65_cpsw_port *port = am65_common_get_port(common, i);
2086 struct am65_cpsw_ndev_priv *priv;
2087
2088 if (!port->ndev)
2089 continue;
2090
2091 priv = am65_ndev_to_priv(port->ndev);
2092 priv->offload_fwd_mark = set_val;
2093 }
2094 }
2095
am65_cpsw_port_dev_check(const struct net_device * ndev)2096 bool am65_cpsw_port_dev_check(const struct net_device *ndev)
2097 {
2098 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) {
2099 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
2100
2101 return !common->is_emac_mode;
2102 }
2103
2104 return false;
2105 }
2106
am65_cpsw_netdevice_port_link(struct net_device * ndev,struct net_device * br_ndev,struct netlink_ext_ack * extack)2107 static int am65_cpsw_netdevice_port_link(struct net_device *ndev,
2108 struct net_device *br_ndev,
2109 struct netlink_ext_ack *extack)
2110 {
2111 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
2112 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev);
2113 int err;
2114
2115 if (!common->br_members) {
2116 common->hw_bridge_dev = br_ndev;
2117 } else {
2118 /* This is adding the port to a second bridge, this is
2119 * unsupported
2120 */
2121 if (common->hw_bridge_dev != br_ndev)
2122 return -EOPNOTSUPP;
2123 }
2124
2125 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL,
2126 false, extack);
2127 if (err)
2128 return err;
2129
2130 common->br_members |= BIT(priv->port->port_id);
2131
2132 am65_cpsw_port_offload_fwd_mark_update(common);
2133
2134 return NOTIFY_DONE;
2135 }
2136
am65_cpsw_netdevice_port_unlink(struct net_device * ndev)2137 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev)
2138 {
2139 struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
2140 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev);
2141
2142 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL);
2143
2144 common->br_members &= ~BIT(priv->port->port_id);
2145
2146 am65_cpsw_port_offload_fwd_mark_update(common);
2147
2148 if (!common->br_members)
2149 common->hw_bridge_dev = NULL;
2150 }
2151
2152 /* netdev notifier */
am65_cpsw_netdevice_event(struct notifier_block * unused,unsigned long event,void * ptr)2153 static int am65_cpsw_netdevice_event(struct notifier_block *unused,
2154 unsigned long event, void *ptr)
2155 {
2156 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr);
2157 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
2158 struct netdev_notifier_changeupper_info *info;
2159 int ret = NOTIFY_DONE;
2160
2161 if (!am65_cpsw_port_dev_check(ndev))
2162 return NOTIFY_DONE;
2163
2164 switch (event) {
2165 case NETDEV_CHANGEUPPER:
2166 info = ptr;
2167
2168 if (netif_is_bridge_master(info->upper_dev)) {
2169 if (info->linking)
2170 ret = am65_cpsw_netdevice_port_link(ndev,
2171 info->upper_dev,
2172 extack);
2173 else
2174 am65_cpsw_netdevice_port_unlink(ndev);
2175 }
2176 break;
2177 default:
2178 return NOTIFY_DONE;
2179 }
2180
2181 return notifier_from_errno(ret);
2182 }
2183
am65_cpsw_register_notifiers(struct am65_cpsw_common * cpsw)2184 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw)
2185 {
2186 int ret = 0;
2187
2188 if (AM65_CPSW_IS_CPSW2G(cpsw) ||
2189 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV))
2190 return 0;
2191
2192 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event;
2193 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb);
2194 if (ret) {
2195 dev_err(cpsw->dev, "can't register netdevice notifier\n");
2196 return ret;
2197 }
2198
2199 ret = am65_cpsw_switchdev_register_notifiers(cpsw);
2200 if (ret)
2201 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb);
2202
2203 return ret;
2204 }
2205
am65_cpsw_unregister_notifiers(struct am65_cpsw_common * cpsw)2206 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw)
2207 {
2208 if (AM65_CPSW_IS_CPSW2G(cpsw) ||
2209 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV))
2210 return;
2211
2212 am65_cpsw_switchdev_unregister_notifiers(cpsw);
2213 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb);
2214 }
2215
2216 static const struct devlink_ops am65_cpsw_devlink_ops = {};
2217
am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common * cpsw)2218 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw)
2219 {
2220 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0,
2221 ALE_MCAST_BLOCK_LEARN_FWD);
2222 }
2223
am65_cpsw_init_host_port_switch(struct am65_cpsw_common * common)2224 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common)
2225 {
2226 struct am65_cpsw_host *host = am65_common_get_host(common);
2227
2228 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
2229
2230 am65_cpsw_init_stp_ale_entry(common);
2231
2232 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1);
2233 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n");
2234 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0);
2235 }
2236
am65_cpsw_init_host_port_emac(struct am65_cpsw_common * common)2237 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common)
2238 {
2239 struct am65_cpsw_host *host = am65_common_get_host(common);
2240
2241 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
2242
2243 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0);
2244 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n");
2245
2246 /* learning make no sense in multi-mac mode */
2247 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1);
2248 }
2249
am65_cpsw_dl_switch_mode_get(struct devlink * dl,u32 id,struct devlink_param_gset_ctx * ctx)2250 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id,
2251 struct devlink_param_gset_ctx *ctx)
2252 {
2253 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl);
2254 struct am65_cpsw_common *common = dl_priv->common;
2255
2256 dev_dbg(common->dev, "%s id:%u\n", __func__, id);
2257
2258 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE)
2259 return -EOPNOTSUPP;
2260
2261 ctx->val.vbool = !common->is_emac_mode;
2262
2263 return 0;
2264 }
2265
am65_cpsw_init_port_emac_ale(struct am65_cpsw_port * port)2266 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port)
2267 {
2268 struct am65_cpsw_slave_data *slave = &port->slave;
2269 struct am65_cpsw_common *common = port->common;
2270 u32 port_mask;
2271
2272 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
2273
2274 if (slave->mac_only)
2275 /* enable mac-only mode on port */
2276 cpsw_ale_control_set(common->ale, port->port_id,
2277 ALE_PORT_MACONLY, 1);
2278
2279 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1);
2280
2281 port_mask = BIT(port->port_id) | ALE_PORT_HOST;
2282
2283 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr,
2284 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan);
2285 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast,
2286 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2);
2287 }
2288
am65_cpsw_init_port_switch_ale(struct am65_cpsw_port * port)2289 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port)
2290 {
2291 struct am65_cpsw_slave_data *slave = &port->slave;
2292 struct am65_cpsw_common *cpsw = port->common;
2293 u32 port_mask;
2294
2295 cpsw_ale_control_set(cpsw->ale, port->port_id,
2296 ALE_PORT_NOLEARN, 0);
2297
2298 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr,
2299 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN,
2300 slave->port_vlan);
2301
2302 port_mask = BIT(port->port_id) | ALE_PORT_HOST;
2303
2304 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast,
2305 port_mask, ALE_VLAN, slave->port_vlan,
2306 ALE_MCAST_FWD_2);
2307
2308 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET);
2309
2310 cpsw_ale_control_set(cpsw->ale, port->port_id,
2311 ALE_PORT_MACONLY, 0);
2312 }
2313
am65_cpsw_dl_switch_mode_set(struct devlink * dl,u32 id,struct devlink_param_gset_ctx * ctx)2314 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id,
2315 struct devlink_param_gset_ctx *ctx)
2316 {
2317 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl);
2318 struct am65_cpsw_common *cpsw = dl_priv->common;
2319 bool switch_en = ctx->val.vbool;
2320 bool if_running = false;
2321 int i;
2322
2323 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id);
2324
2325 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE)
2326 return -EOPNOTSUPP;
2327
2328 if (switch_en == !cpsw->is_emac_mode)
2329 return 0;
2330
2331 if (!switch_en && cpsw->br_members) {
2332 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n");
2333 return -EINVAL;
2334 }
2335
2336 rtnl_lock();
2337
2338 cpsw->is_emac_mode = !switch_en;
2339
2340 for (i = 0; i < cpsw->port_num; i++) {
2341 struct net_device *sl_ndev = cpsw->ports[i].ndev;
2342
2343 if (!sl_ndev || !netif_running(sl_ndev))
2344 continue;
2345
2346 if_running = true;
2347 }
2348
2349 if (!if_running) {
2350 /* all ndevs are down */
2351 for (i = 0; i < cpsw->port_num; i++) {
2352 struct net_device *sl_ndev = cpsw->ports[i].ndev;
2353 struct am65_cpsw_slave_data *slave;
2354
2355 if (!sl_ndev)
2356 continue;
2357
2358 slave = am65_ndev_to_slave(sl_ndev);
2359 if (switch_en)
2360 slave->port_vlan = cpsw->default_vlan;
2361 else
2362 slave->port_vlan = 0;
2363 }
2364
2365 goto exit;
2366 }
2367
2368 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1);
2369 /* clean up ALE table */
2370 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1);
2371 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT);
2372
2373 if (switch_en) {
2374 dev_info(cpsw->dev, "Enable switch mode\n");
2375
2376 am65_cpsw_init_host_port_switch(cpsw);
2377
2378 for (i = 0; i < cpsw->port_num; i++) {
2379 struct net_device *sl_ndev = cpsw->ports[i].ndev;
2380 struct am65_cpsw_slave_data *slave;
2381 struct am65_cpsw_port *port;
2382
2383 if (!sl_ndev)
2384 continue;
2385
2386 port = am65_ndev_to_port(sl_ndev);
2387 slave = am65_ndev_to_slave(sl_ndev);
2388 slave->port_vlan = cpsw->default_vlan;
2389
2390 if (netif_running(sl_ndev))
2391 am65_cpsw_init_port_switch_ale(port);
2392 }
2393
2394 } else {
2395 dev_info(cpsw->dev, "Disable switch mode\n");
2396
2397 am65_cpsw_init_host_port_emac(cpsw);
2398
2399 for (i = 0; i < cpsw->port_num; i++) {
2400 struct net_device *sl_ndev = cpsw->ports[i].ndev;
2401 struct am65_cpsw_port *port;
2402
2403 if (!sl_ndev)
2404 continue;
2405
2406 port = am65_ndev_to_port(sl_ndev);
2407 port->slave.port_vlan = 0;
2408 if (netif_running(sl_ndev))
2409 am65_cpsw_init_port_emac_ale(port);
2410 }
2411 }
2412 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0);
2413 exit:
2414 rtnl_unlock();
2415
2416 return 0;
2417 }
2418
2419 static const struct devlink_param am65_cpsw_devlink_params[] = {
2420 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode",
2421 DEVLINK_PARAM_TYPE_BOOL,
2422 BIT(DEVLINK_PARAM_CMODE_RUNTIME),
2423 am65_cpsw_dl_switch_mode_get,
2424 am65_cpsw_dl_switch_mode_set, NULL),
2425 };
2426
am65_cpsw_nuss_register_devlink(struct am65_cpsw_common * common)2427 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common)
2428 {
2429 struct devlink_port_attrs attrs = {};
2430 struct am65_cpsw_devlink *dl_priv;
2431 struct device *dev = common->dev;
2432 struct devlink_port *dl_port;
2433 struct am65_cpsw_port *port;
2434 int ret = 0;
2435 int i;
2436
2437 common->devlink =
2438 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev);
2439 if (!common->devlink)
2440 return -ENOMEM;
2441
2442 dl_priv = devlink_priv(common->devlink);
2443 dl_priv->common = common;
2444
2445 ret = devlink_register(common->devlink);
2446 if (ret) {
2447 dev_err(dev, "devlink reg fail ret:%d\n", ret);
2448 goto dl_free;
2449 }
2450
2451 /* Provide devlink hook to switch mode when multiple external ports
2452 * are present NUSS switchdev driver is enabled.
2453 */
2454 if (!AM65_CPSW_IS_CPSW2G(common) &&
2455 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) {
2456 ret = devlink_params_register(common->devlink,
2457 am65_cpsw_devlink_params,
2458 ARRAY_SIZE(am65_cpsw_devlink_params));
2459 if (ret) {
2460 dev_err(dev, "devlink params reg fail ret:%d\n", ret);
2461 goto dl_unreg;
2462 }
2463 devlink_params_publish(common->devlink);
2464 }
2465
2466 for (i = 1; i <= common->port_num; i++) {
2467 port = am65_common_get_port(common, i);
2468 dl_port = &port->devlink_port;
2469
2470 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL;
2471 attrs.phys.port_number = port->port_id;
2472 attrs.switch_id.id_len = sizeof(resource_size_t);
2473 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len);
2474 devlink_port_attrs_set(dl_port, &attrs);
2475
2476 ret = devlink_port_register(common->devlink, dl_port, port->port_id);
2477 if (ret) {
2478 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n",
2479 port->port_id, ret);
2480 goto dl_port_unreg;
2481 }
2482 }
2483
2484 return ret;
2485
2486 dl_port_unreg:
2487 for (i = i - 1; i >= 1; i--) {
2488 port = am65_common_get_port(common, i);
2489 dl_port = &port->devlink_port;
2490
2491 devlink_port_unregister(dl_port);
2492 }
2493 dl_unreg:
2494 devlink_unregister(common->devlink);
2495 dl_free:
2496 devlink_free(common->devlink);
2497
2498 return ret;
2499 }
2500
am65_cpsw_unregister_devlink(struct am65_cpsw_common * common)2501 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common)
2502 {
2503 struct devlink_port *dl_port;
2504 struct am65_cpsw_port *port;
2505 int i;
2506
2507 for (i = 1; i <= common->port_num; i++) {
2508 port = am65_common_get_port(common, i);
2509 dl_port = &port->devlink_port;
2510
2511 devlink_port_unregister(dl_port);
2512 }
2513
2514 if (!AM65_CPSW_IS_CPSW2G(common) &&
2515 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) {
2516 devlink_params_unpublish(common->devlink);
2517 devlink_params_unregister(common->devlink, am65_cpsw_devlink_params,
2518 ARRAY_SIZE(am65_cpsw_devlink_params));
2519 }
2520
2521 devlink_unregister(common->devlink);
2522 devlink_free(common->devlink);
2523 }
2524
am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common * common)2525 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common)
2526 {
2527 struct device *dev = common->dev;
2528 struct devlink_port *dl_port;
2529 struct am65_cpsw_port *port;
2530 int ret = 0, i;
2531
2532 ret = am65_cpsw_nuss_ndev_add_tx_napi(common);
2533 if (ret)
2534 return ret;
2535
2536 ret = devm_request_irq(dev, common->rx_chns.irq,
2537 am65_cpsw_nuss_rx_irq,
2538 IRQF_TRIGGER_HIGH, dev_name(dev), common);
2539 if (ret) {
2540 dev_err(dev, "failure requesting rx irq %u, %d\n",
2541 common->rx_chns.irq, ret);
2542 return ret;
2543 }
2544
2545 ret = am65_cpsw_nuss_register_devlink(common);
2546 if (ret)
2547 return ret;
2548
2549 for (i = 0; i < common->port_num; i++) {
2550 port = &common->ports[i];
2551
2552 if (!port->ndev)
2553 continue;
2554
2555 ret = register_netdev(port->ndev);
2556 if (ret) {
2557 dev_err(dev, "error registering slave net device%i %d\n",
2558 i, ret);
2559 goto err_cleanup_ndev;
2560 }
2561
2562 dl_port = &port->devlink_port;
2563 devlink_port_type_eth_set(dl_port, port->ndev);
2564 }
2565
2566 ret = am65_cpsw_register_notifiers(common);
2567 if (ret)
2568 goto err_cleanup_ndev;
2569
2570 /* can't auto unregister ndev using devm_add_action() due to
2571 * devres release sequence in DD core for DMA
2572 */
2573
2574 return 0;
2575
2576 err_cleanup_ndev:
2577 am65_cpsw_nuss_cleanup_ndev(common);
2578 am65_cpsw_unregister_devlink(common);
2579
2580 return ret;
2581 }
2582
am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common * common,int num_tx)2583 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx)
2584 {
2585 int ret;
2586
2587 common->tx_ch_num = num_tx;
2588 ret = am65_cpsw_nuss_init_tx_chns(common);
2589 if (ret)
2590 return ret;
2591
2592 return am65_cpsw_nuss_ndev_add_tx_napi(common);
2593 }
2594
2595 struct am65_cpsw_soc_pdata {
2596 u32 quirks_dis;
2597 };
2598
2599 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = {
2600 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM,
2601 };
2602
2603 static const struct soc_device_attribute am65_cpsw_socinfo[] = {
2604 { .family = "AM65X",
2605 .revision = "SR2.0",
2606 .data = &am65x_soc_sr2_0
2607 },
2608 {/* sentinel */}
2609 };
2610
2611 static const struct am65_cpsw_pdata am65x_sr1_0 = {
2612 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM,
2613 .ale_dev_id = "am65x-cpsw2g",
2614 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE,
2615 };
2616
2617 static const struct am65_cpsw_pdata j721e_pdata = {
2618 .quirks = 0,
2619 .ale_dev_id = "am65x-cpsw2g",
2620 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE,
2621 };
2622
2623 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = {
2624 .quirks = AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ,
2625 .ale_dev_id = "am64-cpswxg",
2626 .fdqring_mode = K3_RINGACC_RING_MODE_RING,
2627 };
2628
2629 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = {
2630 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0},
2631 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata},
2632 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata},
2633 { /* sentinel */ },
2634 };
2635 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable);
2636
am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common * common)2637 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common)
2638 {
2639 const struct soc_device_attribute *soc;
2640
2641 soc = soc_device_match(am65_cpsw_socinfo);
2642 if (soc && soc->data) {
2643 const struct am65_cpsw_soc_pdata *socdata = soc->data;
2644
2645 /* disable quirks */
2646 common->pdata.quirks &= ~socdata->quirks_dis;
2647 }
2648 }
2649
am65_cpsw_nuss_probe(struct platform_device * pdev)2650 static int am65_cpsw_nuss_probe(struct platform_device *pdev)
2651 {
2652 struct cpsw_ale_params ale_params = { 0 };
2653 const struct of_device_id *of_id;
2654 struct device *dev = &pdev->dev;
2655 struct am65_cpsw_common *common;
2656 struct device_node *node;
2657 struct resource *res;
2658 struct clk *clk;
2659 u64 id_temp;
2660 int ret, i;
2661
2662 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL);
2663 if (!common)
2664 return -ENOMEM;
2665 common->dev = dev;
2666
2667 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev);
2668 if (!of_id)
2669 return -EINVAL;
2670 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data;
2671
2672 am65_cpsw_nuss_apply_socinfo(common);
2673
2674 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss");
2675 common->ss_base = devm_ioremap_resource(&pdev->dev, res);
2676 if (IS_ERR(common->ss_base))
2677 return PTR_ERR(common->ss_base);
2678 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE;
2679 /* Use device's physical base address as switch id */
2680 id_temp = cpu_to_be64(res->start);
2681 memcpy(common->switch_id, &id_temp, sizeof(res->start));
2682
2683 node = of_get_child_by_name(dev->of_node, "ethernet-ports");
2684 if (!node)
2685 return -ENOENT;
2686 common->port_num = of_get_child_count(node);
2687 of_node_put(node);
2688 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS)
2689 return -ENOENT;
2690
2691 common->rx_flow_id_base = -1;
2692 init_completion(&common->tdown_complete);
2693 common->tx_ch_num = 1;
2694 common->pf_p0_rx_ptype_rrobin = false;
2695 common->default_vlan = 1;
2696
2697 common->ports = devm_kcalloc(dev, common->port_num,
2698 sizeof(*common->ports),
2699 GFP_KERNEL);
2700 if (!common->ports)
2701 return -ENOMEM;
2702
2703 clk = devm_clk_get(dev, "fck");
2704 if (IS_ERR(clk))
2705 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n");
2706 common->bus_freq = clk_get_rate(clk);
2707
2708 pm_runtime_enable(dev);
2709 ret = pm_runtime_get_sync(dev);
2710 if (ret < 0) {
2711 pm_runtime_put_noidle(dev);
2712 pm_runtime_disable(dev);
2713 return ret;
2714 }
2715
2716 node = of_get_child_by_name(dev->of_node, "mdio");
2717 if (!node) {
2718 dev_warn(dev, "MDIO node not found\n");
2719 } else if (of_device_is_available(node)) {
2720 struct platform_device *mdio_pdev;
2721
2722 mdio_pdev = of_platform_device_create(node, NULL, dev);
2723 if (!mdio_pdev) {
2724 ret = -ENODEV;
2725 goto err_pm_clear;
2726 }
2727
2728 common->mdio_dev = &mdio_pdev->dev;
2729 }
2730 of_node_put(node);
2731
2732 am65_cpsw_nuss_get_ver(common);
2733
2734 /* init tx channels */
2735 ret = am65_cpsw_nuss_init_tx_chns(common);
2736 if (ret)
2737 goto err_of_clear;
2738 ret = am65_cpsw_nuss_init_rx_chns(common);
2739 if (ret)
2740 goto err_of_clear;
2741
2742 ret = am65_cpsw_nuss_init_host_p(common);
2743 if (ret)
2744 goto err_of_clear;
2745
2746 ret = am65_cpsw_nuss_init_slave_ports(common);
2747 if (ret)
2748 goto err_of_clear;
2749
2750 /* init common data */
2751 ale_params.dev = dev;
2752 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT;
2753 ale_params.ale_ports = common->port_num + 1;
2754 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE;
2755 ale_params.dev_id = common->pdata.ale_dev_id;
2756 ale_params.bus_freq = common->bus_freq;
2757
2758 common->ale = cpsw_ale_create(&ale_params);
2759 if (IS_ERR(common->ale)) {
2760 dev_err(dev, "error initializing ale engine\n");
2761 ret = PTR_ERR(common->ale);
2762 goto err_of_clear;
2763 }
2764
2765 ret = am65_cpsw_init_cpts(common);
2766 if (ret)
2767 goto err_of_clear;
2768
2769 /* init ports */
2770 for (i = 0; i < common->port_num; i++)
2771 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]);
2772
2773 dev_set_drvdata(dev, common);
2774
2775 common->is_emac_mode = true;
2776
2777 ret = am65_cpsw_nuss_init_ndevs(common);
2778 if (ret)
2779 goto err_of_clear;
2780
2781 ret = am65_cpsw_nuss_register_ndevs(common);
2782 if (ret)
2783 goto err_of_clear;
2784
2785 pm_runtime_put(dev);
2786 return 0;
2787
2788 err_of_clear:
2789 if (common->mdio_dev)
2790 of_platform_device_destroy(common->mdio_dev, NULL);
2791 err_pm_clear:
2792 pm_runtime_put_sync(dev);
2793 pm_runtime_disable(dev);
2794 return ret;
2795 }
2796
am65_cpsw_nuss_remove(struct platform_device * pdev)2797 static int am65_cpsw_nuss_remove(struct platform_device *pdev)
2798 {
2799 struct device *dev = &pdev->dev;
2800 struct am65_cpsw_common *common;
2801 int ret;
2802
2803 common = dev_get_drvdata(dev);
2804
2805 ret = pm_runtime_get_sync(&pdev->dev);
2806 if (ret < 0) {
2807 pm_runtime_put_noidle(&pdev->dev);
2808 return ret;
2809 }
2810
2811 am65_cpsw_unregister_devlink(common);
2812 am65_cpsw_unregister_notifiers(common);
2813
2814 /* must unregister ndevs here because DD release_driver routine calls
2815 * dma_deconfigure(dev) before devres_release_all(dev)
2816 */
2817 am65_cpsw_nuss_cleanup_ndev(common);
2818
2819 if (common->mdio_dev)
2820 of_platform_device_destroy(common->mdio_dev, NULL);
2821
2822 pm_runtime_put_sync(&pdev->dev);
2823 pm_runtime_disable(&pdev->dev);
2824 return 0;
2825 }
2826
2827 static struct platform_driver am65_cpsw_nuss_driver = {
2828 .driver = {
2829 .name = AM65_CPSW_DRV_NAME,
2830 .of_match_table = am65_cpsw_nuss_of_mtable,
2831 },
2832 .probe = am65_cpsw_nuss_probe,
2833 .remove = am65_cpsw_nuss_remove,
2834 };
2835
2836 module_platform_driver(am65_cpsw_nuss_driver);
2837
2838 MODULE_LICENSE("GPL v2");
2839 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>");
2840 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver");
2841