1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
10
11 #include <linux/ratelimit.h>
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/amba/bus.h>
15 #include <linux/platform_device.h>
16 #include <linux/pci-ats.h>
17 #include <linux/bitmap.h>
18 #include <linux/slab.h>
19 #include <linux/debugfs.h>
20 #include <linux/scatterlist.h>
21 #include <linux/dma-map-ops.h>
22 #include <linux/dma-direct.h>
23 #include <linux/dma-iommu.h>
24 #include <linux/iommu-helper.h>
25 #include <linux/delay.h>
26 #include <linux/amd-iommu.h>
27 #include <linux/notifier.h>
28 #include <linux/export.h>
29 #include <linux/irq.h>
30 #include <linux/msi.h>
31 #include <linux/irqdomain.h>
32 #include <linux/percpu.h>
33 #include <linux/io-pgtable.h>
34 #include <asm/irq_remapping.h>
35 #include <asm/io_apic.h>
36 #include <asm/apic.h>
37 #include <asm/hw_irq.h>
38 #include <asm/proto.h>
39 #include <asm/iommu.h>
40 #include <asm/gart.h>
41 #include <asm/dma.h>
42
43 #include "amd_iommu.h"
44 #include "../irq_remapping.h"
45
46 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
47
48 #define LOOP_TIMEOUT 100000
49
50 /* IO virtual address start page frame number */
51 #define IOVA_START_PFN (1)
52 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
53
54 /* Reserved IOVA ranges */
55 #define MSI_RANGE_START (0xfee00000)
56 #define MSI_RANGE_END (0xfeefffff)
57 #define HT_RANGE_START (0xfd00000000ULL)
58 #define HT_RANGE_END (0xffffffffffULL)
59
60 #define DEFAULT_PGTABLE_LEVEL PAGE_MODE_3_LEVEL
61
62 static DEFINE_SPINLOCK(pd_bitmap_lock);
63
64 /* List of all available dev_data structures */
65 static LLIST_HEAD(dev_data_list);
66
67 LIST_HEAD(ioapic_map);
68 LIST_HEAD(hpet_map);
69 LIST_HEAD(acpihid_map);
70
71 /*
72 * Domain for untranslated devices - only allocated
73 * if iommu=pt passed on kernel cmd line.
74 */
75 const struct iommu_ops amd_iommu_ops;
76
77 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
78 int amd_iommu_max_glx_val = -1;
79
80 /*
81 * general struct to manage commands send to an IOMMU
82 */
83 struct iommu_cmd {
84 u32 data[4];
85 };
86
87 struct kmem_cache *amd_iommu_irq_cache;
88
89 static void detach_device(struct device *dev);
90
91 /****************************************************************************
92 *
93 * Helper functions
94 *
95 ****************************************************************************/
96
get_pci_device_id(struct device * dev)97 static inline u16 get_pci_device_id(struct device *dev)
98 {
99 struct pci_dev *pdev = to_pci_dev(dev);
100
101 return pci_dev_id(pdev);
102 }
103
get_acpihid_device_id(struct device * dev,struct acpihid_map_entry ** entry)104 static inline int get_acpihid_device_id(struct device *dev,
105 struct acpihid_map_entry **entry)
106 {
107 struct acpi_device *adev = ACPI_COMPANION(dev);
108 struct acpihid_map_entry *p;
109
110 if (!adev)
111 return -ENODEV;
112
113 list_for_each_entry(p, &acpihid_map, list) {
114 if (acpi_dev_hid_uid_match(adev, p->hid,
115 p->uid[0] ? p->uid : NULL)) {
116 if (entry)
117 *entry = p;
118 return p->devid;
119 }
120 }
121 return -EINVAL;
122 }
123
get_device_id(struct device * dev)124 static inline int get_device_id(struct device *dev)
125 {
126 int devid;
127
128 if (dev_is_pci(dev))
129 devid = get_pci_device_id(dev);
130 else
131 devid = get_acpihid_device_id(dev, NULL);
132
133 return devid;
134 }
135
to_pdomain(struct iommu_domain * dom)136 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
137 {
138 return container_of(dom, struct protection_domain, domain);
139 }
140
alloc_dev_data(u16 devid)141 static struct iommu_dev_data *alloc_dev_data(u16 devid)
142 {
143 struct iommu_dev_data *dev_data;
144
145 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
146 if (!dev_data)
147 return NULL;
148
149 spin_lock_init(&dev_data->lock);
150 dev_data->devid = devid;
151 ratelimit_default_init(&dev_data->rs);
152
153 llist_add(&dev_data->dev_data_list, &dev_data_list);
154 return dev_data;
155 }
156
search_dev_data(u16 devid)157 static struct iommu_dev_data *search_dev_data(u16 devid)
158 {
159 struct iommu_dev_data *dev_data;
160 struct llist_node *node;
161
162 if (llist_empty(&dev_data_list))
163 return NULL;
164
165 node = dev_data_list.first;
166 llist_for_each_entry(dev_data, node, dev_data_list) {
167 if (dev_data->devid == devid)
168 return dev_data;
169 }
170
171 return NULL;
172 }
173
clone_alias(struct pci_dev * pdev,u16 alias,void * data)174 static int clone_alias(struct pci_dev *pdev, u16 alias, void *data)
175 {
176 u16 devid = pci_dev_id(pdev);
177
178 if (devid == alias)
179 return 0;
180
181 amd_iommu_rlookup_table[alias] =
182 amd_iommu_rlookup_table[devid];
183 memcpy(amd_iommu_dev_table[alias].data,
184 amd_iommu_dev_table[devid].data,
185 sizeof(amd_iommu_dev_table[alias].data));
186
187 return 0;
188 }
189
clone_aliases(struct pci_dev * pdev)190 static void clone_aliases(struct pci_dev *pdev)
191 {
192 if (!pdev)
193 return;
194
195 /*
196 * The IVRS alias stored in the alias table may not be
197 * part of the PCI DMA aliases if it's bus differs
198 * from the original device.
199 */
200 clone_alias(pdev, amd_iommu_alias_table[pci_dev_id(pdev)], NULL);
201
202 pci_for_each_dma_alias(pdev, clone_alias, NULL);
203 }
204
setup_aliases(struct device * dev)205 static struct pci_dev *setup_aliases(struct device *dev)
206 {
207 struct pci_dev *pdev = to_pci_dev(dev);
208 u16 ivrs_alias;
209
210 /* For ACPI HID devices, there are no aliases */
211 if (!dev_is_pci(dev))
212 return NULL;
213
214 /*
215 * Add the IVRS alias to the pci aliases if it is on the same
216 * bus. The IVRS table may know about a quirk that we don't.
217 */
218 ivrs_alias = amd_iommu_alias_table[pci_dev_id(pdev)];
219 if (ivrs_alias != pci_dev_id(pdev) &&
220 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number)
221 pci_add_dma_alias(pdev, ivrs_alias & 0xff, 1);
222
223 clone_aliases(pdev);
224
225 return pdev;
226 }
227
find_dev_data(u16 devid)228 static struct iommu_dev_data *find_dev_data(u16 devid)
229 {
230 struct iommu_dev_data *dev_data;
231 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
232
233 dev_data = search_dev_data(devid);
234
235 if (dev_data == NULL) {
236 dev_data = alloc_dev_data(devid);
237 if (!dev_data)
238 return NULL;
239
240 if (translation_pre_enabled(iommu))
241 dev_data->defer_attach = true;
242 }
243
244 return dev_data;
245 }
246
247 /*
248 * Find or create an IOMMU group for a acpihid device.
249 */
acpihid_device_group(struct device * dev)250 static struct iommu_group *acpihid_device_group(struct device *dev)
251 {
252 struct acpihid_map_entry *p, *entry = NULL;
253 int devid;
254
255 devid = get_acpihid_device_id(dev, &entry);
256 if (devid < 0)
257 return ERR_PTR(devid);
258
259 list_for_each_entry(p, &acpihid_map, list) {
260 if ((devid == p->devid) && p->group)
261 entry->group = p->group;
262 }
263
264 if (!entry->group)
265 entry->group = generic_device_group(dev);
266 else
267 iommu_group_ref_get(entry->group);
268
269 return entry->group;
270 }
271
pci_iommuv2_capable(struct pci_dev * pdev)272 static bool pci_iommuv2_capable(struct pci_dev *pdev)
273 {
274 static const int caps[] = {
275 PCI_EXT_CAP_ID_PRI,
276 PCI_EXT_CAP_ID_PASID,
277 };
278 int i, pos;
279
280 if (!pci_ats_supported(pdev))
281 return false;
282
283 for (i = 0; i < 2; ++i) {
284 pos = pci_find_ext_capability(pdev, caps[i]);
285 if (pos == 0)
286 return false;
287 }
288
289 return true;
290 }
291
292 /*
293 * This function checks if the driver got a valid device from the caller to
294 * avoid dereferencing invalid pointers.
295 */
check_device(struct device * dev)296 static bool check_device(struct device *dev)
297 {
298 int devid;
299
300 if (!dev)
301 return false;
302
303 devid = get_device_id(dev);
304 if (devid < 0)
305 return false;
306
307 /* Out of our scope? */
308 if (devid > amd_iommu_last_bdf)
309 return false;
310
311 if (amd_iommu_rlookup_table[devid] == NULL)
312 return false;
313
314 return true;
315 }
316
iommu_init_device(struct device * dev)317 static int iommu_init_device(struct device *dev)
318 {
319 struct iommu_dev_data *dev_data;
320 int devid;
321
322 if (dev_iommu_priv_get(dev))
323 return 0;
324
325 devid = get_device_id(dev);
326 if (devid < 0)
327 return devid;
328
329 dev_data = find_dev_data(devid);
330 if (!dev_data)
331 return -ENOMEM;
332
333 dev_data->pdev = setup_aliases(dev);
334
335 /*
336 * By default we use passthrough mode for IOMMUv2 capable device.
337 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
338 * invalid address), we ignore the capability for the device so
339 * it'll be forced to go into translation mode.
340 */
341 if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
342 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
343 struct amd_iommu *iommu;
344
345 iommu = amd_iommu_rlookup_table[dev_data->devid];
346 dev_data->iommu_v2 = iommu->is_iommu_v2;
347 }
348
349 dev_iommu_priv_set(dev, dev_data);
350
351 return 0;
352 }
353
iommu_ignore_device(struct device * dev)354 static void iommu_ignore_device(struct device *dev)
355 {
356 int devid;
357
358 devid = get_device_id(dev);
359 if (devid < 0)
360 return;
361
362 amd_iommu_rlookup_table[devid] = NULL;
363 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
364
365 setup_aliases(dev);
366 }
367
amd_iommu_uninit_device(struct device * dev)368 static void amd_iommu_uninit_device(struct device *dev)
369 {
370 struct iommu_dev_data *dev_data;
371
372 dev_data = dev_iommu_priv_get(dev);
373 if (!dev_data)
374 return;
375
376 if (dev_data->domain)
377 detach_device(dev);
378
379 dev_iommu_priv_set(dev, NULL);
380
381 /*
382 * We keep dev_data around for unplugged devices and reuse it when the
383 * device is re-plugged - not doing so would introduce a ton of races.
384 */
385 }
386
387 /****************************************************************************
388 *
389 * Interrupt handling functions
390 *
391 ****************************************************************************/
392
dump_dte_entry(u16 devid)393 static void dump_dte_entry(u16 devid)
394 {
395 int i;
396
397 for (i = 0; i < 4; ++i)
398 pr_err("DTE[%d]: %016llx\n", i,
399 amd_iommu_dev_table[devid].data[i]);
400 }
401
dump_command(unsigned long phys_addr)402 static void dump_command(unsigned long phys_addr)
403 {
404 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
405 int i;
406
407 for (i = 0; i < 4; ++i)
408 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
409 }
410
amd_iommu_report_rmp_hw_error(volatile u32 * event)411 static void amd_iommu_report_rmp_hw_error(volatile u32 *event)
412 {
413 struct iommu_dev_data *dev_data = NULL;
414 int devid, vmg_tag, flags;
415 struct pci_dev *pdev;
416 u64 spa;
417
418 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
419 vmg_tag = (event[1]) & 0xFFFF;
420 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
421 spa = ((u64)event[3] << 32) | (event[2] & 0xFFFFFFF8);
422
423 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
424 devid & 0xff);
425 if (pdev)
426 dev_data = dev_iommu_priv_get(&pdev->dev);
427
428 if (dev_data) {
429 if (__ratelimit(&dev_data->rs)) {
430 pci_err(pdev, "Event logged [RMP_HW_ERROR vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n",
431 vmg_tag, spa, flags);
432 }
433 } else {
434 pr_err_ratelimited("Event logged [RMP_HW_ERROR device=%02x:%02x.%x, vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n",
435 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
436 vmg_tag, spa, flags);
437 }
438
439 if (pdev)
440 pci_dev_put(pdev);
441 }
442
amd_iommu_report_rmp_fault(volatile u32 * event)443 static void amd_iommu_report_rmp_fault(volatile u32 *event)
444 {
445 struct iommu_dev_data *dev_data = NULL;
446 int devid, flags_rmp, vmg_tag, flags;
447 struct pci_dev *pdev;
448 u64 gpa;
449
450 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
451 flags_rmp = (event[0] >> EVENT_FLAGS_SHIFT) & 0xFF;
452 vmg_tag = (event[1]) & 0xFFFF;
453 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
454 gpa = ((u64)event[3] << 32) | event[2];
455
456 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
457 devid & 0xff);
458 if (pdev)
459 dev_data = dev_iommu_priv_get(&pdev->dev);
460
461 if (dev_data) {
462 if (__ratelimit(&dev_data->rs)) {
463 pci_err(pdev, "Event logged [RMP_PAGE_FAULT vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n",
464 vmg_tag, gpa, flags_rmp, flags);
465 }
466 } else {
467 pr_err_ratelimited("Event logged [RMP_PAGE_FAULT device=%02x:%02x.%x, vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n",
468 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
469 vmg_tag, gpa, flags_rmp, flags);
470 }
471
472 if (pdev)
473 pci_dev_put(pdev);
474 }
475
amd_iommu_report_page_fault(u16 devid,u16 domain_id,u64 address,int flags)476 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
477 u64 address, int flags)
478 {
479 struct iommu_dev_data *dev_data = NULL;
480 struct pci_dev *pdev;
481
482 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
483 devid & 0xff);
484 if (pdev)
485 dev_data = dev_iommu_priv_get(&pdev->dev);
486
487 if (dev_data) {
488 if (__ratelimit(&dev_data->rs)) {
489 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
490 domain_id, address, flags);
491 }
492 } else {
493 pr_err_ratelimited("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
494 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
495 domain_id, address, flags);
496 }
497
498 if (pdev)
499 pci_dev_put(pdev);
500 }
501
iommu_print_event(struct amd_iommu * iommu,void * __evt)502 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
503 {
504 struct device *dev = iommu->iommu.dev;
505 int type, devid, flags, tag;
506 volatile u32 *event = __evt;
507 int count = 0;
508 u64 address;
509 u32 pasid;
510
511 retry:
512 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
513 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
514 pasid = (event[0] & EVENT_DOMID_MASK_HI) |
515 (event[1] & EVENT_DOMID_MASK_LO);
516 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
517 address = (u64)(((u64)event[3]) << 32) | event[2];
518
519 if (type == 0) {
520 /* Did we hit the erratum? */
521 if (++count == LOOP_TIMEOUT) {
522 pr_err("No event written to event log\n");
523 return;
524 }
525 udelay(1);
526 goto retry;
527 }
528
529 if (type == EVENT_TYPE_IO_FAULT) {
530 amd_iommu_report_page_fault(devid, pasid, address, flags);
531 return;
532 }
533
534 switch (type) {
535 case EVENT_TYPE_ILL_DEV:
536 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
537 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
538 pasid, address, flags);
539 dump_dte_entry(devid);
540 break;
541 case EVENT_TYPE_DEV_TAB_ERR:
542 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
543 "address=0x%llx flags=0x%04x]\n",
544 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
545 address, flags);
546 break;
547 case EVENT_TYPE_PAGE_TAB_ERR:
548 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
549 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
550 pasid, address, flags);
551 break;
552 case EVENT_TYPE_ILL_CMD:
553 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
554 dump_command(address);
555 break;
556 case EVENT_TYPE_CMD_HARD_ERR:
557 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
558 address, flags);
559 break;
560 case EVENT_TYPE_IOTLB_INV_TO:
561 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
562 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
563 address);
564 break;
565 case EVENT_TYPE_INV_DEV_REQ:
566 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
567 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
568 pasid, address, flags);
569 break;
570 case EVENT_TYPE_RMP_FAULT:
571 amd_iommu_report_rmp_fault(event);
572 break;
573 case EVENT_TYPE_RMP_HW_ERR:
574 amd_iommu_report_rmp_hw_error(event);
575 break;
576 case EVENT_TYPE_INV_PPR_REQ:
577 pasid = PPR_PASID(*((u64 *)__evt));
578 tag = event[1] & 0x03FF;
579 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
580 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
581 pasid, address, flags, tag);
582 break;
583 default:
584 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
585 event[0], event[1], event[2], event[3]);
586 }
587
588 memset(__evt, 0, 4 * sizeof(u32));
589 }
590
iommu_poll_events(struct amd_iommu * iommu)591 static void iommu_poll_events(struct amd_iommu *iommu)
592 {
593 u32 head, tail;
594
595 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
596 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
597
598 while (head != tail) {
599 iommu_print_event(iommu, iommu->evt_buf + head);
600 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
601 }
602
603 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
604 }
605
iommu_handle_ppr_entry(struct amd_iommu * iommu,u64 * raw)606 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
607 {
608 struct amd_iommu_fault fault;
609
610 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
611 pr_err_ratelimited("Unknown PPR request received\n");
612 return;
613 }
614
615 fault.address = raw[1];
616 fault.pasid = PPR_PASID(raw[0]);
617 fault.device_id = PPR_DEVID(raw[0]);
618 fault.tag = PPR_TAG(raw[0]);
619 fault.flags = PPR_FLAGS(raw[0]);
620
621 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
622 }
623
iommu_poll_ppr_log(struct amd_iommu * iommu)624 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
625 {
626 u32 head, tail;
627
628 if (iommu->ppr_log == NULL)
629 return;
630
631 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
632 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
633
634 while (head != tail) {
635 volatile u64 *raw;
636 u64 entry[2];
637 int i;
638
639 raw = (u64 *)(iommu->ppr_log + head);
640
641 /*
642 * Hardware bug: Interrupt may arrive before the entry is
643 * written to memory. If this happens we need to wait for the
644 * entry to arrive.
645 */
646 for (i = 0; i < LOOP_TIMEOUT; ++i) {
647 if (PPR_REQ_TYPE(raw[0]) != 0)
648 break;
649 udelay(1);
650 }
651
652 /* Avoid memcpy function-call overhead */
653 entry[0] = raw[0];
654 entry[1] = raw[1];
655
656 /*
657 * To detect the hardware bug we need to clear the entry
658 * back to zero.
659 */
660 raw[0] = raw[1] = 0UL;
661
662 /* Update head pointer of hardware ring-buffer */
663 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
664 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
665
666 /* Handle PPR entry */
667 iommu_handle_ppr_entry(iommu, entry);
668
669 /* Refresh ring-buffer information */
670 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
671 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
672 }
673 }
674
675 #ifdef CONFIG_IRQ_REMAP
676 static int (*iommu_ga_log_notifier)(u32);
677
amd_iommu_register_ga_log_notifier(int (* notifier)(u32))678 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
679 {
680 iommu_ga_log_notifier = notifier;
681
682 return 0;
683 }
684 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
685
iommu_poll_ga_log(struct amd_iommu * iommu)686 static void iommu_poll_ga_log(struct amd_iommu *iommu)
687 {
688 u32 head, tail, cnt = 0;
689
690 if (iommu->ga_log == NULL)
691 return;
692
693 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
694 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
695
696 while (head != tail) {
697 volatile u64 *raw;
698 u64 log_entry;
699
700 raw = (u64 *)(iommu->ga_log + head);
701 cnt++;
702
703 /* Avoid memcpy function-call overhead */
704 log_entry = *raw;
705
706 /* Update head pointer of hardware ring-buffer */
707 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
708 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
709
710 /* Handle GA entry */
711 switch (GA_REQ_TYPE(log_entry)) {
712 case GA_GUEST_NR:
713 if (!iommu_ga_log_notifier)
714 break;
715
716 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
717 __func__, GA_DEVID(log_entry),
718 GA_TAG(log_entry));
719
720 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
721 pr_err("GA log notifier failed.\n");
722 break;
723 default:
724 break;
725 }
726 }
727 }
728
729 static void
amd_iommu_set_pci_msi_domain(struct device * dev,struct amd_iommu * iommu)730 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu)
731 {
732 if (!irq_remapping_enabled || !dev_is_pci(dev) ||
733 pci_dev_has_special_msi_domain(to_pci_dev(dev)))
734 return;
735
736 dev_set_msi_domain(dev, iommu->msi_domain);
737 }
738
739 #else /* CONFIG_IRQ_REMAP */
740 static inline void
amd_iommu_set_pci_msi_domain(struct device * dev,struct amd_iommu * iommu)741 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu) { }
742 #endif /* !CONFIG_IRQ_REMAP */
743
744 #define AMD_IOMMU_INT_MASK \
745 (MMIO_STATUS_EVT_OVERFLOW_INT_MASK | \
746 MMIO_STATUS_EVT_INT_MASK | \
747 MMIO_STATUS_PPR_INT_MASK | \
748 MMIO_STATUS_GALOG_INT_MASK)
749
amd_iommu_int_thread(int irq,void * data)750 irqreturn_t amd_iommu_int_thread(int irq, void *data)
751 {
752 struct amd_iommu *iommu = (struct amd_iommu *) data;
753 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
754
755 while (status & AMD_IOMMU_INT_MASK) {
756 /* Enable interrupt sources again */
757 writel(AMD_IOMMU_INT_MASK,
758 iommu->mmio_base + MMIO_STATUS_OFFSET);
759
760 if (status & MMIO_STATUS_EVT_INT_MASK) {
761 pr_devel("Processing IOMMU Event Log\n");
762 iommu_poll_events(iommu);
763 }
764
765 if (status & MMIO_STATUS_PPR_INT_MASK) {
766 pr_devel("Processing IOMMU PPR Log\n");
767 iommu_poll_ppr_log(iommu);
768 }
769
770 #ifdef CONFIG_IRQ_REMAP
771 if (status & MMIO_STATUS_GALOG_INT_MASK) {
772 pr_devel("Processing IOMMU GA Log\n");
773 iommu_poll_ga_log(iommu);
774 }
775 #endif
776
777 if (status & MMIO_STATUS_EVT_OVERFLOW_INT_MASK) {
778 pr_info_ratelimited("IOMMU event log overflow\n");
779 amd_iommu_restart_event_logging(iommu);
780 }
781
782 /*
783 * Hardware bug: ERBT1312
784 * When re-enabling interrupt (by writing 1
785 * to clear the bit), the hardware might also try to set
786 * the interrupt bit in the event status register.
787 * In this scenario, the bit will be set, and disable
788 * subsequent interrupts.
789 *
790 * Workaround: The IOMMU driver should read back the
791 * status register and check if the interrupt bits are cleared.
792 * If not, driver will need to go through the interrupt handler
793 * again and re-clear the bits
794 */
795 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
796 }
797 return IRQ_HANDLED;
798 }
799
amd_iommu_int_handler(int irq,void * data)800 irqreturn_t amd_iommu_int_handler(int irq, void *data)
801 {
802 return IRQ_WAKE_THREAD;
803 }
804
805 /****************************************************************************
806 *
807 * IOMMU command queuing functions
808 *
809 ****************************************************************************/
810
wait_on_sem(struct amd_iommu * iommu,u64 data)811 static int wait_on_sem(struct amd_iommu *iommu, u64 data)
812 {
813 int i = 0;
814
815 while (*iommu->cmd_sem != data && i < LOOP_TIMEOUT) {
816 udelay(1);
817 i += 1;
818 }
819
820 if (i == LOOP_TIMEOUT) {
821 pr_alert("Completion-Wait loop timed out\n");
822 return -EIO;
823 }
824
825 return 0;
826 }
827
copy_cmd_to_buffer(struct amd_iommu * iommu,struct iommu_cmd * cmd)828 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
829 struct iommu_cmd *cmd)
830 {
831 u8 *target;
832 u32 tail;
833
834 /* Copy command to buffer */
835 tail = iommu->cmd_buf_tail;
836 target = iommu->cmd_buf + tail;
837 memcpy(target, cmd, sizeof(*cmd));
838
839 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
840 iommu->cmd_buf_tail = tail;
841
842 /* Tell the IOMMU about it */
843 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
844 }
845
build_completion_wait(struct iommu_cmd * cmd,struct amd_iommu * iommu,u64 data)846 static void build_completion_wait(struct iommu_cmd *cmd,
847 struct amd_iommu *iommu,
848 u64 data)
849 {
850 u64 paddr = iommu_virt_to_phys((void *)iommu->cmd_sem);
851
852 memset(cmd, 0, sizeof(*cmd));
853 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
854 cmd->data[1] = upper_32_bits(paddr);
855 cmd->data[2] = lower_32_bits(data);
856 cmd->data[3] = upper_32_bits(data);
857 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
858 }
859
build_inv_dte(struct iommu_cmd * cmd,u16 devid)860 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
861 {
862 memset(cmd, 0, sizeof(*cmd));
863 cmd->data[0] = devid;
864 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
865 }
866
867 /*
868 * Builds an invalidation address which is suitable for one page or multiple
869 * pages. Sets the size bit (S) as needed is more than one page is flushed.
870 */
build_inv_address(u64 address,size_t size)871 static inline u64 build_inv_address(u64 address, size_t size)
872 {
873 u64 pages, end, msb_diff;
874
875 pages = iommu_num_pages(address, size, PAGE_SIZE);
876
877 if (pages == 1)
878 return address & PAGE_MASK;
879
880 end = address + size - 1;
881
882 /*
883 * msb_diff would hold the index of the most significant bit that
884 * flipped between the start and end.
885 */
886 msb_diff = fls64(end ^ address) - 1;
887
888 /*
889 * Bits 63:52 are sign extended. If for some reason bit 51 is different
890 * between the start and the end, invalidate everything.
891 */
892 if (unlikely(msb_diff > 51)) {
893 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
894 } else {
895 /*
896 * The msb-bit must be clear on the address. Just set all the
897 * lower bits.
898 */
899 address |= (1ull << msb_diff) - 1;
900 }
901
902 /* Clear bits 11:0 */
903 address &= PAGE_MASK;
904
905 /* Set the size bit - we flush more than one 4kb page */
906 return address | CMD_INV_IOMMU_PAGES_SIZE_MASK;
907 }
908
build_inv_iommu_pages(struct iommu_cmd * cmd,u64 address,size_t size,u16 domid,int pde)909 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
910 size_t size, u16 domid, int pde)
911 {
912 u64 inv_address = build_inv_address(address, size);
913
914 memset(cmd, 0, sizeof(*cmd));
915 cmd->data[1] |= domid;
916 cmd->data[2] = lower_32_bits(inv_address);
917 cmd->data[3] = upper_32_bits(inv_address);
918 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
919 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
920 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
921 }
922
build_inv_iotlb_pages(struct iommu_cmd * cmd,u16 devid,int qdep,u64 address,size_t size)923 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
924 u64 address, size_t size)
925 {
926 u64 inv_address = build_inv_address(address, size);
927
928 memset(cmd, 0, sizeof(*cmd));
929 cmd->data[0] = devid;
930 cmd->data[0] |= (qdep & 0xff) << 24;
931 cmd->data[1] = devid;
932 cmd->data[2] = lower_32_bits(inv_address);
933 cmd->data[3] = upper_32_bits(inv_address);
934 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
935 }
936
build_inv_iommu_pasid(struct iommu_cmd * cmd,u16 domid,u32 pasid,u64 address,bool size)937 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, u32 pasid,
938 u64 address, bool size)
939 {
940 memset(cmd, 0, sizeof(*cmd));
941
942 address &= ~(0xfffULL);
943
944 cmd->data[0] = pasid;
945 cmd->data[1] = domid;
946 cmd->data[2] = lower_32_bits(address);
947 cmd->data[3] = upper_32_bits(address);
948 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
949 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
950 if (size)
951 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
952 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
953 }
954
build_inv_iotlb_pasid(struct iommu_cmd * cmd,u16 devid,u32 pasid,int qdep,u64 address,bool size)955 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, u32 pasid,
956 int qdep, u64 address, bool size)
957 {
958 memset(cmd, 0, sizeof(*cmd));
959
960 address &= ~(0xfffULL);
961
962 cmd->data[0] = devid;
963 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
964 cmd->data[0] |= (qdep & 0xff) << 24;
965 cmd->data[1] = devid;
966 cmd->data[1] |= (pasid & 0xff) << 16;
967 cmd->data[2] = lower_32_bits(address);
968 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
969 cmd->data[3] = upper_32_bits(address);
970 if (size)
971 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
972 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
973 }
974
build_complete_ppr(struct iommu_cmd * cmd,u16 devid,u32 pasid,int status,int tag,bool gn)975 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid,
976 int status, int tag, bool gn)
977 {
978 memset(cmd, 0, sizeof(*cmd));
979
980 cmd->data[0] = devid;
981 if (gn) {
982 cmd->data[1] = pasid;
983 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
984 }
985 cmd->data[3] = tag & 0x1ff;
986 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
987
988 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
989 }
990
build_inv_all(struct iommu_cmd * cmd)991 static void build_inv_all(struct iommu_cmd *cmd)
992 {
993 memset(cmd, 0, sizeof(*cmd));
994 CMD_SET_TYPE(cmd, CMD_INV_ALL);
995 }
996
build_inv_irt(struct iommu_cmd * cmd,u16 devid)997 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
998 {
999 memset(cmd, 0, sizeof(*cmd));
1000 cmd->data[0] = devid;
1001 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1002 }
1003
1004 /*
1005 * Writes the command to the IOMMUs command buffer and informs the
1006 * hardware about the new command.
1007 */
__iommu_queue_command_sync(struct amd_iommu * iommu,struct iommu_cmd * cmd,bool sync)1008 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1009 struct iommu_cmd *cmd,
1010 bool sync)
1011 {
1012 unsigned int count = 0;
1013 u32 left, next_tail;
1014
1015 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1016 again:
1017 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1018
1019 if (left <= 0x20) {
1020 /* Skip udelay() the first time around */
1021 if (count++) {
1022 if (count == LOOP_TIMEOUT) {
1023 pr_err("Command buffer timeout\n");
1024 return -EIO;
1025 }
1026
1027 udelay(1);
1028 }
1029
1030 /* Update head and recheck remaining space */
1031 iommu->cmd_buf_head = readl(iommu->mmio_base +
1032 MMIO_CMD_HEAD_OFFSET);
1033
1034 goto again;
1035 }
1036
1037 copy_cmd_to_buffer(iommu, cmd);
1038
1039 /* Do we need to make sure all commands are processed? */
1040 iommu->need_sync = sync;
1041
1042 return 0;
1043 }
1044
iommu_queue_command_sync(struct amd_iommu * iommu,struct iommu_cmd * cmd,bool sync)1045 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1046 struct iommu_cmd *cmd,
1047 bool sync)
1048 {
1049 unsigned long flags;
1050 int ret;
1051
1052 raw_spin_lock_irqsave(&iommu->lock, flags);
1053 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1054 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1055
1056 return ret;
1057 }
1058
iommu_queue_command(struct amd_iommu * iommu,struct iommu_cmd * cmd)1059 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1060 {
1061 return iommu_queue_command_sync(iommu, cmd, true);
1062 }
1063
1064 /*
1065 * This function queues a completion wait command into the command
1066 * buffer of an IOMMU
1067 */
iommu_completion_wait(struct amd_iommu * iommu)1068 static int iommu_completion_wait(struct amd_iommu *iommu)
1069 {
1070 struct iommu_cmd cmd;
1071 unsigned long flags;
1072 int ret;
1073 u64 data;
1074
1075 if (!iommu->need_sync)
1076 return 0;
1077
1078 raw_spin_lock_irqsave(&iommu->lock, flags);
1079
1080 data = ++iommu->cmd_sem_val;
1081 build_completion_wait(&cmd, iommu, data);
1082
1083 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1084 if (ret)
1085 goto out_unlock;
1086
1087 ret = wait_on_sem(iommu, data);
1088
1089 out_unlock:
1090 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1091
1092 return ret;
1093 }
1094
iommu_flush_dte(struct amd_iommu * iommu,u16 devid)1095 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1096 {
1097 struct iommu_cmd cmd;
1098
1099 build_inv_dte(&cmd, devid);
1100
1101 return iommu_queue_command(iommu, &cmd);
1102 }
1103
amd_iommu_flush_dte_all(struct amd_iommu * iommu)1104 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1105 {
1106 u32 devid;
1107
1108 for (devid = 0; devid <= 0xffff; ++devid)
1109 iommu_flush_dte(iommu, devid);
1110
1111 iommu_completion_wait(iommu);
1112 }
1113
1114 /*
1115 * This function uses heavy locking and may disable irqs for some time. But
1116 * this is no issue because it is only called during resume.
1117 */
amd_iommu_flush_tlb_all(struct amd_iommu * iommu)1118 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1119 {
1120 u32 dom_id;
1121
1122 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1123 struct iommu_cmd cmd;
1124 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1125 dom_id, 1);
1126 iommu_queue_command(iommu, &cmd);
1127 }
1128
1129 iommu_completion_wait(iommu);
1130 }
1131
amd_iommu_flush_tlb_domid(struct amd_iommu * iommu,u32 dom_id)1132 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1133 {
1134 struct iommu_cmd cmd;
1135
1136 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1137 dom_id, 1);
1138 iommu_queue_command(iommu, &cmd);
1139
1140 iommu_completion_wait(iommu);
1141 }
1142
amd_iommu_flush_all(struct amd_iommu * iommu)1143 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1144 {
1145 struct iommu_cmd cmd;
1146
1147 build_inv_all(&cmd);
1148
1149 iommu_queue_command(iommu, &cmd);
1150 iommu_completion_wait(iommu);
1151 }
1152
iommu_flush_irt(struct amd_iommu * iommu,u16 devid)1153 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1154 {
1155 struct iommu_cmd cmd;
1156
1157 build_inv_irt(&cmd, devid);
1158
1159 iommu_queue_command(iommu, &cmd);
1160 }
1161
amd_iommu_flush_irt_all(struct amd_iommu * iommu)1162 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1163 {
1164 u32 devid;
1165
1166 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1167 iommu_flush_irt(iommu, devid);
1168
1169 iommu_completion_wait(iommu);
1170 }
1171
iommu_flush_all_caches(struct amd_iommu * iommu)1172 void iommu_flush_all_caches(struct amd_iommu *iommu)
1173 {
1174 if (iommu_feature(iommu, FEATURE_IA)) {
1175 amd_iommu_flush_all(iommu);
1176 } else {
1177 amd_iommu_flush_dte_all(iommu);
1178 amd_iommu_flush_irt_all(iommu);
1179 amd_iommu_flush_tlb_all(iommu);
1180 }
1181 }
1182
1183 /*
1184 * Command send function for flushing on-device TLB
1185 */
device_flush_iotlb(struct iommu_dev_data * dev_data,u64 address,size_t size)1186 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1187 u64 address, size_t size)
1188 {
1189 struct amd_iommu *iommu;
1190 struct iommu_cmd cmd;
1191 int qdep;
1192
1193 qdep = dev_data->ats.qdep;
1194 iommu = amd_iommu_rlookup_table[dev_data->devid];
1195
1196 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1197
1198 return iommu_queue_command(iommu, &cmd);
1199 }
1200
device_flush_dte_alias(struct pci_dev * pdev,u16 alias,void * data)1201 static int device_flush_dte_alias(struct pci_dev *pdev, u16 alias, void *data)
1202 {
1203 struct amd_iommu *iommu = data;
1204
1205 return iommu_flush_dte(iommu, alias);
1206 }
1207
1208 /*
1209 * Command send function for invalidating a device table entry
1210 */
device_flush_dte(struct iommu_dev_data * dev_data)1211 static int device_flush_dte(struct iommu_dev_data *dev_data)
1212 {
1213 struct amd_iommu *iommu;
1214 u16 alias;
1215 int ret;
1216
1217 iommu = amd_iommu_rlookup_table[dev_data->devid];
1218
1219 if (dev_data->pdev)
1220 ret = pci_for_each_dma_alias(dev_data->pdev,
1221 device_flush_dte_alias, iommu);
1222 else
1223 ret = iommu_flush_dte(iommu, dev_data->devid);
1224 if (ret)
1225 return ret;
1226
1227 alias = amd_iommu_alias_table[dev_data->devid];
1228 if (alias != dev_data->devid) {
1229 ret = iommu_flush_dte(iommu, alias);
1230 if (ret)
1231 return ret;
1232 }
1233
1234 if (dev_data->ats.enabled)
1235 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1236
1237 return ret;
1238 }
1239
1240 /*
1241 * TLB invalidation function which is called from the mapping functions.
1242 * It invalidates a single PTE if the range to flush is within a single
1243 * page. Otherwise it flushes the whole TLB of the IOMMU.
1244 */
__domain_flush_pages(struct protection_domain * domain,u64 address,size_t size,int pde)1245 static void __domain_flush_pages(struct protection_domain *domain,
1246 u64 address, size_t size, int pde)
1247 {
1248 struct iommu_dev_data *dev_data;
1249 struct iommu_cmd cmd;
1250 int ret = 0, i;
1251
1252 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1253
1254 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1255 if (!domain->dev_iommu[i])
1256 continue;
1257
1258 /*
1259 * Devices of this domain are behind this IOMMU
1260 * We need a TLB flush
1261 */
1262 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1263 }
1264
1265 list_for_each_entry(dev_data, &domain->dev_list, list) {
1266
1267 if (!dev_data->ats.enabled)
1268 continue;
1269
1270 ret |= device_flush_iotlb(dev_data, address, size);
1271 }
1272
1273 WARN_ON(ret);
1274 }
1275
domain_flush_pages(struct protection_domain * domain,u64 address,size_t size,int pde)1276 static void domain_flush_pages(struct protection_domain *domain,
1277 u64 address, size_t size, int pde)
1278 {
1279 if (likely(!amd_iommu_np_cache)) {
1280 __domain_flush_pages(domain, address, size, pde);
1281 return;
1282 }
1283
1284 /*
1285 * When NpCache is on, we infer that we run in a VM and use a vIOMMU.
1286 * In such setups it is best to avoid flushes of ranges which are not
1287 * naturally aligned, since it would lead to flushes of unmodified
1288 * PTEs. Such flushes would require the hypervisor to do more work than
1289 * necessary. Therefore, perform repeated flushes of aligned ranges
1290 * until you cover the range. Each iteration flushes the smaller
1291 * between the natural alignment of the address that we flush and the
1292 * greatest naturally aligned region that fits in the range.
1293 */
1294 while (size != 0) {
1295 int addr_alignment = __ffs(address);
1296 int size_alignment = __fls(size);
1297 int min_alignment;
1298 size_t flush_size;
1299
1300 /*
1301 * size is always non-zero, but address might be zero, causing
1302 * addr_alignment to be negative. As the casting of the
1303 * argument in __ffs(address) to long might trim the high bits
1304 * of the address on x86-32, cast to long when doing the check.
1305 */
1306 if (likely((unsigned long)address != 0))
1307 min_alignment = min(addr_alignment, size_alignment);
1308 else
1309 min_alignment = size_alignment;
1310
1311 flush_size = 1ul << min_alignment;
1312
1313 __domain_flush_pages(domain, address, flush_size, pde);
1314 address += flush_size;
1315 size -= flush_size;
1316 }
1317 }
1318
1319 /* Flush the whole IO/TLB for a given protection domain - including PDE */
amd_iommu_domain_flush_tlb_pde(struct protection_domain * domain)1320 void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain)
1321 {
1322 domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1323 }
1324
amd_iommu_domain_flush_complete(struct protection_domain * domain)1325 void amd_iommu_domain_flush_complete(struct protection_domain *domain)
1326 {
1327 int i;
1328
1329 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1330 if (domain && !domain->dev_iommu[i])
1331 continue;
1332
1333 /*
1334 * Devices of this domain are behind this IOMMU
1335 * We need to wait for completion of all commands.
1336 */
1337 iommu_completion_wait(amd_iommus[i]);
1338 }
1339 }
1340
1341 /* Flush the not present cache if it exists */
domain_flush_np_cache(struct protection_domain * domain,dma_addr_t iova,size_t size)1342 static void domain_flush_np_cache(struct protection_domain *domain,
1343 dma_addr_t iova, size_t size)
1344 {
1345 if (unlikely(amd_iommu_np_cache)) {
1346 unsigned long flags;
1347
1348 spin_lock_irqsave(&domain->lock, flags);
1349 domain_flush_pages(domain, iova, size, 1);
1350 amd_iommu_domain_flush_complete(domain);
1351 spin_unlock_irqrestore(&domain->lock, flags);
1352 }
1353 }
1354
1355
1356 /*
1357 * This function flushes the DTEs for all devices in domain
1358 */
domain_flush_devices(struct protection_domain * domain)1359 static void domain_flush_devices(struct protection_domain *domain)
1360 {
1361 struct iommu_dev_data *dev_data;
1362
1363 list_for_each_entry(dev_data, &domain->dev_list, list)
1364 device_flush_dte(dev_data);
1365 }
1366
1367 /****************************************************************************
1368 *
1369 * The next functions belong to the domain allocation. A domain is
1370 * allocated for every IOMMU as the default domain. If device isolation
1371 * is enabled, every device get its own domain. The most important thing
1372 * about domains is the page table mapping the DMA address space they
1373 * contain.
1374 *
1375 ****************************************************************************/
1376
domain_id_alloc(void)1377 static u16 domain_id_alloc(void)
1378 {
1379 int id;
1380
1381 spin_lock(&pd_bitmap_lock);
1382 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1383 BUG_ON(id == 0);
1384 if (id > 0 && id < MAX_DOMAIN_ID)
1385 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1386 else
1387 id = 0;
1388 spin_unlock(&pd_bitmap_lock);
1389
1390 return id;
1391 }
1392
domain_id_free(int id)1393 static void domain_id_free(int id)
1394 {
1395 spin_lock(&pd_bitmap_lock);
1396 if (id > 0 && id < MAX_DOMAIN_ID)
1397 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1398 spin_unlock(&pd_bitmap_lock);
1399 }
1400
free_gcr3_tbl_level1(u64 * tbl)1401 static void free_gcr3_tbl_level1(u64 *tbl)
1402 {
1403 u64 *ptr;
1404 int i;
1405
1406 for (i = 0; i < 512; ++i) {
1407 if (!(tbl[i] & GCR3_VALID))
1408 continue;
1409
1410 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1411
1412 free_page((unsigned long)ptr);
1413 }
1414 }
1415
free_gcr3_tbl_level2(u64 * tbl)1416 static void free_gcr3_tbl_level2(u64 *tbl)
1417 {
1418 u64 *ptr;
1419 int i;
1420
1421 for (i = 0; i < 512; ++i) {
1422 if (!(tbl[i] & GCR3_VALID))
1423 continue;
1424
1425 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1426
1427 free_gcr3_tbl_level1(ptr);
1428 }
1429 }
1430
free_gcr3_table(struct protection_domain * domain)1431 static void free_gcr3_table(struct protection_domain *domain)
1432 {
1433 if (domain->glx == 2)
1434 free_gcr3_tbl_level2(domain->gcr3_tbl);
1435 else if (domain->glx == 1)
1436 free_gcr3_tbl_level1(domain->gcr3_tbl);
1437 else
1438 BUG_ON(domain->glx != 0);
1439
1440 free_page((unsigned long)domain->gcr3_tbl);
1441 }
1442
set_dte_entry(u16 devid,struct protection_domain * domain,bool ats,bool ppr)1443 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1444 bool ats, bool ppr)
1445 {
1446 u64 pte_root = 0;
1447 u64 flags = 0;
1448 u32 old_domid;
1449
1450 if (domain->iop.mode != PAGE_MODE_NONE)
1451 pte_root = iommu_virt_to_phys(domain->iop.root);
1452
1453 pte_root |= (domain->iop.mode & DEV_ENTRY_MODE_MASK)
1454 << DEV_ENTRY_MODE_SHIFT;
1455 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1456
1457 flags = amd_iommu_dev_table[devid].data[1];
1458
1459 if (ats)
1460 flags |= DTE_FLAG_IOTLB;
1461
1462 if (ppr) {
1463 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1464
1465 if (iommu_feature(iommu, FEATURE_EPHSUP))
1466 pte_root |= 1ULL << DEV_ENTRY_PPR;
1467 }
1468
1469 if (domain->flags & PD_IOMMUV2_MASK) {
1470 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1471 u64 glx = domain->glx;
1472 u64 tmp;
1473
1474 pte_root |= DTE_FLAG_GV;
1475 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1476
1477 /* First mask out possible old values for GCR3 table */
1478 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1479 flags &= ~tmp;
1480
1481 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1482 flags &= ~tmp;
1483
1484 /* Encode GCR3 table into DTE */
1485 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1486 pte_root |= tmp;
1487
1488 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1489 flags |= tmp;
1490
1491 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1492 flags |= tmp;
1493 }
1494
1495 flags &= ~DEV_DOMID_MASK;
1496 flags |= domain->id;
1497
1498 old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK;
1499 amd_iommu_dev_table[devid].data[1] = flags;
1500 amd_iommu_dev_table[devid].data[0] = pte_root;
1501
1502 /*
1503 * A kdump kernel might be replacing a domain ID that was copied from
1504 * the previous kernel--if so, it needs to flush the translation cache
1505 * entries for the old domain ID that is being overwritten
1506 */
1507 if (old_domid) {
1508 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1509
1510 amd_iommu_flush_tlb_domid(iommu, old_domid);
1511 }
1512 }
1513
clear_dte_entry(u16 devid)1514 static void clear_dte_entry(u16 devid)
1515 {
1516 /* remove entry from the device table seen by the hardware */
1517 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1518 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1519
1520 amd_iommu_apply_erratum_63(devid);
1521 }
1522
do_attach(struct iommu_dev_data * dev_data,struct protection_domain * domain)1523 static void do_attach(struct iommu_dev_data *dev_data,
1524 struct protection_domain *domain)
1525 {
1526 struct amd_iommu *iommu;
1527 bool ats;
1528
1529 iommu = amd_iommu_rlookup_table[dev_data->devid];
1530 ats = dev_data->ats.enabled;
1531
1532 /* Update data structures */
1533 dev_data->domain = domain;
1534 list_add(&dev_data->list, &domain->dev_list);
1535
1536 /* Do reference counting */
1537 domain->dev_iommu[iommu->index] += 1;
1538 domain->dev_cnt += 1;
1539
1540 /* Update device table */
1541 set_dte_entry(dev_data->devid, domain,
1542 ats, dev_data->iommu_v2);
1543 clone_aliases(dev_data->pdev);
1544
1545 device_flush_dte(dev_data);
1546 }
1547
do_detach(struct iommu_dev_data * dev_data)1548 static void do_detach(struct iommu_dev_data *dev_data)
1549 {
1550 struct protection_domain *domain = dev_data->domain;
1551 struct amd_iommu *iommu;
1552
1553 iommu = amd_iommu_rlookup_table[dev_data->devid];
1554
1555 /* Update data structures */
1556 dev_data->domain = NULL;
1557 list_del(&dev_data->list);
1558 clear_dte_entry(dev_data->devid);
1559 clone_aliases(dev_data->pdev);
1560
1561 /* Flush the DTE entry */
1562 device_flush_dte(dev_data);
1563
1564 /* Flush IOTLB */
1565 amd_iommu_domain_flush_tlb_pde(domain);
1566
1567 /* Wait for the flushes to finish */
1568 amd_iommu_domain_flush_complete(domain);
1569
1570 /* decrease reference counters - needs to happen after the flushes */
1571 domain->dev_iommu[iommu->index] -= 1;
1572 domain->dev_cnt -= 1;
1573 }
1574
pdev_iommuv2_disable(struct pci_dev * pdev)1575 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1576 {
1577 pci_disable_ats(pdev);
1578 pci_disable_pri(pdev);
1579 pci_disable_pasid(pdev);
1580 }
1581
pdev_iommuv2_enable(struct pci_dev * pdev)1582 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1583 {
1584 int ret;
1585
1586 /* Only allow access to user-accessible pages */
1587 ret = pci_enable_pasid(pdev, 0);
1588 if (ret)
1589 return ret;
1590
1591 /* First reset the PRI state of the device */
1592 ret = pci_reset_pri(pdev);
1593 if (ret)
1594 goto out_err_pasid;
1595
1596 /* Enable PRI */
1597 /* FIXME: Hardcode number of outstanding requests for now */
1598 ret = pci_enable_pri(pdev, 32);
1599 if (ret)
1600 goto out_err_pasid;
1601
1602 ret = pci_enable_ats(pdev, PAGE_SHIFT);
1603 if (ret)
1604 goto out_err_pri;
1605
1606 return 0;
1607
1608 out_err_pri:
1609 pci_disable_pri(pdev);
1610
1611 out_err_pasid:
1612 pci_disable_pasid(pdev);
1613
1614 return ret;
1615 }
1616
1617 /*
1618 * If a device is not yet associated with a domain, this function makes the
1619 * device visible in the domain
1620 */
attach_device(struct device * dev,struct protection_domain * domain)1621 static int attach_device(struct device *dev,
1622 struct protection_domain *domain)
1623 {
1624 struct iommu_dev_data *dev_data;
1625 struct pci_dev *pdev;
1626 unsigned long flags;
1627 int ret;
1628
1629 spin_lock_irqsave(&domain->lock, flags);
1630
1631 dev_data = dev_iommu_priv_get(dev);
1632
1633 spin_lock(&dev_data->lock);
1634
1635 ret = -EBUSY;
1636 if (dev_data->domain != NULL)
1637 goto out;
1638
1639 if (!dev_is_pci(dev))
1640 goto skip_ats_check;
1641
1642 pdev = to_pci_dev(dev);
1643 if (domain->flags & PD_IOMMUV2_MASK) {
1644 struct iommu_domain *def_domain = iommu_get_dma_domain(dev);
1645
1646 ret = -EINVAL;
1647 if (def_domain->type != IOMMU_DOMAIN_IDENTITY)
1648 goto out;
1649
1650 if (dev_data->iommu_v2) {
1651 if (pdev_iommuv2_enable(pdev) != 0)
1652 goto out;
1653
1654 dev_data->ats.enabled = true;
1655 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1656 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
1657 }
1658 } else if (amd_iommu_iotlb_sup &&
1659 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
1660 dev_data->ats.enabled = true;
1661 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1662 }
1663
1664 skip_ats_check:
1665 ret = 0;
1666
1667 do_attach(dev_data, domain);
1668
1669 /*
1670 * We might boot into a crash-kernel here. The crashed kernel
1671 * left the caches in the IOMMU dirty. So we have to flush
1672 * here to evict all dirty stuff.
1673 */
1674 amd_iommu_domain_flush_tlb_pde(domain);
1675
1676 amd_iommu_domain_flush_complete(domain);
1677
1678 out:
1679 spin_unlock(&dev_data->lock);
1680
1681 spin_unlock_irqrestore(&domain->lock, flags);
1682
1683 return ret;
1684 }
1685
1686 /*
1687 * Removes a device from a protection domain (with devtable_lock held)
1688 */
detach_device(struct device * dev)1689 static void detach_device(struct device *dev)
1690 {
1691 struct protection_domain *domain;
1692 struct iommu_dev_data *dev_data;
1693 unsigned long flags;
1694
1695 dev_data = dev_iommu_priv_get(dev);
1696 domain = dev_data->domain;
1697
1698 spin_lock_irqsave(&domain->lock, flags);
1699
1700 spin_lock(&dev_data->lock);
1701
1702 /*
1703 * First check if the device is still attached. It might already
1704 * be detached from its domain because the generic
1705 * iommu_detach_group code detached it and we try again here in
1706 * our alias handling.
1707 */
1708 if (WARN_ON(!dev_data->domain))
1709 goto out;
1710
1711 do_detach(dev_data);
1712
1713 if (!dev_is_pci(dev))
1714 goto out;
1715
1716 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
1717 pdev_iommuv2_disable(to_pci_dev(dev));
1718 else if (dev_data->ats.enabled)
1719 pci_disable_ats(to_pci_dev(dev));
1720
1721 dev_data->ats.enabled = false;
1722
1723 out:
1724 spin_unlock(&dev_data->lock);
1725
1726 spin_unlock_irqrestore(&domain->lock, flags);
1727 }
1728
amd_iommu_probe_device(struct device * dev)1729 static struct iommu_device *amd_iommu_probe_device(struct device *dev)
1730 {
1731 struct iommu_device *iommu_dev;
1732 struct amd_iommu *iommu;
1733 int ret, devid;
1734
1735 if (!check_device(dev))
1736 return ERR_PTR(-ENODEV);
1737
1738 devid = get_device_id(dev);
1739 iommu = amd_iommu_rlookup_table[devid];
1740
1741 if (dev_iommu_priv_get(dev))
1742 return &iommu->iommu;
1743
1744 ret = iommu_init_device(dev);
1745 if (ret) {
1746 if (ret != -ENOTSUPP)
1747 dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
1748 iommu_dev = ERR_PTR(ret);
1749 iommu_ignore_device(dev);
1750 } else {
1751 amd_iommu_set_pci_msi_domain(dev, iommu);
1752 iommu_dev = &iommu->iommu;
1753 }
1754
1755 iommu_completion_wait(iommu);
1756
1757 return iommu_dev;
1758 }
1759
amd_iommu_probe_finalize(struct device * dev)1760 static void amd_iommu_probe_finalize(struct device *dev)
1761 {
1762 /* Domains are initialized for this device - have a look what we ended up with */
1763 set_dma_ops(dev, NULL);
1764 iommu_setup_dma_ops(dev, 0, U64_MAX);
1765 }
1766
amd_iommu_release_device(struct device * dev)1767 static void amd_iommu_release_device(struct device *dev)
1768 {
1769 int devid = get_device_id(dev);
1770 struct amd_iommu *iommu;
1771
1772 if (!check_device(dev))
1773 return;
1774
1775 iommu = amd_iommu_rlookup_table[devid];
1776
1777 amd_iommu_uninit_device(dev);
1778 iommu_completion_wait(iommu);
1779 }
1780
amd_iommu_device_group(struct device * dev)1781 static struct iommu_group *amd_iommu_device_group(struct device *dev)
1782 {
1783 if (dev_is_pci(dev))
1784 return pci_device_group(dev);
1785
1786 return acpihid_device_group(dev);
1787 }
1788
1789 /*****************************************************************************
1790 *
1791 * The next functions belong to the dma_ops mapping/unmapping code.
1792 *
1793 *****************************************************************************/
1794
update_device_table(struct protection_domain * domain)1795 static void update_device_table(struct protection_domain *domain)
1796 {
1797 struct iommu_dev_data *dev_data;
1798
1799 list_for_each_entry(dev_data, &domain->dev_list, list) {
1800 set_dte_entry(dev_data->devid, domain,
1801 dev_data->ats.enabled, dev_data->iommu_v2);
1802 clone_aliases(dev_data->pdev);
1803 }
1804 }
1805
amd_iommu_update_and_flush_device_table(struct protection_domain * domain)1806 void amd_iommu_update_and_flush_device_table(struct protection_domain *domain)
1807 {
1808 update_device_table(domain);
1809 domain_flush_devices(domain);
1810 }
1811
amd_iommu_domain_update(struct protection_domain * domain)1812 void amd_iommu_domain_update(struct protection_domain *domain)
1813 {
1814 /* Update device table */
1815 amd_iommu_update_and_flush_device_table(domain);
1816
1817 /* Flush domain TLB(s) and wait for completion */
1818 amd_iommu_domain_flush_tlb_pde(domain);
1819 amd_iommu_domain_flush_complete(domain);
1820 }
1821
amd_iommu_init_api(void)1822 int __init amd_iommu_init_api(void)
1823 {
1824 int err;
1825
1826 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
1827 if (err)
1828 return err;
1829 #ifdef CONFIG_ARM_AMBA
1830 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
1831 if (err)
1832 return err;
1833 #endif
1834 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
1835 if (err)
1836 return err;
1837
1838 return 0;
1839 }
1840
1841 /*****************************************************************************
1842 *
1843 * The following functions belong to the exported interface of AMD IOMMU
1844 *
1845 * This interface allows access to lower level functions of the IOMMU
1846 * like protection domain handling and assignement of devices to domains
1847 * which is not possible with the dma_ops interface.
1848 *
1849 *****************************************************************************/
1850
cleanup_domain(struct protection_domain * domain)1851 static void cleanup_domain(struct protection_domain *domain)
1852 {
1853 struct iommu_dev_data *entry;
1854 unsigned long flags;
1855
1856 spin_lock_irqsave(&domain->lock, flags);
1857
1858 while (!list_empty(&domain->dev_list)) {
1859 entry = list_first_entry(&domain->dev_list,
1860 struct iommu_dev_data, list);
1861 BUG_ON(!entry->domain);
1862 do_detach(entry);
1863 }
1864
1865 spin_unlock_irqrestore(&domain->lock, flags);
1866 }
1867
protection_domain_free(struct protection_domain * domain)1868 static void protection_domain_free(struct protection_domain *domain)
1869 {
1870 if (!domain)
1871 return;
1872
1873 if (domain->id)
1874 domain_id_free(domain->id);
1875
1876 if (domain->iop.pgtbl_cfg.tlb)
1877 free_io_pgtable_ops(&domain->iop.iop.ops);
1878
1879 kfree(domain);
1880 }
1881
protection_domain_init_v1(struct protection_domain * domain,int mode)1882 static int protection_domain_init_v1(struct protection_domain *domain, int mode)
1883 {
1884 u64 *pt_root = NULL;
1885
1886 BUG_ON(mode < PAGE_MODE_NONE || mode > PAGE_MODE_6_LEVEL);
1887
1888 spin_lock_init(&domain->lock);
1889 domain->id = domain_id_alloc();
1890 if (!domain->id)
1891 return -ENOMEM;
1892 INIT_LIST_HEAD(&domain->dev_list);
1893
1894 if (mode != PAGE_MODE_NONE) {
1895 pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1896 if (!pt_root)
1897 return -ENOMEM;
1898 }
1899
1900 amd_iommu_domain_set_pgtable(domain, pt_root, mode);
1901
1902 return 0;
1903 }
1904
protection_domain_alloc(unsigned int type)1905 static struct protection_domain *protection_domain_alloc(unsigned int type)
1906 {
1907 struct io_pgtable_ops *pgtbl_ops;
1908 struct protection_domain *domain;
1909 int pgtable = amd_iommu_pgtable;
1910 int mode = DEFAULT_PGTABLE_LEVEL;
1911 int ret;
1912
1913 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1914 if (!domain)
1915 return NULL;
1916
1917 /*
1918 * Force IOMMU v1 page table when iommu=pt and
1919 * when allocating domain for pass-through devices.
1920 */
1921 if (type == IOMMU_DOMAIN_IDENTITY) {
1922 pgtable = AMD_IOMMU_V1;
1923 mode = PAGE_MODE_NONE;
1924 } else if (type == IOMMU_DOMAIN_UNMANAGED) {
1925 pgtable = AMD_IOMMU_V1;
1926 }
1927
1928 switch (pgtable) {
1929 case AMD_IOMMU_V1:
1930 ret = protection_domain_init_v1(domain, mode);
1931 break;
1932 default:
1933 ret = -EINVAL;
1934 }
1935
1936 if (ret)
1937 goto out_err;
1938
1939 pgtbl_ops = alloc_io_pgtable_ops(pgtable, &domain->iop.pgtbl_cfg, domain);
1940 if (!pgtbl_ops)
1941 goto out_err;
1942
1943 return domain;
1944 out_err:
1945 kfree(domain);
1946 return NULL;
1947 }
1948
amd_iommu_domain_alloc(unsigned type)1949 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
1950 {
1951 struct protection_domain *domain;
1952
1953 domain = protection_domain_alloc(type);
1954 if (!domain)
1955 return NULL;
1956
1957 domain->domain.geometry.aperture_start = 0;
1958 domain->domain.geometry.aperture_end = ~0ULL;
1959 domain->domain.geometry.force_aperture = true;
1960
1961 return &domain->domain;
1962 }
1963
amd_iommu_domain_free(struct iommu_domain * dom)1964 static void amd_iommu_domain_free(struct iommu_domain *dom)
1965 {
1966 struct protection_domain *domain;
1967
1968 domain = to_pdomain(dom);
1969
1970 if (domain->dev_cnt > 0)
1971 cleanup_domain(domain);
1972
1973 BUG_ON(domain->dev_cnt != 0);
1974
1975 if (!dom)
1976 return;
1977
1978 if (domain->flags & PD_IOMMUV2_MASK)
1979 free_gcr3_table(domain);
1980
1981 protection_domain_free(domain);
1982 }
1983
amd_iommu_detach_device(struct iommu_domain * dom,struct device * dev)1984 static void amd_iommu_detach_device(struct iommu_domain *dom,
1985 struct device *dev)
1986 {
1987 struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
1988 int devid = get_device_id(dev);
1989 struct amd_iommu *iommu;
1990
1991 if (!check_device(dev))
1992 return;
1993
1994 if (dev_data->domain != NULL)
1995 detach_device(dev);
1996
1997 iommu = amd_iommu_rlookup_table[devid];
1998 if (!iommu)
1999 return;
2000
2001 #ifdef CONFIG_IRQ_REMAP
2002 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2003 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2004 dev_data->use_vapic = 0;
2005 #endif
2006
2007 iommu_completion_wait(iommu);
2008 }
2009
amd_iommu_attach_device(struct iommu_domain * dom,struct device * dev)2010 static int amd_iommu_attach_device(struct iommu_domain *dom,
2011 struct device *dev)
2012 {
2013 struct protection_domain *domain = to_pdomain(dom);
2014 struct iommu_dev_data *dev_data;
2015 struct amd_iommu *iommu;
2016 int ret;
2017
2018 if (!check_device(dev))
2019 return -EINVAL;
2020
2021 dev_data = dev_iommu_priv_get(dev);
2022 dev_data->defer_attach = false;
2023
2024 iommu = amd_iommu_rlookup_table[dev_data->devid];
2025 if (!iommu)
2026 return -EINVAL;
2027
2028 if (dev_data->domain)
2029 detach_device(dev);
2030
2031 ret = attach_device(dev, domain);
2032
2033 #ifdef CONFIG_IRQ_REMAP
2034 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
2035 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
2036 dev_data->use_vapic = 1;
2037 else
2038 dev_data->use_vapic = 0;
2039 }
2040 #endif
2041
2042 iommu_completion_wait(iommu);
2043
2044 return ret;
2045 }
2046
amd_iommu_iotlb_sync_map(struct iommu_domain * dom,unsigned long iova,size_t size)2047 static void amd_iommu_iotlb_sync_map(struct iommu_domain *dom,
2048 unsigned long iova, size_t size)
2049 {
2050 struct protection_domain *domain = to_pdomain(dom);
2051 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2052
2053 if (ops->map)
2054 domain_flush_np_cache(domain, iova, size);
2055 }
2056
amd_iommu_map(struct iommu_domain * dom,unsigned long iova,phys_addr_t paddr,size_t page_size,int iommu_prot,gfp_t gfp)2057 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2058 phys_addr_t paddr, size_t page_size, int iommu_prot,
2059 gfp_t gfp)
2060 {
2061 struct protection_domain *domain = to_pdomain(dom);
2062 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2063 int prot = 0;
2064 int ret = -EINVAL;
2065
2066 if ((amd_iommu_pgtable == AMD_IOMMU_V1) &&
2067 (domain->iop.mode == PAGE_MODE_NONE))
2068 return -EINVAL;
2069
2070 if (iommu_prot & IOMMU_READ)
2071 prot |= IOMMU_PROT_IR;
2072 if (iommu_prot & IOMMU_WRITE)
2073 prot |= IOMMU_PROT_IW;
2074
2075 if (ops->map)
2076 ret = ops->map(ops, iova, paddr, page_size, prot, gfp);
2077
2078 return ret;
2079 }
2080
amd_iommu_iotlb_gather_add_page(struct iommu_domain * domain,struct iommu_iotlb_gather * gather,unsigned long iova,size_t size)2081 static void amd_iommu_iotlb_gather_add_page(struct iommu_domain *domain,
2082 struct iommu_iotlb_gather *gather,
2083 unsigned long iova, size_t size)
2084 {
2085 /*
2086 * AMD's IOMMU can flush as many pages as necessary in a single flush.
2087 * Unless we run in a virtual machine, which can be inferred according
2088 * to whether "non-present cache" is on, it is probably best to prefer
2089 * (potentially) too extensive TLB flushing (i.e., more misses) over
2090 * mutliple TLB flushes (i.e., more flushes). For virtual machines the
2091 * hypervisor needs to synchronize the host IOMMU PTEs with those of
2092 * the guest, and the trade-off is different: unnecessary TLB flushes
2093 * should be avoided.
2094 */
2095 if (amd_iommu_np_cache &&
2096 iommu_iotlb_gather_is_disjoint(gather, iova, size))
2097 iommu_iotlb_sync(domain, gather);
2098
2099 iommu_iotlb_gather_add_range(gather, iova, size);
2100 }
2101
amd_iommu_unmap(struct iommu_domain * dom,unsigned long iova,size_t page_size,struct iommu_iotlb_gather * gather)2102 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2103 size_t page_size,
2104 struct iommu_iotlb_gather *gather)
2105 {
2106 struct protection_domain *domain = to_pdomain(dom);
2107 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2108 size_t r;
2109
2110 if ((amd_iommu_pgtable == AMD_IOMMU_V1) &&
2111 (domain->iop.mode == PAGE_MODE_NONE))
2112 return 0;
2113
2114 r = (ops->unmap) ? ops->unmap(ops, iova, page_size, gather) : 0;
2115
2116 amd_iommu_iotlb_gather_add_page(dom, gather, iova, page_size);
2117
2118 return r;
2119 }
2120
amd_iommu_iova_to_phys(struct iommu_domain * dom,dma_addr_t iova)2121 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2122 dma_addr_t iova)
2123 {
2124 struct protection_domain *domain = to_pdomain(dom);
2125 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2126
2127 return ops->iova_to_phys(ops, iova);
2128 }
2129
amd_iommu_capable(enum iommu_cap cap)2130 static bool amd_iommu_capable(enum iommu_cap cap)
2131 {
2132 switch (cap) {
2133 case IOMMU_CAP_CACHE_COHERENCY:
2134 return true;
2135 case IOMMU_CAP_INTR_REMAP:
2136 return (irq_remapping_enabled == 1);
2137 case IOMMU_CAP_NOEXEC:
2138 return false;
2139 default:
2140 break;
2141 }
2142
2143 return false;
2144 }
2145
amd_iommu_get_resv_regions(struct device * dev,struct list_head * head)2146 static void amd_iommu_get_resv_regions(struct device *dev,
2147 struct list_head *head)
2148 {
2149 struct iommu_resv_region *region;
2150 struct unity_map_entry *entry;
2151 int devid;
2152
2153 devid = get_device_id(dev);
2154 if (devid < 0)
2155 return;
2156
2157 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
2158 int type, prot = 0;
2159 size_t length;
2160
2161 if (devid < entry->devid_start || devid > entry->devid_end)
2162 continue;
2163
2164 type = IOMMU_RESV_DIRECT;
2165 length = entry->address_end - entry->address_start;
2166 if (entry->prot & IOMMU_PROT_IR)
2167 prot |= IOMMU_READ;
2168 if (entry->prot & IOMMU_PROT_IW)
2169 prot |= IOMMU_WRITE;
2170 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
2171 /* Exclusion range */
2172 type = IOMMU_RESV_RESERVED;
2173
2174 region = iommu_alloc_resv_region(entry->address_start,
2175 length, prot, type);
2176 if (!region) {
2177 dev_err(dev, "Out of memory allocating dm-regions\n");
2178 return;
2179 }
2180 list_add_tail(®ion->list, head);
2181 }
2182
2183 region = iommu_alloc_resv_region(MSI_RANGE_START,
2184 MSI_RANGE_END - MSI_RANGE_START + 1,
2185 0, IOMMU_RESV_MSI);
2186 if (!region)
2187 return;
2188 list_add_tail(®ion->list, head);
2189
2190 region = iommu_alloc_resv_region(HT_RANGE_START,
2191 HT_RANGE_END - HT_RANGE_START + 1,
2192 0, IOMMU_RESV_RESERVED);
2193 if (!region)
2194 return;
2195 list_add_tail(®ion->list, head);
2196 }
2197
amd_iommu_is_attach_deferred(struct iommu_domain * domain,struct device * dev)2198 bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
2199 struct device *dev)
2200 {
2201 struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
2202
2203 return dev_data->defer_attach;
2204 }
2205 EXPORT_SYMBOL_GPL(amd_iommu_is_attach_deferred);
2206
amd_iommu_flush_iotlb_all(struct iommu_domain * domain)2207 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
2208 {
2209 struct protection_domain *dom = to_pdomain(domain);
2210 unsigned long flags;
2211
2212 spin_lock_irqsave(&dom->lock, flags);
2213 amd_iommu_domain_flush_tlb_pde(dom);
2214 amd_iommu_domain_flush_complete(dom);
2215 spin_unlock_irqrestore(&dom->lock, flags);
2216 }
2217
amd_iommu_iotlb_sync(struct iommu_domain * domain,struct iommu_iotlb_gather * gather)2218 static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
2219 struct iommu_iotlb_gather *gather)
2220 {
2221 struct protection_domain *dom = to_pdomain(domain);
2222 unsigned long flags;
2223
2224 spin_lock_irqsave(&dom->lock, flags);
2225 domain_flush_pages(dom, gather->start, gather->end - gather->start + 1, 1);
2226 amd_iommu_domain_flush_complete(dom);
2227 spin_unlock_irqrestore(&dom->lock, flags);
2228 }
2229
amd_iommu_def_domain_type(struct device * dev)2230 static int amd_iommu_def_domain_type(struct device *dev)
2231 {
2232 struct iommu_dev_data *dev_data;
2233
2234 dev_data = dev_iommu_priv_get(dev);
2235 if (!dev_data)
2236 return 0;
2237
2238 /*
2239 * Do not identity map IOMMUv2 capable devices when memory encryption is
2240 * active, because some of those devices (AMD GPUs) don't have the
2241 * encryption bit in their DMA-mask and require remapping.
2242 */
2243 if (!mem_encrypt_active() && dev_data->iommu_v2)
2244 return IOMMU_DOMAIN_IDENTITY;
2245
2246 return 0;
2247 }
2248
2249 const struct iommu_ops amd_iommu_ops = {
2250 .capable = amd_iommu_capable,
2251 .domain_alloc = amd_iommu_domain_alloc,
2252 .domain_free = amd_iommu_domain_free,
2253 .attach_dev = amd_iommu_attach_device,
2254 .detach_dev = amd_iommu_detach_device,
2255 .map = amd_iommu_map,
2256 .iotlb_sync_map = amd_iommu_iotlb_sync_map,
2257 .unmap = amd_iommu_unmap,
2258 .iova_to_phys = amd_iommu_iova_to_phys,
2259 .probe_device = amd_iommu_probe_device,
2260 .release_device = amd_iommu_release_device,
2261 .probe_finalize = amd_iommu_probe_finalize,
2262 .device_group = amd_iommu_device_group,
2263 .get_resv_regions = amd_iommu_get_resv_regions,
2264 .put_resv_regions = generic_iommu_put_resv_regions,
2265 .is_attach_deferred = amd_iommu_is_attach_deferred,
2266 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
2267 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
2268 .iotlb_sync = amd_iommu_iotlb_sync,
2269 .def_domain_type = amd_iommu_def_domain_type,
2270 };
2271
2272 /*****************************************************************************
2273 *
2274 * The next functions do a basic initialization of IOMMU for pass through
2275 * mode
2276 *
2277 * In passthrough mode the IOMMU is initialized and enabled but not used for
2278 * DMA-API translation.
2279 *
2280 *****************************************************************************/
2281
2282 /* IOMMUv2 specific functions */
amd_iommu_register_ppr_notifier(struct notifier_block * nb)2283 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
2284 {
2285 return atomic_notifier_chain_register(&ppr_notifier, nb);
2286 }
2287 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
2288
amd_iommu_unregister_ppr_notifier(struct notifier_block * nb)2289 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
2290 {
2291 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
2292 }
2293 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
2294
amd_iommu_domain_direct_map(struct iommu_domain * dom)2295 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
2296 {
2297 struct protection_domain *domain = to_pdomain(dom);
2298 unsigned long flags;
2299
2300 spin_lock_irqsave(&domain->lock, flags);
2301
2302 if (domain->iop.pgtbl_cfg.tlb)
2303 free_io_pgtable_ops(&domain->iop.iop.ops);
2304
2305 spin_unlock_irqrestore(&domain->lock, flags);
2306 }
2307 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
2308
amd_iommu_domain_enable_v2(struct iommu_domain * dom,int pasids)2309 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
2310 {
2311 struct protection_domain *domain = to_pdomain(dom);
2312 unsigned long flags;
2313 int levels, ret;
2314
2315 /* Number of GCR3 table levels required */
2316 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
2317 levels += 1;
2318
2319 if (levels > amd_iommu_max_glx_val)
2320 return -EINVAL;
2321
2322 spin_lock_irqsave(&domain->lock, flags);
2323
2324 /*
2325 * Save us all sanity checks whether devices already in the
2326 * domain support IOMMUv2. Just force that the domain has no
2327 * devices attached when it is switched into IOMMUv2 mode.
2328 */
2329 ret = -EBUSY;
2330 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
2331 goto out;
2332
2333 ret = -ENOMEM;
2334 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
2335 if (domain->gcr3_tbl == NULL)
2336 goto out;
2337
2338 domain->glx = levels;
2339 domain->flags |= PD_IOMMUV2_MASK;
2340
2341 amd_iommu_domain_update(domain);
2342
2343 ret = 0;
2344
2345 out:
2346 spin_unlock_irqrestore(&domain->lock, flags);
2347
2348 return ret;
2349 }
2350 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
2351
__flush_pasid(struct protection_domain * domain,u32 pasid,u64 address,bool size)2352 static int __flush_pasid(struct protection_domain *domain, u32 pasid,
2353 u64 address, bool size)
2354 {
2355 struct iommu_dev_data *dev_data;
2356 struct iommu_cmd cmd;
2357 int i, ret;
2358
2359 if (!(domain->flags & PD_IOMMUV2_MASK))
2360 return -EINVAL;
2361
2362 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
2363
2364 /*
2365 * IOMMU TLB needs to be flushed before Device TLB to
2366 * prevent device TLB refill from IOMMU TLB
2367 */
2368 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
2369 if (domain->dev_iommu[i] == 0)
2370 continue;
2371
2372 ret = iommu_queue_command(amd_iommus[i], &cmd);
2373 if (ret != 0)
2374 goto out;
2375 }
2376
2377 /* Wait until IOMMU TLB flushes are complete */
2378 amd_iommu_domain_flush_complete(domain);
2379
2380 /* Now flush device TLBs */
2381 list_for_each_entry(dev_data, &domain->dev_list, list) {
2382 struct amd_iommu *iommu;
2383 int qdep;
2384
2385 /*
2386 There might be non-IOMMUv2 capable devices in an IOMMUv2
2387 * domain.
2388 */
2389 if (!dev_data->ats.enabled)
2390 continue;
2391
2392 qdep = dev_data->ats.qdep;
2393 iommu = amd_iommu_rlookup_table[dev_data->devid];
2394
2395 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
2396 qdep, address, size);
2397
2398 ret = iommu_queue_command(iommu, &cmd);
2399 if (ret != 0)
2400 goto out;
2401 }
2402
2403 /* Wait until all device TLBs are flushed */
2404 amd_iommu_domain_flush_complete(domain);
2405
2406 ret = 0;
2407
2408 out:
2409
2410 return ret;
2411 }
2412
__amd_iommu_flush_page(struct protection_domain * domain,u32 pasid,u64 address)2413 static int __amd_iommu_flush_page(struct protection_domain *domain, u32 pasid,
2414 u64 address)
2415 {
2416 return __flush_pasid(domain, pasid, address, false);
2417 }
2418
amd_iommu_flush_page(struct iommu_domain * dom,u32 pasid,u64 address)2419 int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
2420 u64 address)
2421 {
2422 struct protection_domain *domain = to_pdomain(dom);
2423 unsigned long flags;
2424 int ret;
2425
2426 spin_lock_irqsave(&domain->lock, flags);
2427 ret = __amd_iommu_flush_page(domain, pasid, address);
2428 spin_unlock_irqrestore(&domain->lock, flags);
2429
2430 return ret;
2431 }
2432 EXPORT_SYMBOL(amd_iommu_flush_page);
2433
__amd_iommu_flush_tlb(struct protection_domain * domain,u32 pasid)2434 static int __amd_iommu_flush_tlb(struct protection_domain *domain, u32 pasid)
2435 {
2436 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
2437 true);
2438 }
2439
amd_iommu_flush_tlb(struct iommu_domain * dom,u32 pasid)2440 int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid)
2441 {
2442 struct protection_domain *domain = to_pdomain(dom);
2443 unsigned long flags;
2444 int ret;
2445
2446 spin_lock_irqsave(&domain->lock, flags);
2447 ret = __amd_iommu_flush_tlb(domain, pasid);
2448 spin_unlock_irqrestore(&domain->lock, flags);
2449
2450 return ret;
2451 }
2452 EXPORT_SYMBOL(amd_iommu_flush_tlb);
2453
__get_gcr3_pte(u64 * root,int level,u32 pasid,bool alloc)2454 static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)
2455 {
2456 int index;
2457 u64 *pte;
2458
2459 while (true) {
2460
2461 index = (pasid >> (9 * level)) & 0x1ff;
2462 pte = &root[index];
2463
2464 if (level == 0)
2465 break;
2466
2467 if (!(*pte & GCR3_VALID)) {
2468 if (!alloc)
2469 return NULL;
2470
2471 root = (void *)get_zeroed_page(GFP_ATOMIC);
2472 if (root == NULL)
2473 return NULL;
2474
2475 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
2476 }
2477
2478 root = iommu_phys_to_virt(*pte & PAGE_MASK);
2479
2480 level -= 1;
2481 }
2482
2483 return pte;
2484 }
2485
__set_gcr3(struct protection_domain * domain,u32 pasid,unsigned long cr3)2486 static int __set_gcr3(struct protection_domain *domain, u32 pasid,
2487 unsigned long cr3)
2488 {
2489 u64 *pte;
2490
2491 if (domain->iop.mode != PAGE_MODE_NONE)
2492 return -EINVAL;
2493
2494 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
2495 if (pte == NULL)
2496 return -ENOMEM;
2497
2498 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
2499
2500 return __amd_iommu_flush_tlb(domain, pasid);
2501 }
2502
__clear_gcr3(struct protection_domain * domain,u32 pasid)2503 static int __clear_gcr3(struct protection_domain *domain, u32 pasid)
2504 {
2505 u64 *pte;
2506
2507 if (domain->iop.mode != PAGE_MODE_NONE)
2508 return -EINVAL;
2509
2510 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
2511 if (pte == NULL)
2512 return 0;
2513
2514 *pte = 0;
2515
2516 return __amd_iommu_flush_tlb(domain, pasid);
2517 }
2518
amd_iommu_domain_set_gcr3(struct iommu_domain * dom,u32 pasid,unsigned long cr3)2519 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
2520 unsigned long cr3)
2521 {
2522 struct protection_domain *domain = to_pdomain(dom);
2523 unsigned long flags;
2524 int ret;
2525
2526 spin_lock_irqsave(&domain->lock, flags);
2527 ret = __set_gcr3(domain, pasid, cr3);
2528 spin_unlock_irqrestore(&domain->lock, flags);
2529
2530 return ret;
2531 }
2532 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
2533
amd_iommu_domain_clear_gcr3(struct iommu_domain * dom,u32 pasid)2534 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid)
2535 {
2536 struct protection_domain *domain = to_pdomain(dom);
2537 unsigned long flags;
2538 int ret;
2539
2540 spin_lock_irqsave(&domain->lock, flags);
2541 ret = __clear_gcr3(domain, pasid);
2542 spin_unlock_irqrestore(&domain->lock, flags);
2543
2544 return ret;
2545 }
2546 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
2547
amd_iommu_complete_ppr(struct pci_dev * pdev,u32 pasid,int status,int tag)2548 int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
2549 int status, int tag)
2550 {
2551 struct iommu_dev_data *dev_data;
2552 struct amd_iommu *iommu;
2553 struct iommu_cmd cmd;
2554
2555 dev_data = dev_iommu_priv_get(&pdev->dev);
2556 iommu = amd_iommu_rlookup_table[dev_data->devid];
2557
2558 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
2559 tag, dev_data->pri_tlp);
2560
2561 return iommu_queue_command(iommu, &cmd);
2562 }
2563 EXPORT_SYMBOL(amd_iommu_complete_ppr);
2564
amd_iommu_device_info(struct pci_dev * pdev,struct amd_iommu_device_info * info)2565 int amd_iommu_device_info(struct pci_dev *pdev,
2566 struct amd_iommu_device_info *info)
2567 {
2568 int max_pasids;
2569 int pos;
2570
2571 if (pdev == NULL || info == NULL)
2572 return -EINVAL;
2573
2574 if (!amd_iommu_v2_supported())
2575 return -EINVAL;
2576
2577 memset(info, 0, sizeof(*info));
2578
2579 if (pci_ats_supported(pdev))
2580 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
2581
2582 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2583 if (pos)
2584 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
2585
2586 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
2587 if (pos) {
2588 int features;
2589
2590 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
2591 max_pasids = min(max_pasids, (1 << 20));
2592
2593 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
2594 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
2595
2596 features = pci_pasid_features(pdev);
2597 if (features & PCI_PASID_CAP_EXEC)
2598 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
2599 if (features & PCI_PASID_CAP_PRIV)
2600 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
2601 }
2602
2603 return 0;
2604 }
2605 EXPORT_SYMBOL(amd_iommu_device_info);
2606
2607 #ifdef CONFIG_IRQ_REMAP
2608
2609 /*****************************************************************************
2610 *
2611 * Interrupt Remapping Implementation
2612 *
2613 *****************************************************************************/
2614
2615 static struct irq_chip amd_ir_chip;
2616 static DEFINE_SPINLOCK(iommu_table_lock);
2617
set_dte_irq_entry(u16 devid,struct irq_remap_table * table)2618 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
2619 {
2620 u64 dte;
2621
2622 dte = amd_iommu_dev_table[devid].data[2];
2623 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
2624 dte |= iommu_virt_to_phys(table->table);
2625 dte |= DTE_IRQ_REMAP_INTCTL;
2626 dte |= DTE_INTTABLEN;
2627 dte |= DTE_IRQ_REMAP_ENABLE;
2628
2629 amd_iommu_dev_table[devid].data[2] = dte;
2630 }
2631
get_irq_table(u16 devid)2632 static struct irq_remap_table *get_irq_table(u16 devid)
2633 {
2634 struct irq_remap_table *table;
2635
2636 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
2637 "%s: no iommu for devid %x\n", __func__, devid))
2638 return NULL;
2639
2640 table = irq_lookup_table[devid];
2641 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
2642 return NULL;
2643
2644 return table;
2645 }
2646
__alloc_irq_table(void)2647 static struct irq_remap_table *__alloc_irq_table(void)
2648 {
2649 struct irq_remap_table *table;
2650
2651 table = kzalloc(sizeof(*table), GFP_KERNEL);
2652 if (!table)
2653 return NULL;
2654
2655 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
2656 if (!table->table) {
2657 kfree(table);
2658 return NULL;
2659 }
2660 raw_spin_lock_init(&table->lock);
2661
2662 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2663 memset(table->table, 0,
2664 MAX_IRQS_PER_TABLE * sizeof(u32));
2665 else
2666 memset(table->table, 0,
2667 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
2668 return table;
2669 }
2670
set_remap_table_entry(struct amd_iommu * iommu,u16 devid,struct irq_remap_table * table)2671 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
2672 struct irq_remap_table *table)
2673 {
2674 irq_lookup_table[devid] = table;
2675 set_dte_irq_entry(devid, table);
2676 iommu_flush_dte(iommu, devid);
2677 }
2678
set_remap_table_entry_alias(struct pci_dev * pdev,u16 alias,void * data)2679 static int set_remap_table_entry_alias(struct pci_dev *pdev, u16 alias,
2680 void *data)
2681 {
2682 struct irq_remap_table *table = data;
2683
2684 irq_lookup_table[alias] = table;
2685 set_dte_irq_entry(alias, table);
2686
2687 iommu_flush_dte(amd_iommu_rlookup_table[alias], alias);
2688
2689 return 0;
2690 }
2691
alloc_irq_table(u16 devid,struct pci_dev * pdev)2692 static struct irq_remap_table *alloc_irq_table(u16 devid, struct pci_dev *pdev)
2693 {
2694 struct irq_remap_table *table = NULL;
2695 struct irq_remap_table *new_table = NULL;
2696 struct amd_iommu *iommu;
2697 unsigned long flags;
2698 u16 alias;
2699
2700 spin_lock_irqsave(&iommu_table_lock, flags);
2701
2702 iommu = amd_iommu_rlookup_table[devid];
2703 if (!iommu)
2704 goto out_unlock;
2705
2706 table = irq_lookup_table[devid];
2707 if (table)
2708 goto out_unlock;
2709
2710 alias = amd_iommu_alias_table[devid];
2711 table = irq_lookup_table[alias];
2712 if (table) {
2713 set_remap_table_entry(iommu, devid, table);
2714 goto out_wait;
2715 }
2716 spin_unlock_irqrestore(&iommu_table_lock, flags);
2717
2718 /* Nothing there yet, allocate new irq remapping table */
2719 new_table = __alloc_irq_table();
2720 if (!new_table)
2721 return NULL;
2722
2723 spin_lock_irqsave(&iommu_table_lock, flags);
2724
2725 table = irq_lookup_table[devid];
2726 if (table)
2727 goto out_unlock;
2728
2729 table = irq_lookup_table[alias];
2730 if (table) {
2731 set_remap_table_entry(iommu, devid, table);
2732 goto out_wait;
2733 }
2734
2735 table = new_table;
2736 new_table = NULL;
2737
2738 if (pdev)
2739 pci_for_each_dma_alias(pdev, set_remap_table_entry_alias,
2740 table);
2741 else
2742 set_remap_table_entry(iommu, devid, table);
2743
2744 if (devid != alias)
2745 set_remap_table_entry(iommu, alias, table);
2746
2747 out_wait:
2748 iommu_completion_wait(iommu);
2749
2750 out_unlock:
2751 spin_unlock_irqrestore(&iommu_table_lock, flags);
2752
2753 if (new_table) {
2754 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
2755 kfree(new_table);
2756 }
2757 return table;
2758 }
2759
alloc_irq_index(u16 devid,int count,bool align,struct pci_dev * pdev)2760 static int alloc_irq_index(u16 devid, int count, bool align,
2761 struct pci_dev *pdev)
2762 {
2763 struct irq_remap_table *table;
2764 int index, c, alignment = 1;
2765 unsigned long flags;
2766 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
2767
2768 if (!iommu)
2769 return -ENODEV;
2770
2771 table = alloc_irq_table(devid, pdev);
2772 if (!table)
2773 return -ENODEV;
2774
2775 if (align)
2776 alignment = roundup_pow_of_two(count);
2777
2778 raw_spin_lock_irqsave(&table->lock, flags);
2779
2780 /* Scan table for free entries */
2781 for (index = ALIGN(table->min_index, alignment), c = 0;
2782 index < MAX_IRQS_PER_TABLE;) {
2783 if (!iommu->irte_ops->is_allocated(table, index)) {
2784 c += 1;
2785 } else {
2786 c = 0;
2787 index = ALIGN(index + 1, alignment);
2788 continue;
2789 }
2790
2791 if (c == count) {
2792 for (; c != 0; --c)
2793 iommu->irte_ops->set_allocated(table, index - c + 1);
2794
2795 index -= count - 1;
2796 goto out;
2797 }
2798
2799 index++;
2800 }
2801
2802 index = -ENOSPC;
2803
2804 out:
2805 raw_spin_unlock_irqrestore(&table->lock, flags);
2806
2807 return index;
2808 }
2809
modify_irte_ga(u16 devid,int index,struct irte_ga * irte,struct amd_ir_data * data)2810 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
2811 struct amd_ir_data *data)
2812 {
2813 bool ret;
2814 struct irq_remap_table *table;
2815 struct amd_iommu *iommu;
2816 unsigned long flags;
2817 struct irte_ga *entry;
2818
2819 iommu = amd_iommu_rlookup_table[devid];
2820 if (iommu == NULL)
2821 return -EINVAL;
2822
2823 table = get_irq_table(devid);
2824 if (!table)
2825 return -ENOMEM;
2826
2827 raw_spin_lock_irqsave(&table->lock, flags);
2828
2829 entry = (struct irte_ga *)table->table;
2830 entry = &entry[index];
2831
2832 ret = cmpxchg_double(&entry->lo.val, &entry->hi.val,
2833 entry->lo.val, entry->hi.val,
2834 irte->lo.val, irte->hi.val);
2835 /*
2836 * We use cmpxchg16 to atomically update the 128-bit IRTE,
2837 * and it cannot be updated by the hardware or other processors
2838 * behind us, so the return value of cmpxchg16 should be the
2839 * same as the old value.
2840 */
2841 WARN_ON(!ret);
2842
2843 if (data)
2844 data->ref = entry;
2845
2846 raw_spin_unlock_irqrestore(&table->lock, flags);
2847
2848 iommu_flush_irt(iommu, devid);
2849 iommu_completion_wait(iommu);
2850
2851 return 0;
2852 }
2853
modify_irte(u16 devid,int index,union irte * irte)2854 static int modify_irte(u16 devid, int index, union irte *irte)
2855 {
2856 struct irq_remap_table *table;
2857 struct amd_iommu *iommu;
2858 unsigned long flags;
2859
2860 iommu = amd_iommu_rlookup_table[devid];
2861 if (iommu == NULL)
2862 return -EINVAL;
2863
2864 table = get_irq_table(devid);
2865 if (!table)
2866 return -ENOMEM;
2867
2868 raw_spin_lock_irqsave(&table->lock, flags);
2869 table->table[index] = irte->val;
2870 raw_spin_unlock_irqrestore(&table->lock, flags);
2871
2872 iommu_flush_irt(iommu, devid);
2873 iommu_completion_wait(iommu);
2874
2875 return 0;
2876 }
2877
free_irte(u16 devid,int index)2878 static void free_irte(u16 devid, int index)
2879 {
2880 struct irq_remap_table *table;
2881 struct amd_iommu *iommu;
2882 unsigned long flags;
2883
2884 iommu = amd_iommu_rlookup_table[devid];
2885 if (iommu == NULL)
2886 return;
2887
2888 table = get_irq_table(devid);
2889 if (!table)
2890 return;
2891
2892 raw_spin_lock_irqsave(&table->lock, flags);
2893 iommu->irte_ops->clear_allocated(table, index);
2894 raw_spin_unlock_irqrestore(&table->lock, flags);
2895
2896 iommu_flush_irt(iommu, devid);
2897 iommu_completion_wait(iommu);
2898 }
2899
irte_prepare(void * entry,u32 delivery_mode,bool dest_mode,u8 vector,u32 dest_apicid,int devid)2900 static void irte_prepare(void *entry,
2901 u32 delivery_mode, bool dest_mode,
2902 u8 vector, u32 dest_apicid, int devid)
2903 {
2904 union irte *irte = (union irte *) entry;
2905
2906 irte->val = 0;
2907 irte->fields.vector = vector;
2908 irte->fields.int_type = delivery_mode;
2909 irte->fields.destination = dest_apicid;
2910 irte->fields.dm = dest_mode;
2911 irte->fields.valid = 1;
2912 }
2913
irte_ga_prepare(void * entry,u32 delivery_mode,bool dest_mode,u8 vector,u32 dest_apicid,int devid)2914 static void irte_ga_prepare(void *entry,
2915 u32 delivery_mode, bool dest_mode,
2916 u8 vector, u32 dest_apicid, int devid)
2917 {
2918 struct irte_ga *irte = (struct irte_ga *) entry;
2919
2920 irte->lo.val = 0;
2921 irte->hi.val = 0;
2922 irte->lo.fields_remap.int_type = delivery_mode;
2923 irte->lo.fields_remap.dm = dest_mode;
2924 irte->hi.fields.vector = vector;
2925 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
2926 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
2927 irte->lo.fields_remap.valid = 1;
2928 }
2929
irte_activate(void * entry,u16 devid,u16 index)2930 static void irte_activate(void *entry, u16 devid, u16 index)
2931 {
2932 union irte *irte = (union irte *) entry;
2933
2934 irte->fields.valid = 1;
2935 modify_irte(devid, index, irte);
2936 }
2937
irte_ga_activate(void * entry,u16 devid,u16 index)2938 static void irte_ga_activate(void *entry, u16 devid, u16 index)
2939 {
2940 struct irte_ga *irte = (struct irte_ga *) entry;
2941
2942 irte->lo.fields_remap.valid = 1;
2943 modify_irte_ga(devid, index, irte, NULL);
2944 }
2945
irte_deactivate(void * entry,u16 devid,u16 index)2946 static void irte_deactivate(void *entry, u16 devid, u16 index)
2947 {
2948 union irte *irte = (union irte *) entry;
2949
2950 irte->fields.valid = 0;
2951 modify_irte(devid, index, irte);
2952 }
2953
irte_ga_deactivate(void * entry,u16 devid,u16 index)2954 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
2955 {
2956 struct irte_ga *irte = (struct irte_ga *) entry;
2957
2958 irte->lo.fields_remap.valid = 0;
2959 modify_irte_ga(devid, index, irte, NULL);
2960 }
2961
irte_set_affinity(void * entry,u16 devid,u16 index,u8 vector,u32 dest_apicid)2962 static void irte_set_affinity(void *entry, u16 devid, u16 index,
2963 u8 vector, u32 dest_apicid)
2964 {
2965 union irte *irte = (union irte *) entry;
2966
2967 irte->fields.vector = vector;
2968 irte->fields.destination = dest_apicid;
2969 modify_irte(devid, index, irte);
2970 }
2971
irte_ga_set_affinity(void * entry,u16 devid,u16 index,u8 vector,u32 dest_apicid)2972 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
2973 u8 vector, u32 dest_apicid)
2974 {
2975 struct irte_ga *irte = (struct irte_ga *) entry;
2976
2977 if (!irte->lo.fields_remap.guest_mode) {
2978 irte->hi.fields.vector = vector;
2979 irte->lo.fields_remap.destination =
2980 APICID_TO_IRTE_DEST_LO(dest_apicid);
2981 irte->hi.fields.destination =
2982 APICID_TO_IRTE_DEST_HI(dest_apicid);
2983 modify_irte_ga(devid, index, irte, NULL);
2984 }
2985 }
2986
2987 #define IRTE_ALLOCATED (~1U)
irte_set_allocated(struct irq_remap_table * table,int index)2988 static void irte_set_allocated(struct irq_remap_table *table, int index)
2989 {
2990 table->table[index] = IRTE_ALLOCATED;
2991 }
2992
irte_ga_set_allocated(struct irq_remap_table * table,int index)2993 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
2994 {
2995 struct irte_ga *ptr = (struct irte_ga *)table->table;
2996 struct irte_ga *irte = &ptr[index];
2997
2998 memset(&irte->lo.val, 0, sizeof(u64));
2999 memset(&irte->hi.val, 0, sizeof(u64));
3000 irte->hi.fields.vector = 0xff;
3001 }
3002
irte_is_allocated(struct irq_remap_table * table,int index)3003 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3004 {
3005 union irte *ptr = (union irte *)table->table;
3006 union irte *irte = &ptr[index];
3007
3008 return irte->val != 0;
3009 }
3010
irte_ga_is_allocated(struct irq_remap_table * table,int index)3011 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3012 {
3013 struct irte_ga *ptr = (struct irte_ga *)table->table;
3014 struct irte_ga *irte = &ptr[index];
3015
3016 return irte->hi.fields.vector != 0;
3017 }
3018
irte_clear_allocated(struct irq_remap_table * table,int index)3019 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3020 {
3021 table->table[index] = 0;
3022 }
3023
irte_ga_clear_allocated(struct irq_remap_table * table,int index)3024 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3025 {
3026 struct irte_ga *ptr = (struct irte_ga *)table->table;
3027 struct irte_ga *irte = &ptr[index];
3028
3029 memset(&irte->lo.val, 0, sizeof(u64));
3030 memset(&irte->hi.val, 0, sizeof(u64));
3031 }
3032
get_devid(struct irq_alloc_info * info)3033 static int get_devid(struct irq_alloc_info *info)
3034 {
3035 switch (info->type) {
3036 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3037 return get_ioapic_devid(info->devid);
3038 case X86_IRQ_ALLOC_TYPE_HPET:
3039 return get_hpet_devid(info->devid);
3040 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
3041 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
3042 return get_device_id(msi_desc_to_dev(info->desc));
3043 default:
3044 WARN_ON_ONCE(1);
3045 return -1;
3046 }
3047 }
3048
3049 struct irq_remap_ops amd_iommu_irq_ops = {
3050 .prepare = amd_iommu_prepare,
3051 .enable = amd_iommu_enable,
3052 .disable = amd_iommu_disable,
3053 .reenable = amd_iommu_reenable,
3054 .enable_faulting = amd_iommu_enable_faulting,
3055 };
3056
fill_msi_msg(struct msi_msg * msg,u32 index)3057 static void fill_msi_msg(struct msi_msg *msg, u32 index)
3058 {
3059 msg->data = index;
3060 msg->address_lo = 0;
3061 msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW;
3062 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
3063 }
3064
irq_remapping_prepare_irte(struct amd_ir_data * data,struct irq_cfg * irq_cfg,struct irq_alloc_info * info,int devid,int index,int sub_handle)3065 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3066 struct irq_cfg *irq_cfg,
3067 struct irq_alloc_info *info,
3068 int devid, int index, int sub_handle)
3069 {
3070 struct irq_2_irte *irte_info = &data->irq_2_irte;
3071 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3072
3073 if (!iommu)
3074 return;
3075
3076 data->irq_2_irte.devid = devid;
3077 data->irq_2_irte.index = index + sub_handle;
3078 iommu->irte_ops->prepare(data->entry, apic->delivery_mode,
3079 apic->dest_mode_logical, irq_cfg->vector,
3080 irq_cfg->dest_apicid, devid);
3081
3082 switch (info->type) {
3083 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3084 case X86_IRQ_ALLOC_TYPE_HPET:
3085 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
3086 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
3087 fill_msi_msg(&data->msi_entry, irte_info->index);
3088 break;
3089
3090 default:
3091 BUG_ON(1);
3092 break;
3093 }
3094 }
3095
3096 struct amd_irte_ops irte_32_ops = {
3097 .prepare = irte_prepare,
3098 .activate = irte_activate,
3099 .deactivate = irte_deactivate,
3100 .set_affinity = irte_set_affinity,
3101 .set_allocated = irte_set_allocated,
3102 .is_allocated = irte_is_allocated,
3103 .clear_allocated = irte_clear_allocated,
3104 };
3105
3106 struct amd_irte_ops irte_128_ops = {
3107 .prepare = irte_ga_prepare,
3108 .activate = irte_ga_activate,
3109 .deactivate = irte_ga_deactivate,
3110 .set_affinity = irte_ga_set_affinity,
3111 .set_allocated = irte_ga_set_allocated,
3112 .is_allocated = irte_ga_is_allocated,
3113 .clear_allocated = irte_ga_clear_allocated,
3114 };
3115
irq_remapping_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)3116 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
3117 unsigned int nr_irqs, void *arg)
3118 {
3119 struct irq_alloc_info *info = arg;
3120 struct irq_data *irq_data;
3121 struct amd_ir_data *data = NULL;
3122 struct irq_cfg *cfg;
3123 int i, ret, devid;
3124 int index;
3125
3126 if (!info)
3127 return -EINVAL;
3128 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI &&
3129 info->type != X86_IRQ_ALLOC_TYPE_PCI_MSIX)
3130 return -EINVAL;
3131
3132 /*
3133 * With IRQ remapping enabled, don't need contiguous CPU vectors
3134 * to support multiple MSI interrupts.
3135 */
3136 if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI)
3137 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
3138
3139 devid = get_devid(info);
3140 if (devid < 0)
3141 return -EINVAL;
3142
3143 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
3144 if (ret < 0)
3145 return ret;
3146
3147 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
3148 struct irq_remap_table *table;
3149 struct amd_iommu *iommu;
3150
3151 table = alloc_irq_table(devid, NULL);
3152 if (table) {
3153 if (!table->min_index) {
3154 /*
3155 * Keep the first 32 indexes free for IOAPIC
3156 * interrupts.
3157 */
3158 table->min_index = 32;
3159 iommu = amd_iommu_rlookup_table[devid];
3160 for (i = 0; i < 32; ++i)
3161 iommu->irte_ops->set_allocated(table, i);
3162 }
3163 WARN_ON(table->min_index != 32);
3164 index = info->ioapic.pin;
3165 } else {
3166 index = -ENOMEM;
3167 }
3168 } else if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI ||
3169 info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX) {
3170 bool align = (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI);
3171
3172 index = alloc_irq_index(devid, nr_irqs, align,
3173 msi_desc_to_pci_dev(info->desc));
3174 } else {
3175 index = alloc_irq_index(devid, nr_irqs, false, NULL);
3176 }
3177
3178 if (index < 0) {
3179 pr_warn("Failed to allocate IRTE\n");
3180 ret = index;
3181 goto out_free_parent;
3182 }
3183
3184 for (i = 0; i < nr_irqs; i++) {
3185 irq_data = irq_domain_get_irq_data(domain, virq + i);
3186 cfg = irq_data ? irqd_cfg(irq_data) : NULL;
3187 if (!cfg) {
3188 ret = -EINVAL;
3189 goto out_free_data;
3190 }
3191
3192 ret = -ENOMEM;
3193 data = kzalloc(sizeof(*data), GFP_KERNEL);
3194 if (!data)
3195 goto out_free_data;
3196
3197 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3198 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
3199 else
3200 data->entry = kzalloc(sizeof(struct irte_ga),
3201 GFP_KERNEL);
3202 if (!data->entry) {
3203 kfree(data);
3204 goto out_free_data;
3205 }
3206
3207 irq_data->hwirq = (devid << 16) + i;
3208 irq_data->chip_data = data;
3209 irq_data->chip = &amd_ir_chip;
3210 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
3211 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
3212 }
3213
3214 return 0;
3215
3216 out_free_data:
3217 for (i--; i >= 0; i--) {
3218 irq_data = irq_domain_get_irq_data(domain, virq + i);
3219 if (irq_data)
3220 kfree(irq_data->chip_data);
3221 }
3222 for (i = 0; i < nr_irqs; i++)
3223 free_irte(devid, index + i);
3224 out_free_parent:
3225 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3226 return ret;
3227 }
3228
irq_remapping_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)3229 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
3230 unsigned int nr_irqs)
3231 {
3232 struct irq_2_irte *irte_info;
3233 struct irq_data *irq_data;
3234 struct amd_ir_data *data;
3235 int i;
3236
3237 for (i = 0; i < nr_irqs; i++) {
3238 irq_data = irq_domain_get_irq_data(domain, virq + i);
3239 if (irq_data && irq_data->chip_data) {
3240 data = irq_data->chip_data;
3241 irte_info = &data->irq_2_irte;
3242 free_irte(irte_info->devid, irte_info->index);
3243 kfree(data->entry);
3244 kfree(data);
3245 }
3246 }
3247 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3248 }
3249
3250 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3251 struct amd_ir_data *ir_data,
3252 struct irq_2_irte *irte_info,
3253 struct irq_cfg *cfg);
3254
irq_remapping_activate(struct irq_domain * domain,struct irq_data * irq_data,bool reserve)3255 static int irq_remapping_activate(struct irq_domain *domain,
3256 struct irq_data *irq_data, bool reserve)
3257 {
3258 struct amd_ir_data *data = irq_data->chip_data;
3259 struct irq_2_irte *irte_info = &data->irq_2_irte;
3260 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3261 struct irq_cfg *cfg = irqd_cfg(irq_data);
3262
3263 if (!iommu)
3264 return 0;
3265
3266 iommu->irte_ops->activate(data->entry, irte_info->devid,
3267 irte_info->index);
3268 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
3269 return 0;
3270 }
3271
irq_remapping_deactivate(struct irq_domain * domain,struct irq_data * irq_data)3272 static void irq_remapping_deactivate(struct irq_domain *domain,
3273 struct irq_data *irq_data)
3274 {
3275 struct amd_ir_data *data = irq_data->chip_data;
3276 struct irq_2_irte *irte_info = &data->irq_2_irte;
3277 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3278
3279 if (iommu)
3280 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
3281 irte_info->index);
3282 }
3283
irq_remapping_select(struct irq_domain * d,struct irq_fwspec * fwspec,enum irq_domain_bus_token bus_token)3284 static int irq_remapping_select(struct irq_domain *d, struct irq_fwspec *fwspec,
3285 enum irq_domain_bus_token bus_token)
3286 {
3287 struct amd_iommu *iommu;
3288 int devid = -1;
3289
3290 if (!amd_iommu_irq_remap)
3291 return 0;
3292
3293 if (x86_fwspec_is_ioapic(fwspec))
3294 devid = get_ioapic_devid(fwspec->param[0]);
3295 else if (x86_fwspec_is_hpet(fwspec))
3296 devid = get_hpet_devid(fwspec->param[0]);
3297
3298 if (devid < 0)
3299 return 0;
3300
3301 iommu = amd_iommu_rlookup_table[devid];
3302 return iommu && iommu->ir_domain == d;
3303 }
3304
3305 static const struct irq_domain_ops amd_ir_domain_ops = {
3306 .select = irq_remapping_select,
3307 .alloc = irq_remapping_alloc,
3308 .free = irq_remapping_free,
3309 .activate = irq_remapping_activate,
3310 .deactivate = irq_remapping_deactivate,
3311 };
3312
amd_iommu_activate_guest_mode(void * data)3313 int amd_iommu_activate_guest_mode(void *data)
3314 {
3315 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3316 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3317 u64 valid;
3318
3319 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || !entry)
3320 return 0;
3321
3322 valid = entry->lo.fields_vapic.valid;
3323
3324 entry->lo.val = 0;
3325 entry->hi.val = 0;
3326
3327 entry->lo.fields_vapic.valid = valid;
3328 entry->lo.fields_vapic.guest_mode = 1;
3329 entry->lo.fields_vapic.ga_log_intr = 1;
3330 entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr;
3331 entry->hi.fields.vector = ir_data->ga_vector;
3332 entry->lo.fields_vapic.ga_tag = ir_data->ga_tag;
3333
3334 return modify_irte_ga(ir_data->irq_2_irte.devid,
3335 ir_data->irq_2_irte.index, entry, ir_data);
3336 }
3337 EXPORT_SYMBOL(amd_iommu_activate_guest_mode);
3338
amd_iommu_deactivate_guest_mode(void * data)3339 int amd_iommu_deactivate_guest_mode(void *data)
3340 {
3341 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3342 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3343 struct irq_cfg *cfg = ir_data->cfg;
3344 u64 valid;
3345
3346 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3347 !entry || !entry->lo.fields_vapic.guest_mode)
3348 return 0;
3349
3350 valid = entry->lo.fields_remap.valid;
3351
3352 entry->lo.val = 0;
3353 entry->hi.val = 0;
3354
3355 entry->lo.fields_remap.valid = valid;
3356 entry->lo.fields_remap.dm = apic->dest_mode_logical;
3357 entry->lo.fields_remap.int_type = apic->delivery_mode;
3358 entry->hi.fields.vector = cfg->vector;
3359 entry->lo.fields_remap.destination =
3360 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
3361 entry->hi.fields.destination =
3362 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
3363
3364 return modify_irte_ga(ir_data->irq_2_irte.devid,
3365 ir_data->irq_2_irte.index, entry, ir_data);
3366 }
3367 EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);
3368
amd_ir_set_vcpu_affinity(struct irq_data * data,void * vcpu_info)3369 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
3370 {
3371 int ret;
3372 struct amd_iommu *iommu;
3373 struct amd_iommu_pi_data *pi_data = vcpu_info;
3374 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
3375 struct amd_ir_data *ir_data = data->chip_data;
3376 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3377 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
3378
3379 /* Note:
3380 * This device has never been set up for guest mode.
3381 * we should not modify the IRTE
3382 */
3383 if (!dev_data || !dev_data->use_vapic)
3384 return 0;
3385
3386 ir_data->cfg = irqd_cfg(data);
3387 pi_data->ir_data = ir_data;
3388
3389 /* Note:
3390 * SVM tries to set up for VAPIC mode, but we are in
3391 * legacy mode. So, we force legacy mode instead.
3392 */
3393 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3394 pr_debug("%s: Fall back to using intr legacy remap\n",
3395 __func__);
3396 pi_data->is_guest_mode = false;
3397 }
3398
3399 iommu = amd_iommu_rlookup_table[irte_info->devid];
3400 if (iommu == NULL)
3401 return -EINVAL;
3402
3403 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
3404 if (pi_data->is_guest_mode) {
3405 ir_data->ga_root_ptr = (pi_data->base >> 12);
3406 ir_data->ga_vector = vcpu_pi_info->vector;
3407 ir_data->ga_tag = pi_data->ga_tag;
3408 ret = amd_iommu_activate_guest_mode(ir_data);
3409 if (!ret)
3410 ir_data->cached_ga_tag = pi_data->ga_tag;
3411 } else {
3412 ret = amd_iommu_deactivate_guest_mode(ir_data);
3413
3414 /*
3415 * This communicates the ga_tag back to the caller
3416 * so that it can do all the necessary clean up.
3417 */
3418 if (!ret)
3419 ir_data->cached_ga_tag = 0;
3420 }
3421
3422 return ret;
3423 }
3424
3425
amd_ir_update_irte(struct irq_data * irqd,struct amd_iommu * iommu,struct amd_ir_data * ir_data,struct irq_2_irte * irte_info,struct irq_cfg * cfg)3426 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3427 struct amd_ir_data *ir_data,
3428 struct irq_2_irte *irte_info,
3429 struct irq_cfg *cfg)
3430 {
3431
3432 /*
3433 * Atomically updates the IRTE with the new destination, vector
3434 * and flushes the interrupt entry cache.
3435 */
3436 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
3437 irte_info->index, cfg->vector,
3438 cfg->dest_apicid);
3439 }
3440
amd_ir_set_affinity(struct irq_data * data,const struct cpumask * mask,bool force)3441 static int amd_ir_set_affinity(struct irq_data *data,
3442 const struct cpumask *mask, bool force)
3443 {
3444 struct amd_ir_data *ir_data = data->chip_data;
3445 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3446 struct irq_cfg *cfg = irqd_cfg(data);
3447 struct irq_data *parent = data->parent_data;
3448 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3449 int ret;
3450
3451 if (!iommu)
3452 return -ENODEV;
3453
3454 ret = parent->chip->irq_set_affinity(parent, mask, force);
3455 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
3456 return ret;
3457
3458 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
3459 /*
3460 * After this point, all the interrupts will start arriving
3461 * at the new destination. So, time to cleanup the previous
3462 * vector allocation.
3463 */
3464 send_cleanup_vector(cfg);
3465
3466 return IRQ_SET_MASK_OK_DONE;
3467 }
3468
ir_compose_msi_msg(struct irq_data * irq_data,struct msi_msg * msg)3469 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
3470 {
3471 struct amd_ir_data *ir_data = irq_data->chip_data;
3472
3473 *msg = ir_data->msi_entry;
3474 }
3475
3476 static struct irq_chip amd_ir_chip = {
3477 .name = "AMD-IR",
3478 .irq_ack = apic_ack_irq,
3479 .irq_set_affinity = amd_ir_set_affinity,
3480 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
3481 .irq_compose_msi_msg = ir_compose_msi_msg,
3482 };
3483
amd_iommu_create_irq_domain(struct amd_iommu * iommu)3484 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
3485 {
3486 struct fwnode_handle *fn;
3487
3488 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
3489 if (!fn)
3490 return -ENOMEM;
3491 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
3492 if (!iommu->ir_domain) {
3493 irq_domain_free_fwnode(fn);
3494 return -ENOMEM;
3495 }
3496
3497 iommu->ir_domain->parent = arch_get_ir_parent_domain();
3498 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
3499 "AMD-IR-MSI",
3500 iommu->index);
3501 return 0;
3502 }
3503
amd_iommu_update_ga(int cpu,bool is_run,void * data)3504 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
3505 {
3506 unsigned long flags;
3507 struct amd_iommu *iommu;
3508 struct irq_remap_table *table;
3509 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3510 int devid = ir_data->irq_2_irte.devid;
3511 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3512 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
3513
3514 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3515 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
3516 return 0;
3517
3518 iommu = amd_iommu_rlookup_table[devid];
3519 if (!iommu)
3520 return -ENODEV;
3521
3522 table = get_irq_table(devid);
3523 if (!table)
3524 return -ENODEV;
3525
3526 raw_spin_lock_irqsave(&table->lock, flags);
3527
3528 if (ref->lo.fields_vapic.guest_mode) {
3529 if (cpu >= 0) {
3530 ref->lo.fields_vapic.destination =
3531 APICID_TO_IRTE_DEST_LO(cpu);
3532 ref->hi.fields.destination =
3533 APICID_TO_IRTE_DEST_HI(cpu);
3534 }
3535 ref->lo.fields_vapic.is_run = is_run;
3536 barrier();
3537 }
3538
3539 raw_spin_unlock_irqrestore(&table->lock, flags);
3540
3541 iommu_flush_irt(iommu, devid);
3542 iommu_completion_wait(iommu);
3543 return 0;
3544 }
3545 EXPORT_SYMBOL(amd_iommu_update_ga);
3546 #endif
3547