• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /*
2  * Copyright 2009 Jerome Glisse.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Jerome Glisse <glisse@freedesktop.org>
29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30  *    Dave Airlie
31  */
32 #include <linux/list.h>
33 #include <linux/slab.h>
34 #include <linux/dma-buf.h>
35 
36 #include <drm/amdgpu_drm.h>
37 #include <drm/drm_cache.h>
38 #include "amdgpu.h"
39 #include "amdgpu_trace.h"
40 #include "amdgpu_amdkfd.h"
41 
42 /**
43  * DOC: amdgpu_object
44  *
45  * This defines the interfaces to operate on an &amdgpu_bo buffer object which
46  * represents memory used by driver (VRAM, system memory, etc.). The driver
47  * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces
48  * to create/destroy/set buffer object which are then managed by the kernel TTM
49  * memory manager.
50  * The interfaces are also used internally by kernel clients, including gfx,
51  * uvd, etc. for kernel managed allocations used by the GPU.
52  *
53  */
54 
amdgpu_bo_destroy(struct ttm_buffer_object * tbo)55 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
56 {
57 	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
58 
59 	amdgpu_bo_kunmap(bo);
60 
61 	if (bo->tbo.base.import_attach)
62 		drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
63 	drm_gem_object_release(&bo->tbo.base);
64 	amdgpu_bo_unref(&bo->parent);
65 	kvfree(bo);
66 }
67 
amdgpu_bo_user_destroy(struct ttm_buffer_object * tbo)68 static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo)
69 {
70 	struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
71 	struct amdgpu_bo_user *ubo;
72 
73 	ubo = to_amdgpu_bo_user(bo);
74 	kfree(ubo->metadata);
75 	amdgpu_bo_destroy(tbo);
76 }
77 
amdgpu_bo_vm_destroy(struct ttm_buffer_object * tbo)78 static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo)
79 {
80 	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
81 	struct amdgpu_bo *shadow_bo = ttm_to_amdgpu_bo(tbo), *bo;
82 	struct amdgpu_bo_vm *vmbo;
83 
84 	bo = shadow_bo->parent;
85 	vmbo = to_amdgpu_bo_vm(bo);
86 	/* in case amdgpu_device_recover_vram got NULL of bo->parent */
87 	if (!list_empty(&vmbo->shadow_list)) {
88 		mutex_lock(&adev->shadow_list_lock);
89 		list_del_init(&vmbo->shadow_list);
90 		mutex_unlock(&adev->shadow_list_lock);
91 	}
92 
93 	amdgpu_bo_destroy(tbo);
94 }
95 
96 /**
97  * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo
98  * @bo: buffer object to be checked
99  *
100  * Uses destroy function associated with the object to determine if this is
101  * an &amdgpu_bo.
102  *
103  * Returns:
104  * true if the object belongs to &amdgpu_bo, false if not.
105  */
amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object * bo)106 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
107 {
108 	if (bo->destroy == &amdgpu_bo_destroy ||
109 	    bo->destroy == &amdgpu_bo_user_destroy ||
110 	    bo->destroy == &amdgpu_bo_vm_destroy)
111 		return true;
112 
113 	return false;
114 }
115 
116 /**
117  * amdgpu_bo_placement_from_domain - set buffer's placement
118  * @abo: &amdgpu_bo buffer object whose placement is to be set
119  * @domain: requested domain
120  *
121  * Sets buffer's placement according to requested domain and the buffer's
122  * flags.
123  */
amdgpu_bo_placement_from_domain(struct amdgpu_bo * abo,u32 domain)124 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
125 {
126 	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
127 	struct ttm_placement *placement = &abo->placement;
128 	struct ttm_place *places = abo->placements;
129 	u64 flags = abo->flags;
130 	u32 c = 0;
131 
132 	if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
133 		unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
134 
135 		places[c].fpfn = 0;
136 		places[c].lpfn = 0;
137 		places[c].mem_type = TTM_PL_VRAM;
138 		places[c].flags = 0;
139 
140 		if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
141 			places[c].lpfn = visible_pfn;
142 		else
143 			places[c].flags |= TTM_PL_FLAG_TOPDOWN;
144 
145 		if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
146 			places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
147 		c++;
148 	}
149 
150 	if (domain & AMDGPU_GEM_DOMAIN_GTT) {
151 		places[c].fpfn = 0;
152 		places[c].lpfn = 0;
153 		places[c].mem_type =
154 			abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ?
155 			AMDGPU_PL_PREEMPT : TTM_PL_TT;
156 		places[c].flags = 0;
157 		c++;
158 	}
159 
160 	if (domain & AMDGPU_GEM_DOMAIN_CPU) {
161 		places[c].fpfn = 0;
162 		places[c].lpfn = 0;
163 		places[c].mem_type = TTM_PL_SYSTEM;
164 		places[c].flags = 0;
165 		c++;
166 	}
167 
168 	if (domain & AMDGPU_GEM_DOMAIN_GDS) {
169 		places[c].fpfn = 0;
170 		places[c].lpfn = 0;
171 		places[c].mem_type = AMDGPU_PL_GDS;
172 		places[c].flags = 0;
173 		c++;
174 	}
175 
176 	if (domain & AMDGPU_GEM_DOMAIN_GWS) {
177 		places[c].fpfn = 0;
178 		places[c].lpfn = 0;
179 		places[c].mem_type = AMDGPU_PL_GWS;
180 		places[c].flags = 0;
181 		c++;
182 	}
183 
184 	if (domain & AMDGPU_GEM_DOMAIN_OA) {
185 		places[c].fpfn = 0;
186 		places[c].lpfn = 0;
187 		places[c].mem_type = AMDGPU_PL_OA;
188 		places[c].flags = 0;
189 		c++;
190 	}
191 
192 	if (!c) {
193 		places[c].fpfn = 0;
194 		places[c].lpfn = 0;
195 		places[c].mem_type = TTM_PL_SYSTEM;
196 		places[c].flags = 0;
197 		c++;
198 	}
199 
200 	BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS);
201 
202 	placement->num_placement = c;
203 	placement->placement = places;
204 
205 	placement->num_busy_placement = c;
206 	placement->busy_placement = places;
207 }
208 
209 /**
210  * amdgpu_bo_create_reserved - create reserved BO for kernel use
211  *
212  * @adev: amdgpu device object
213  * @size: size for the new BO
214  * @align: alignment for the new BO
215  * @domain: where to place it
216  * @bo_ptr: used to initialize BOs in structures
217  * @gpu_addr: GPU addr of the pinned BO
218  * @cpu_addr: optional CPU address mapping
219  *
220  * Allocates and pins a BO for kernel internal use, and returns it still
221  * reserved.
222  *
223  * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
224  *
225  * Returns:
226  * 0 on success, negative error code otherwise.
227  */
amdgpu_bo_create_reserved(struct amdgpu_device * adev,unsigned long size,int align,u32 domain,struct amdgpu_bo ** bo_ptr,u64 * gpu_addr,void ** cpu_addr)228 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
229 			      unsigned long size, int align,
230 			      u32 domain, struct amdgpu_bo **bo_ptr,
231 			      u64 *gpu_addr, void **cpu_addr)
232 {
233 	struct amdgpu_bo_param bp;
234 	bool free = false;
235 	int r;
236 
237 	if (!size) {
238 		amdgpu_bo_unref(bo_ptr);
239 		return 0;
240 	}
241 
242 	memset(&bp, 0, sizeof(bp));
243 	bp.size = size;
244 	bp.byte_align = align;
245 	bp.domain = domain;
246 	bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
247 		: AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
248 	bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
249 	bp.type = ttm_bo_type_kernel;
250 	bp.resv = NULL;
251 	bp.bo_ptr_size = sizeof(struct amdgpu_bo);
252 
253 	if (!*bo_ptr) {
254 		r = amdgpu_bo_create(adev, &bp, bo_ptr);
255 		if (r) {
256 			dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
257 				r);
258 			return r;
259 		}
260 		free = true;
261 	}
262 
263 	r = amdgpu_bo_reserve(*bo_ptr, false);
264 	if (r) {
265 		dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
266 		goto error_free;
267 	}
268 
269 	r = amdgpu_bo_pin(*bo_ptr, domain);
270 	if (r) {
271 		dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
272 		goto error_unreserve;
273 	}
274 
275 	r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo);
276 	if (r) {
277 		dev_err(adev->dev, "%p bind failed\n", *bo_ptr);
278 		goto error_unpin;
279 	}
280 
281 	if (gpu_addr)
282 		*gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr);
283 
284 	if (cpu_addr) {
285 		r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
286 		if (r) {
287 			dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
288 			goto error_unpin;
289 		}
290 	}
291 
292 	return 0;
293 
294 error_unpin:
295 	amdgpu_bo_unpin(*bo_ptr);
296 error_unreserve:
297 	amdgpu_bo_unreserve(*bo_ptr);
298 
299 error_free:
300 	if (free)
301 		amdgpu_bo_unref(bo_ptr);
302 
303 	return r;
304 }
305 
306 /**
307  * amdgpu_bo_create_kernel - create BO for kernel use
308  *
309  * @adev: amdgpu device object
310  * @size: size for the new BO
311  * @align: alignment for the new BO
312  * @domain: where to place it
313  * @bo_ptr:  used to initialize BOs in structures
314  * @gpu_addr: GPU addr of the pinned BO
315  * @cpu_addr: optional CPU address mapping
316  *
317  * Allocates and pins a BO for kernel internal use.
318  *
319  * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
320  *
321  * Returns:
322  * 0 on success, negative error code otherwise.
323  */
amdgpu_bo_create_kernel(struct amdgpu_device * adev,unsigned long size,int align,u32 domain,struct amdgpu_bo ** bo_ptr,u64 * gpu_addr,void ** cpu_addr)324 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
325 			    unsigned long size, int align,
326 			    u32 domain, struct amdgpu_bo **bo_ptr,
327 			    u64 *gpu_addr, void **cpu_addr)
328 {
329 	int r;
330 
331 	r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
332 				      gpu_addr, cpu_addr);
333 
334 	if (r)
335 		return r;
336 
337 	if (*bo_ptr)
338 		amdgpu_bo_unreserve(*bo_ptr);
339 
340 	return 0;
341 }
342 
343 /**
344  * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location
345  *
346  * @adev: amdgpu device object
347  * @offset: offset of the BO
348  * @size: size of the BO
349  * @domain: where to place it
350  * @bo_ptr:  used to initialize BOs in structures
351  * @cpu_addr: optional CPU address mapping
352  *
353  * Creates a kernel BO at a specific offset in the address space of the domain.
354  *
355  * Returns:
356  * 0 on success, negative error code otherwise.
357  */
amdgpu_bo_create_kernel_at(struct amdgpu_device * adev,uint64_t offset,uint64_t size,uint32_t domain,struct amdgpu_bo ** bo_ptr,void ** cpu_addr)358 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
359 			       uint64_t offset, uint64_t size, uint32_t domain,
360 			       struct amdgpu_bo **bo_ptr, void **cpu_addr)
361 {
362 	struct ttm_operation_ctx ctx = { false, false };
363 	unsigned int i;
364 	int r;
365 
366 	offset &= PAGE_MASK;
367 	size = ALIGN(size, PAGE_SIZE);
368 
369 	r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr,
370 				      NULL, cpu_addr);
371 	if (r)
372 		return r;
373 
374 	if ((*bo_ptr) == NULL)
375 		return 0;
376 
377 	/*
378 	 * Remove the original mem node and create a new one at the request
379 	 * position.
380 	 */
381 	if (cpu_addr)
382 		amdgpu_bo_kunmap(*bo_ptr);
383 
384 	ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource);
385 
386 	for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
387 		(*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT;
388 		(*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
389 	}
390 	r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
391 			     &(*bo_ptr)->tbo.resource, &ctx);
392 	if (r)
393 		goto error;
394 
395 	if (cpu_addr) {
396 		r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
397 		if (r)
398 			goto error;
399 	}
400 
401 	amdgpu_bo_unreserve(*bo_ptr);
402 	return 0;
403 
404 error:
405 	amdgpu_bo_unreserve(*bo_ptr);
406 	amdgpu_bo_unref(bo_ptr);
407 	return r;
408 }
409 
410 /**
411  * amdgpu_bo_free_kernel - free BO for kernel use
412  *
413  * @bo: amdgpu BO to free
414  * @gpu_addr: pointer to where the BO's GPU memory space address was stored
415  * @cpu_addr: pointer to where the BO's CPU memory space address was stored
416  *
417  * unmaps and unpin a BO for kernel internal use.
418  */
amdgpu_bo_free_kernel(struct amdgpu_bo ** bo,u64 * gpu_addr,void ** cpu_addr)419 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
420 			   void **cpu_addr)
421 {
422 	if (*bo == NULL)
423 		return;
424 
425 	if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
426 		if (cpu_addr)
427 			amdgpu_bo_kunmap(*bo);
428 
429 		amdgpu_bo_unpin(*bo);
430 		amdgpu_bo_unreserve(*bo);
431 	}
432 	amdgpu_bo_unref(bo);
433 
434 	if (gpu_addr)
435 		*gpu_addr = 0;
436 
437 	if (cpu_addr)
438 		*cpu_addr = NULL;
439 }
440 
441 /* Validate bo size is bit bigger then the request domain */
amdgpu_bo_validate_size(struct amdgpu_device * adev,unsigned long size,u32 domain)442 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
443 					  unsigned long size, u32 domain)
444 {
445 	struct ttm_resource_manager *man = NULL;
446 
447 	/*
448 	 * If GTT is part of requested domains the check must succeed to
449 	 * allow fall back to GTT
450 	 */
451 	if (domain & AMDGPU_GEM_DOMAIN_GTT) {
452 		man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
453 
454 		if (size < (man->size << PAGE_SHIFT))
455 			return true;
456 		else
457 			goto fail;
458 	}
459 
460 	if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
461 		man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
462 
463 		if (size < (man->size << PAGE_SHIFT))
464 			return true;
465 		else
466 			goto fail;
467 	}
468 
469 
470 	/* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
471 	return true;
472 
473 fail:
474 	DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
475 		  man->size << PAGE_SHIFT);
476 	return false;
477 }
478 
amdgpu_bo_support_uswc(u64 bo_flags)479 bool amdgpu_bo_support_uswc(u64 bo_flags)
480 {
481 
482 #ifdef CONFIG_X86_32
483 	/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
484 	 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
485 	 */
486 	return false;
487 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
488 	/* Don't try to enable write-combining when it can't work, or things
489 	 * may be slow
490 	 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
491 	 */
492 
493 #ifndef CONFIG_COMPILE_TEST
494 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
495 	 thanks to write-combining
496 #endif
497 
498 	if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
499 		DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
500 			      "better performance thanks to write-combining\n");
501 	return false;
502 #else
503 	/* For architectures that don't support WC memory,
504 	 * mask out the WC flag from the BO
505 	 */
506 	if (!drm_arch_can_wc_memory())
507 		return false;
508 
509 	return true;
510 #endif
511 }
512 
513 /**
514  * amdgpu_bo_create - create an &amdgpu_bo buffer object
515  * @adev: amdgpu device object
516  * @bp: parameters to be used for the buffer object
517  * @bo_ptr: pointer to the buffer object pointer
518  *
519  * Creates an &amdgpu_bo buffer object.
520  *
521  * Returns:
522  * 0 for success or a negative error code on failure.
523  */
amdgpu_bo_create(struct amdgpu_device * adev,struct amdgpu_bo_param * bp,struct amdgpu_bo ** bo_ptr)524 int amdgpu_bo_create(struct amdgpu_device *adev,
525 			       struct amdgpu_bo_param *bp,
526 			       struct amdgpu_bo **bo_ptr)
527 {
528 	struct ttm_operation_ctx ctx = {
529 		.interruptible = (bp->type != ttm_bo_type_kernel),
530 		.no_wait_gpu = bp->no_wait_gpu,
531 		/* We opt to avoid OOM on system pages allocations */
532 		.gfp_retry_mayfail = true,
533 		.allow_res_evict = bp->type != ttm_bo_type_kernel,
534 		.resv = bp->resv
535 	};
536 	struct amdgpu_bo *bo;
537 	unsigned long page_align, size = bp->size;
538 	int r;
539 
540 	/* Note that GDS/GWS/OA allocates 1 page per byte/resource. */
541 	if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
542 		/* GWS and OA don't need any alignment. */
543 		page_align = bp->byte_align;
544 		size <<= PAGE_SHIFT;
545 	} else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
546 		/* Both size and alignment must be a multiple of 4. */
547 		page_align = ALIGN(bp->byte_align, 4);
548 		size = ALIGN(size, 4) << PAGE_SHIFT;
549 	} else {
550 		/* Memory should be aligned at least to a page size. */
551 		page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
552 		size = ALIGN(size, PAGE_SIZE);
553 	}
554 
555 	if (!amdgpu_bo_validate_size(adev, size, bp->domain))
556 		return -ENOMEM;
557 
558 	BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo));
559 
560 	*bo_ptr = NULL;
561 	bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL);
562 	if (bo == NULL)
563 		return -ENOMEM;
564 	drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);
565 	bo->vm_bo = NULL;
566 	bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
567 		bp->domain;
568 	bo->allowed_domains = bo->preferred_domains;
569 	if (bp->type != ttm_bo_type_kernel &&
570 	    bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
571 		bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
572 
573 	bo->flags = bp->flags;
574 
575 	if (!amdgpu_bo_support_uswc(bo->flags))
576 		bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
577 
578 	bo->tbo.bdev = &adev->mman.bdev;
579 	if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
580 			  AMDGPU_GEM_DOMAIN_GDS))
581 		amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
582 	else
583 		amdgpu_bo_placement_from_domain(bo, bp->domain);
584 	if (bp->type == ttm_bo_type_kernel)
585 		bo->tbo.priority = 1;
586 
587 	if (!bp->destroy)
588 		bp->destroy = &amdgpu_bo_destroy;
589 
590 	r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type,
591 				 &bo->placement, page_align, &ctx,  NULL,
592 				 bp->resv, bp->destroy);
593 	if (unlikely(r != 0))
594 		return r;
595 
596 	if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
597 	    bo->tbo.resource->mem_type == TTM_PL_VRAM &&
598 	    bo->tbo.resource->start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
599 		amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
600 					     ctx.bytes_moved);
601 	else
602 		amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
603 
604 	if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
605 	    bo->tbo.resource->mem_type == TTM_PL_VRAM) {
606 		struct dma_fence *fence;
607 
608 		r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence);
609 		if (unlikely(r))
610 			goto fail_unreserve;
611 
612 		amdgpu_bo_fence(bo, fence, false);
613 		dma_fence_put(bo->tbo.moving);
614 		bo->tbo.moving = dma_fence_get(fence);
615 		dma_fence_put(fence);
616 	}
617 	if (!bp->resv)
618 		amdgpu_bo_unreserve(bo);
619 	*bo_ptr = bo;
620 
621 	trace_amdgpu_bo_create(bo);
622 
623 	/* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
624 	if (bp->type == ttm_bo_type_device)
625 		bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
626 
627 	return 0;
628 
629 fail_unreserve:
630 	if (!bp->resv)
631 		dma_resv_unlock(bo->tbo.base.resv);
632 	amdgpu_bo_unref(&bo);
633 	return r;
634 }
635 
636 /**
637  * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object
638  * @adev: amdgpu device object
639  * @bp: parameters to be used for the buffer object
640  * @ubo_ptr: pointer to the buffer object pointer
641  *
642  * Create a BO to be used by user application;
643  *
644  * Returns:
645  * 0 for success or a negative error code on failure.
646  */
647 
amdgpu_bo_create_user(struct amdgpu_device * adev,struct amdgpu_bo_param * bp,struct amdgpu_bo_user ** ubo_ptr)648 int amdgpu_bo_create_user(struct amdgpu_device *adev,
649 			  struct amdgpu_bo_param *bp,
650 			  struct amdgpu_bo_user **ubo_ptr)
651 {
652 	struct amdgpu_bo *bo_ptr;
653 	int r;
654 
655 	bp->bo_ptr_size = sizeof(struct amdgpu_bo_user);
656 	bp->destroy = &amdgpu_bo_user_destroy;
657 	r = amdgpu_bo_create(adev, bp, &bo_ptr);
658 	if (r)
659 		return r;
660 
661 	*ubo_ptr = to_amdgpu_bo_user(bo_ptr);
662 	return r;
663 }
664 
665 /**
666  * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object
667  * @adev: amdgpu device object
668  * @bp: parameters to be used for the buffer object
669  * @vmbo_ptr: pointer to the buffer object pointer
670  *
671  * Create a BO to be for GPUVM.
672  *
673  * Returns:
674  * 0 for success or a negative error code on failure.
675  */
676 
amdgpu_bo_create_vm(struct amdgpu_device * adev,struct amdgpu_bo_param * bp,struct amdgpu_bo_vm ** vmbo_ptr)677 int amdgpu_bo_create_vm(struct amdgpu_device *adev,
678 			struct amdgpu_bo_param *bp,
679 			struct amdgpu_bo_vm **vmbo_ptr)
680 {
681 	struct amdgpu_bo *bo_ptr;
682 	int r;
683 
684 	/* bo_ptr_size will be determined by the caller and it depends on
685 	 * num of amdgpu_vm_pt entries.
686 	 */
687 	BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm));
688 	r = amdgpu_bo_create(adev, bp, &bo_ptr);
689 	if (r)
690 		return r;
691 
692 	*vmbo_ptr = to_amdgpu_bo_vm(bo_ptr);
693 	return r;
694 }
695 
696 /**
697  * amdgpu_bo_validate - validate an &amdgpu_bo buffer object
698  * @bo: pointer to the buffer object
699  *
700  * Sets placement according to domain; and changes placement and caching
701  * policy of the buffer object according to the placement.
702  * This is used for validating shadow bos.  It calls ttm_bo_validate() to
703  * make sure the buffer is resident where it needs to be.
704  *
705  * Returns:
706  * 0 for success or a negative error code on failure.
707  */
amdgpu_bo_validate(struct amdgpu_bo * bo)708 int amdgpu_bo_validate(struct amdgpu_bo *bo)
709 {
710 	struct ttm_operation_ctx ctx = { false, false };
711 	uint32_t domain;
712 	int r;
713 
714 	if (bo->tbo.pin_count)
715 		return 0;
716 
717 	domain = bo->preferred_domains;
718 
719 retry:
720 	amdgpu_bo_placement_from_domain(bo, domain);
721 	r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
722 	if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
723 		domain = bo->allowed_domains;
724 		goto retry;
725 	}
726 
727 	return r;
728 }
729 
730 /**
731  * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list
732  *
733  * @vmbo: BO that will be inserted into the shadow list
734  *
735  * Insert a BO to the shadow list.
736  */
amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm * vmbo)737 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo)
738 {
739 	struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev);
740 
741 	mutex_lock(&adev->shadow_list_lock);
742 	list_add_tail(&vmbo->shadow_list, &adev->shadow_list);
743 	vmbo->shadow->parent = amdgpu_bo_ref(&vmbo->bo);
744 	vmbo->shadow->tbo.destroy = &amdgpu_bo_vm_destroy;
745 	mutex_unlock(&adev->shadow_list_lock);
746 }
747 
748 /**
749  * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow
750  *
751  * @shadow: &amdgpu_bo shadow to be restored
752  * @fence: dma_fence associated with the operation
753  *
754  * Copies a buffer object's shadow content back to the object.
755  * This is used for recovering a buffer from its shadow in case of a gpu
756  * reset where vram context may be lost.
757  *
758  * Returns:
759  * 0 for success or a negative error code on failure.
760  */
amdgpu_bo_restore_shadow(struct amdgpu_bo * shadow,struct dma_fence ** fence)761 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence)
762 
763 {
764 	struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev);
765 	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
766 	uint64_t shadow_addr, parent_addr;
767 
768 	shadow_addr = amdgpu_bo_gpu_offset(shadow);
769 	parent_addr = amdgpu_bo_gpu_offset(shadow->parent);
770 
771 	return amdgpu_copy_buffer(ring, shadow_addr, parent_addr,
772 				  amdgpu_bo_size(shadow), NULL, fence,
773 				  true, false, false);
774 }
775 
776 /**
777  * amdgpu_bo_kmap - map an &amdgpu_bo buffer object
778  * @bo: &amdgpu_bo buffer object to be mapped
779  * @ptr: kernel virtual address to be returned
780  *
781  * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls
782  * amdgpu_bo_kptr() to get the kernel virtual address.
783  *
784  * Returns:
785  * 0 for success or a negative error code on failure.
786  */
amdgpu_bo_kmap(struct amdgpu_bo * bo,void ** ptr)787 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
788 {
789 	void *kptr;
790 	long r;
791 
792 	if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
793 		return -EPERM;
794 
795 	kptr = amdgpu_bo_kptr(bo);
796 	if (kptr) {
797 		if (ptr)
798 			*ptr = kptr;
799 		return 0;
800 	}
801 
802 	r = dma_resv_wait_timeout(bo->tbo.base.resv, false, false,
803 				  MAX_SCHEDULE_TIMEOUT);
804 	if (r < 0)
805 		return r;
806 
807 	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.resource->num_pages, &bo->kmap);
808 	if (r)
809 		return r;
810 
811 	if (ptr)
812 		*ptr = amdgpu_bo_kptr(bo);
813 
814 	return 0;
815 }
816 
817 /**
818  * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object
819  * @bo: &amdgpu_bo buffer object
820  *
821  * Calls ttm_kmap_obj_virtual() to get the kernel virtual address
822  *
823  * Returns:
824  * the virtual address of a buffer object area.
825  */
amdgpu_bo_kptr(struct amdgpu_bo * bo)826 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
827 {
828 	bool is_iomem;
829 
830 	return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
831 }
832 
833 /**
834  * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object
835  * @bo: &amdgpu_bo buffer object to be unmapped
836  *
837  * Unmaps a kernel map set up by amdgpu_bo_kmap().
838  */
amdgpu_bo_kunmap(struct amdgpu_bo * bo)839 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
840 {
841 	if (bo->kmap.bo)
842 		ttm_bo_kunmap(&bo->kmap);
843 }
844 
845 /**
846  * amdgpu_bo_ref - reference an &amdgpu_bo buffer object
847  * @bo: &amdgpu_bo buffer object
848  *
849  * References the contained &ttm_buffer_object.
850  *
851  * Returns:
852  * a refcounted pointer to the &amdgpu_bo buffer object.
853  */
amdgpu_bo_ref(struct amdgpu_bo * bo)854 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
855 {
856 	if (bo == NULL)
857 		return NULL;
858 
859 	ttm_bo_get(&bo->tbo);
860 	return bo;
861 }
862 
863 /**
864  * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object
865  * @bo: &amdgpu_bo buffer object
866  *
867  * Unreferences the contained &ttm_buffer_object and clear the pointer
868  */
amdgpu_bo_unref(struct amdgpu_bo ** bo)869 void amdgpu_bo_unref(struct amdgpu_bo **bo)
870 {
871 	struct ttm_buffer_object *tbo;
872 
873 	if ((*bo) == NULL)
874 		return;
875 
876 	tbo = &((*bo)->tbo);
877 	ttm_bo_put(tbo);
878 	*bo = NULL;
879 }
880 
881 /**
882  * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object
883  * @bo: &amdgpu_bo buffer object to be pinned
884  * @domain: domain to be pinned to
885  * @min_offset: the start of requested address range
886  * @max_offset: the end of requested address range
887  *
888  * Pins the buffer object according to requested domain and address range. If
889  * the memory is unbound gart memory, binds the pages into gart table. Adjusts
890  * pin_count and pin_size accordingly.
891  *
892  * Pinning means to lock pages in memory along with keeping them at a fixed
893  * offset. It is required when a buffer can not be moved, for example, when
894  * a display buffer is being scanned out.
895  *
896  * Compared with amdgpu_bo_pin(), this function gives more flexibility on
897  * where to pin a buffer if there are specific restrictions on where a buffer
898  * must be located.
899  *
900  * Returns:
901  * 0 for success or a negative error code on failure.
902  */
amdgpu_bo_pin_restricted(struct amdgpu_bo * bo,u32 domain,u64 min_offset,u64 max_offset)903 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
904 			     u64 min_offset, u64 max_offset)
905 {
906 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
907 	struct ttm_operation_ctx ctx = { false, false };
908 	int r, i;
909 
910 	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
911 		return -EPERM;
912 
913 	if (WARN_ON_ONCE(min_offset > max_offset))
914 		return -EINVAL;
915 
916 	/* Check domain to be pinned to against preferred domains */
917 	if (bo->preferred_domains & domain)
918 		domain = bo->preferred_domains & domain;
919 
920 	/* A shared bo cannot be migrated to VRAM */
921 	if (bo->tbo.base.import_attach) {
922 		if (domain & AMDGPU_GEM_DOMAIN_GTT)
923 			domain = AMDGPU_GEM_DOMAIN_GTT;
924 		else
925 			return -EINVAL;
926 	}
927 
928 	if (bo->tbo.pin_count) {
929 		uint32_t mem_type = bo->tbo.resource->mem_type;
930 		uint32_t mem_flags = bo->tbo.resource->placement;
931 
932 		if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
933 			return -EINVAL;
934 
935 		if ((mem_type == TTM_PL_VRAM) &&
936 		    (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) &&
937 		    !(mem_flags & TTM_PL_FLAG_CONTIGUOUS))
938 			return -EINVAL;
939 
940 		ttm_bo_pin(&bo->tbo);
941 
942 		if (max_offset != 0) {
943 			u64 domain_start = amdgpu_ttm_domain_start(adev,
944 								   mem_type);
945 			WARN_ON_ONCE(max_offset <
946 				     (amdgpu_bo_gpu_offset(bo) - domain_start));
947 		}
948 
949 		return 0;
950 	}
951 
952 	/* This assumes only APU display buffers are pinned with (VRAM|GTT).
953 	 * See function amdgpu_display_supported_domains()
954 	 */
955 	domain = amdgpu_bo_get_preferred_domain(adev, domain);
956 
957 	if (bo->tbo.base.import_attach)
958 		dma_buf_pin(bo->tbo.base.import_attach);
959 
960 	/* force to pin into visible video ram */
961 	if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
962 		bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
963 	amdgpu_bo_placement_from_domain(bo, domain);
964 	for (i = 0; i < bo->placement.num_placement; i++) {
965 		unsigned fpfn, lpfn;
966 
967 		fpfn = min_offset >> PAGE_SHIFT;
968 		lpfn = max_offset >> PAGE_SHIFT;
969 
970 		if (fpfn > bo->placements[i].fpfn)
971 			bo->placements[i].fpfn = fpfn;
972 		if (!bo->placements[i].lpfn ||
973 		    (lpfn && lpfn < bo->placements[i].lpfn))
974 			bo->placements[i].lpfn = lpfn;
975 	}
976 
977 	r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
978 	if (unlikely(r)) {
979 		dev_err(adev->dev, "%p pin failed\n", bo);
980 		goto error;
981 	}
982 
983 	ttm_bo_pin(&bo->tbo);
984 
985 	domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
986 	if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
987 		atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size);
988 		atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo),
989 			     &adev->visible_pin_size);
990 	} else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
991 		atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size);
992 	}
993 
994 error:
995 	return r;
996 }
997 
998 /**
999  * amdgpu_bo_pin - pin an &amdgpu_bo buffer object
1000  * @bo: &amdgpu_bo buffer object to be pinned
1001  * @domain: domain to be pinned to
1002  *
1003  * A simple wrapper to amdgpu_bo_pin_restricted().
1004  * Provides a simpler API for buffers that do not have any strict restrictions
1005  * on where a buffer must be located.
1006  *
1007  * Returns:
1008  * 0 for success or a negative error code on failure.
1009  */
amdgpu_bo_pin(struct amdgpu_bo * bo,u32 domain)1010 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)
1011 {
1012 	bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1013 	return amdgpu_bo_pin_restricted(bo, domain, 0, 0);
1014 }
1015 
1016 /**
1017  * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object
1018  * @bo: &amdgpu_bo buffer object to be unpinned
1019  *
1020  * Decreases the pin_count, and clears the flags if pin_count reaches 0.
1021  * Changes placement and pin size accordingly.
1022  *
1023  * Returns:
1024  * 0 for success or a negative error code on failure.
1025  */
amdgpu_bo_unpin(struct amdgpu_bo * bo)1026 void amdgpu_bo_unpin(struct amdgpu_bo *bo)
1027 {
1028 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1029 
1030 	ttm_bo_unpin(&bo->tbo);
1031 	if (bo->tbo.pin_count)
1032 		return;
1033 
1034 	if (bo->tbo.base.import_attach)
1035 		dma_buf_unpin(bo->tbo.base.import_attach);
1036 
1037 	if (bo->tbo.resource->mem_type == TTM_PL_VRAM) {
1038 		atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size);
1039 		atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo),
1040 			     &adev->visible_pin_size);
1041 	} else if (bo->tbo.resource->mem_type == TTM_PL_TT) {
1042 		atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);
1043 	}
1044 }
1045 
1046 static const char *amdgpu_vram_names[] = {
1047 	"UNKNOWN",
1048 	"GDDR1",
1049 	"DDR2",
1050 	"GDDR3",
1051 	"GDDR4",
1052 	"GDDR5",
1053 	"HBM",
1054 	"DDR3",
1055 	"DDR4",
1056 	"GDDR6",
1057 	"DDR5"
1058 };
1059 
1060 /**
1061  * amdgpu_bo_init - initialize memory manager
1062  * @adev: amdgpu device object
1063  *
1064  * Calls amdgpu_ttm_init() to initialize amdgpu memory manager.
1065  *
1066  * Returns:
1067  * 0 for success or a negative error code on failure.
1068  */
amdgpu_bo_init(struct amdgpu_device * adev)1069 int amdgpu_bo_init(struct amdgpu_device *adev)
1070 {
1071 	/* On A+A platform, VRAM can be mapped as WB */
1072 	if (!adev->gmc.xgmi.connected_to_cpu) {
1073 		/* reserve PAT memory space to WC for VRAM */
1074 		arch_io_reserve_memtype_wc(adev->gmc.aper_base,
1075 				adev->gmc.aper_size);
1076 
1077 		/* Add an MTRR for the VRAM */
1078 		adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
1079 				adev->gmc.aper_size);
1080 	}
1081 
1082 	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
1083 		 adev->gmc.mc_vram_size >> 20,
1084 		 (unsigned long long)adev->gmc.aper_size >> 20);
1085 	DRM_INFO("RAM width %dbits %s\n",
1086 		 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
1087 	return amdgpu_ttm_init(adev);
1088 }
1089 
1090 /**
1091  * amdgpu_bo_fini - tear down memory manager
1092  * @adev: amdgpu device object
1093  *
1094  * Reverses amdgpu_bo_init() to tear down memory manager.
1095  */
amdgpu_bo_fini(struct amdgpu_device * adev)1096 void amdgpu_bo_fini(struct amdgpu_device *adev)
1097 {
1098 	amdgpu_ttm_fini(adev);
1099 }
1100 
1101 /**
1102  * amdgpu_bo_set_tiling_flags - set tiling flags
1103  * @bo: &amdgpu_bo buffer object
1104  * @tiling_flags: new flags
1105  *
1106  * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or
1107  * kernel driver to set the tiling flags on a buffer.
1108  *
1109  * Returns:
1110  * 0 for success or a negative error code on failure.
1111  */
amdgpu_bo_set_tiling_flags(struct amdgpu_bo * bo,u64 tiling_flags)1112 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
1113 {
1114 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1115 	struct amdgpu_bo_user *ubo;
1116 
1117 	BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1118 	if (adev->family <= AMDGPU_FAMILY_CZ &&
1119 	    AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
1120 		return -EINVAL;
1121 
1122 	ubo = to_amdgpu_bo_user(bo);
1123 	ubo->tiling_flags = tiling_flags;
1124 	return 0;
1125 }
1126 
1127 /**
1128  * amdgpu_bo_get_tiling_flags - get tiling flags
1129  * @bo: &amdgpu_bo buffer object
1130  * @tiling_flags: returned flags
1131  *
1132  * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to
1133  * set the tiling flags on a buffer.
1134  */
amdgpu_bo_get_tiling_flags(struct amdgpu_bo * bo,u64 * tiling_flags)1135 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
1136 {
1137 	struct amdgpu_bo_user *ubo;
1138 
1139 	BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1140 	dma_resv_assert_held(bo->tbo.base.resv);
1141 	ubo = to_amdgpu_bo_user(bo);
1142 
1143 	if (tiling_flags)
1144 		*tiling_flags = ubo->tiling_flags;
1145 }
1146 
1147 /**
1148  * amdgpu_bo_set_metadata - set metadata
1149  * @bo: &amdgpu_bo buffer object
1150  * @metadata: new metadata
1151  * @metadata_size: size of the new metadata
1152  * @flags: flags of the new metadata
1153  *
1154  * Sets buffer object's metadata, its size and flags.
1155  * Used via GEM ioctl.
1156  *
1157  * Returns:
1158  * 0 for success or a negative error code on failure.
1159  */
amdgpu_bo_set_metadata(struct amdgpu_bo * bo,void * metadata,uint32_t metadata_size,uint64_t flags)1160 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
1161 			    uint32_t metadata_size, uint64_t flags)
1162 {
1163 	struct amdgpu_bo_user *ubo;
1164 	void *buffer;
1165 
1166 	BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1167 	ubo = to_amdgpu_bo_user(bo);
1168 	if (!metadata_size) {
1169 		if (ubo->metadata_size) {
1170 			kfree(ubo->metadata);
1171 			ubo->metadata = NULL;
1172 			ubo->metadata_size = 0;
1173 		}
1174 		return 0;
1175 	}
1176 
1177 	if (metadata == NULL)
1178 		return -EINVAL;
1179 
1180 	buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
1181 	if (buffer == NULL)
1182 		return -ENOMEM;
1183 
1184 	kfree(ubo->metadata);
1185 	ubo->metadata_flags = flags;
1186 	ubo->metadata = buffer;
1187 	ubo->metadata_size = metadata_size;
1188 
1189 	return 0;
1190 }
1191 
1192 /**
1193  * amdgpu_bo_get_metadata - get metadata
1194  * @bo: &amdgpu_bo buffer object
1195  * @buffer: returned metadata
1196  * @buffer_size: size of the buffer
1197  * @metadata_size: size of the returned metadata
1198  * @flags: flags of the returned metadata
1199  *
1200  * Gets buffer object's metadata, its size and flags. buffer_size shall not be
1201  * less than metadata_size.
1202  * Used via GEM ioctl.
1203  *
1204  * Returns:
1205  * 0 for success or a negative error code on failure.
1206  */
amdgpu_bo_get_metadata(struct amdgpu_bo * bo,void * buffer,size_t buffer_size,uint32_t * metadata_size,uint64_t * flags)1207 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
1208 			   size_t buffer_size, uint32_t *metadata_size,
1209 			   uint64_t *flags)
1210 {
1211 	struct amdgpu_bo_user *ubo;
1212 
1213 	if (!buffer && !metadata_size)
1214 		return -EINVAL;
1215 
1216 	BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1217 	ubo = to_amdgpu_bo_user(bo);
1218 	if (metadata_size)
1219 		*metadata_size = ubo->metadata_size;
1220 
1221 	if (buffer) {
1222 		if (buffer_size < ubo->metadata_size)
1223 			return -EINVAL;
1224 
1225 		if (ubo->metadata_size)
1226 			memcpy(buffer, ubo->metadata, ubo->metadata_size);
1227 	}
1228 
1229 	if (flags)
1230 		*flags = ubo->metadata_flags;
1231 
1232 	return 0;
1233 }
1234 
1235 /**
1236  * amdgpu_bo_move_notify - notification about a memory move
1237  * @bo: pointer to a buffer object
1238  * @evict: if this move is evicting the buffer from the graphics address space
1239  *
1240  * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs
1241  * bookkeeping.
1242  * TTM driver callback which is called when ttm moves a buffer.
1243  */
amdgpu_bo_move_notify(struct ttm_buffer_object * bo,bool evict)1244 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict)
1245 {
1246 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1247 	struct amdgpu_bo *abo;
1248 
1249 	if (!amdgpu_bo_is_amdgpu_bo(bo))
1250 		return;
1251 
1252 	abo = ttm_to_amdgpu_bo(bo);
1253 	amdgpu_vm_bo_invalidate(adev, abo, evict);
1254 
1255 	amdgpu_bo_kunmap(abo);
1256 
1257 	if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach &&
1258 	    bo->resource->mem_type != TTM_PL_SYSTEM)
1259 		dma_buf_move_notify(abo->tbo.base.dma_buf);
1260 
1261 	/* remember the eviction */
1262 	if (evict)
1263 		atomic64_inc(&adev->num_evictions);
1264 }
1265 
amdgpu_bo_get_memory(struct amdgpu_bo * bo,uint64_t * vram_mem,uint64_t * gtt_mem,uint64_t * cpu_mem)1266 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, uint64_t *vram_mem,
1267 				uint64_t *gtt_mem, uint64_t *cpu_mem)
1268 {
1269 	unsigned int domain;
1270 
1271 	domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
1272 	switch (domain) {
1273 	case AMDGPU_GEM_DOMAIN_VRAM:
1274 		*vram_mem += amdgpu_bo_size(bo);
1275 		break;
1276 	case AMDGPU_GEM_DOMAIN_GTT:
1277 		*gtt_mem += amdgpu_bo_size(bo);
1278 		break;
1279 	case AMDGPU_GEM_DOMAIN_CPU:
1280 	default:
1281 		*cpu_mem += amdgpu_bo_size(bo);
1282 		break;
1283 	}
1284 }
1285 
1286 /**
1287  * amdgpu_bo_release_notify - notification about a BO being released
1288  * @bo: pointer to a buffer object
1289  *
1290  * Wipes VRAM buffers whose contents should not be leaked before the
1291  * memory is released.
1292  */
amdgpu_bo_release_notify(struct ttm_buffer_object * bo)1293 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
1294 {
1295 	struct dma_fence *fence = NULL;
1296 	struct amdgpu_bo *abo;
1297 	int r;
1298 
1299 	if (!amdgpu_bo_is_amdgpu_bo(bo))
1300 		return;
1301 
1302 	abo = ttm_to_amdgpu_bo(bo);
1303 
1304 	if (abo->kfd_bo)
1305 		amdgpu_amdkfd_unreserve_memory_limit(abo);
1306 
1307 	/* We only remove the fence if the resv has individualized. */
1308 	WARN_ON_ONCE(bo->type == ttm_bo_type_kernel
1309 			&& bo->base.resv != &bo->base._resv);
1310 	if (bo->base.resv == &bo->base._resv)
1311 		amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);
1312 
1313 	if (bo->resource->mem_type != TTM_PL_VRAM ||
1314 	    !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE))
1315 		return;
1316 
1317 	if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv)))
1318 		return;
1319 
1320 	r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence);
1321 	if (!WARN_ON(r)) {
1322 		amdgpu_bo_fence(abo, fence, false);
1323 		dma_fence_put(fence);
1324 	}
1325 
1326 	dma_resv_unlock(bo->base.resv);
1327 }
1328 
1329 /**
1330  * amdgpu_bo_fault_reserve_notify - notification about a memory fault
1331  * @bo: pointer to a buffer object
1332  *
1333  * Notifies the driver we are taking a fault on this BO and have reserved it,
1334  * also performs bookkeeping.
1335  * TTM driver callback for dealing with vm faults.
1336  *
1337  * Returns:
1338  * 0 for success or a negative error code on failure.
1339  */
amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object * bo)1340 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
1341 {
1342 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1343 	struct ttm_operation_ctx ctx = { false, false };
1344 	struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1345 	unsigned long offset;
1346 	int r;
1347 
1348 	/* Remember that this BO was accessed by the CPU */
1349 	abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1350 
1351 	if (bo->resource->mem_type != TTM_PL_VRAM)
1352 		return 0;
1353 
1354 	offset = bo->resource->start << PAGE_SHIFT;
1355 	if ((offset + bo->base.size) <= adev->gmc.visible_vram_size)
1356 		return 0;
1357 
1358 	/* Can't move a pinned BO to visible VRAM */
1359 	if (abo->tbo.pin_count > 0)
1360 		return VM_FAULT_SIGBUS;
1361 
1362 	/* hurrah the memory is not visible ! */
1363 	atomic64_inc(&adev->num_vram_cpu_page_faults);
1364 	amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
1365 					AMDGPU_GEM_DOMAIN_GTT);
1366 
1367 	/* Avoid costly evictions; only set GTT as a busy placement */
1368 	abo->placement.num_busy_placement = 1;
1369 	abo->placement.busy_placement = &abo->placements[1];
1370 
1371 	r = ttm_bo_validate(bo, &abo->placement, &ctx);
1372 	if (unlikely(r == -EBUSY || r == -ERESTARTSYS))
1373 		return VM_FAULT_NOPAGE;
1374 	else if (unlikely(r))
1375 		return VM_FAULT_SIGBUS;
1376 
1377 	offset = bo->resource->start << PAGE_SHIFT;
1378 	/* this should never happen */
1379 	if (bo->resource->mem_type == TTM_PL_VRAM &&
1380 	    (offset + bo->base.size) > adev->gmc.visible_vram_size)
1381 		return VM_FAULT_SIGBUS;
1382 
1383 	ttm_bo_move_to_lru_tail_unlocked(bo);
1384 	return 0;
1385 }
1386 
1387 /**
1388  * amdgpu_bo_fence - add fence to buffer object
1389  *
1390  * @bo: buffer object in question
1391  * @fence: fence to add
1392  * @shared: true if fence should be added shared
1393  *
1394  */
amdgpu_bo_fence(struct amdgpu_bo * bo,struct dma_fence * fence,bool shared)1395 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1396 		     bool shared)
1397 {
1398 	struct dma_resv *resv = bo->tbo.base.resv;
1399 
1400 	if (shared)
1401 		dma_resv_add_shared_fence(resv, fence);
1402 	else
1403 		dma_resv_add_excl_fence(resv, fence);
1404 }
1405 
1406 /**
1407  * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences
1408  *
1409  * @adev: amdgpu device pointer
1410  * @resv: reservation object to sync to
1411  * @sync_mode: synchronization mode
1412  * @owner: fence owner
1413  * @intr: Whether the wait is interruptible
1414  *
1415  * Extract the fences from the reservation object and waits for them to finish.
1416  *
1417  * Returns:
1418  * 0 on success, errno otherwise.
1419  */
amdgpu_bo_sync_wait_resv(struct amdgpu_device * adev,struct dma_resv * resv,enum amdgpu_sync_mode sync_mode,void * owner,bool intr)1420 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
1421 			     enum amdgpu_sync_mode sync_mode, void *owner,
1422 			     bool intr)
1423 {
1424 	struct amdgpu_sync sync;
1425 	int r;
1426 
1427 	amdgpu_sync_create(&sync);
1428 	amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);
1429 	r = amdgpu_sync_wait(&sync, intr);
1430 	amdgpu_sync_free(&sync);
1431 	return r;
1432 }
1433 
1434 /**
1435  * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv
1436  * @bo: buffer object to wait for
1437  * @owner: fence owner
1438  * @intr: Whether the wait is interruptible
1439  *
1440  * Wrapper to wait for fences in a BO.
1441  * Returns:
1442  * 0 on success, errno otherwise.
1443  */
amdgpu_bo_sync_wait(struct amdgpu_bo * bo,void * owner,bool intr)1444 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
1445 {
1446 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1447 
1448 	return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,
1449 					AMDGPU_SYNC_NE_OWNER, owner, intr);
1450 }
1451 
1452 /**
1453  * amdgpu_bo_gpu_offset - return GPU offset of bo
1454  * @bo:	amdgpu object for which we query the offset
1455  *
1456  * Note: object should either be pinned or reserved when calling this
1457  * function, it might be useful to add check for this for debugging.
1458  *
1459  * Returns:
1460  * current GPU offset of the object.
1461  */
amdgpu_bo_gpu_offset(struct amdgpu_bo * bo)1462 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1463 {
1464 	WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM);
1465 	WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) &&
1466 		     !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel);
1467 	WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET);
1468 	WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM &&
1469 		     !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1470 
1471 	return amdgpu_bo_gpu_offset_no_check(bo);
1472 }
1473 
1474 /**
1475  * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo
1476  * @bo:	amdgpu object for which we query the offset
1477  *
1478  * Returns:
1479  * current GPU offset of the object without raising warnings.
1480  */
amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo * bo)1481 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
1482 {
1483 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1484 	uint64_t offset;
1485 
1486 	offset = (bo->tbo.resource->start << PAGE_SHIFT) +
1487 		 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
1488 
1489 	return amdgpu_gmc_sign_extend(offset);
1490 }
1491 
1492 /**
1493  * amdgpu_bo_get_preferred_domain - get preferred domain
1494  * @adev: amdgpu device object
1495  * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>`
1496  *
1497  * Returns:
1498  * Which of the allowed domains is preferred for allocating the BO.
1499  */
amdgpu_bo_get_preferred_domain(struct amdgpu_device * adev,uint32_t domain)1500 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
1501 					    uint32_t domain)
1502 {
1503 	if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
1504 		domain = AMDGPU_GEM_DOMAIN_VRAM;
1505 		if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
1506 			domain = AMDGPU_GEM_DOMAIN_GTT;
1507 	}
1508 	return domain;
1509 }
1510 
1511 #if defined(CONFIG_DEBUG_FS)
1512 #define amdgpu_bo_print_flag(m, bo, flag)		        \
1513 	do {							\
1514 		if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) {	\
1515 			seq_printf((m), " " #flag);		\
1516 		}						\
1517 	} while (0)
1518 
1519 /**
1520  * amdgpu_bo_print_info - print BO info in debugfs file
1521  *
1522  * @id: Index or Id of the BO
1523  * @bo: Requested BO for printing info
1524  * @m: debugfs file
1525  *
1526  * Print BO information in debugfs file
1527  *
1528  * Returns:
1529  * Size of the BO in bytes.
1530  */
amdgpu_bo_print_info(int id,struct amdgpu_bo * bo,struct seq_file * m)1531 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)
1532 {
1533 	struct dma_buf_attachment *attachment;
1534 	struct dma_buf *dma_buf;
1535 	unsigned int domain;
1536 	const char *placement;
1537 	unsigned int pin_count;
1538 	u64 size;
1539 
1540 	domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
1541 	switch (domain) {
1542 	case AMDGPU_GEM_DOMAIN_VRAM:
1543 		placement = "VRAM";
1544 		break;
1545 	case AMDGPU_GEM_DOMAIN_GTT:
1546 		placement = " GTT";
1547 		break;
1548 	case AMDGPU_GEM_DOMAIN_CPU:
1549 	default:
1550 		placement = " CPU";
1551 		break;
1552 	}
1553 
1554 	size = amdgpu_bo_size(bo);
1555 	seq_printf(m, "\t\t0x%08x: %12lld byte %s",
1556 			id, size, placement);
1557 
1558 	pin_count = READ_ONCE(bo->tbo.pin_count);
1559 	if (pin_count)
1560 		seq_printf(m, " pin count %d", pin_count);
1561 
1562 	dma_buf = READ_ONCE(bo->tbo.base.dma_buf);
1563 	attachment = READ_ONCE(bo->tbo.base.import_attach);
1564 
1565 	if (attachment)
1566 		seq_printf(m, " imported from %p", dma_buf);
1567 	else if (dma_buf)
1568 		seq_printf(m, " exported as %p", dma_buf);
1569 
1570 	amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
1571 	amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS);
1572 	amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC);
1573 	amdgpu_bo_print_flag(m, bo, VRAM_CLEARED);
1574 	amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
1575 	amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID);
1576 	amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC);
1577 
1578 	seq_puts(m, "\n");
1579 
1580 	return size;
1581 }
1582 #endif
1583