1 /*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 /*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32
33 #include <linux/dma-mapping.h>
34 #include <linux/iommu.h>
35 #include <linux/pagemap.h>
36 #include <linux/sched/task.h>
37 #include <linux/sched/mm.h>
38 #include <linux/seq_file.h>
39 #include <linux/slab.h>
40 #include <linux/swap.h>
41 #include <linux/swiotlb.h>
42 #include <linux/dma-buf.h>
43 #include <linux/sizes.h>
44
45 #include <drm/ttm/ttm_bo_api.h>
46 #include <drm/ttm/ttm_bo_driver.h>
47 #include <drm/ttm/ttm_placement.h>
48 #include <drm/ttm/ttm_range_manager.h>
49
50 #include <drm/amdgpu_drm.h>
51
52 #include "amdgpu.h"
53 #include "amdgpu_object.h"
54 #include "amdgpu_trace.h"
55 #include "amdgpu_amdkfd.h"
56 #include "amdgpu_sdma.h"
57 #include "amdgpu_ras.h"
58 #include "amdgpu_atomfirmware.h"
59 #include "amdgpu_res_cursor.h"
60 #include "bif/bif_4_1_d.h"
61
62 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128
63
64 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
65 struct ttm_tt *ttm,
66 struct ttm_resource *bo_mem);
67 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
68 struct ttm_tt *ttm);
69
amdgpu_ttm_init_on_chip(struct amdgpu_device * adev,unsigned int type,uint64_t size_in_page)70 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
71 unsigned int type,
72 uint64_t size_in_page)
73 {
74 return ttm_range_man_init(&adev->mman.bdev, type,
75 false, size_in_page);
76 }
77
78 /**
79 * amdgpu_evict_flags - Compute placement flags
80 *
81 * @bo: The buffer object to evict
82 * @placement: Possible destination(s) for evicted BO
83 *
84 * Fill in placement data when ttm_bo_evict() is called
85 */
amdgpu_evict_flags(struct ttm_buffer_object * bo,struct ttm_placement * placement)86 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
87 struct ttm_placement *placement)
88 {
89 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
90 struct amdgpu_bo *abo;
91 static const struct ttm_place placements = {
92 .fpfn = 0,
93 .lpfn = 0,
94 .mem_type = TTM_PL_SYSTEM,
95 .flags = 0
96 };
97
98 /* Don't handle scatter gather BOs */
99 if (bo->type == ttm_bo_type_sg) {
100 placement->num_placement = 0;
101 placement->num_busy_placement = 0;
102 return;
103 }
104
105 /* Object isn't an AMDGPU object so ignore */
106 if (!amdgpu_bo_is_amdgpu_bo(bo)) {
107 placement->placement = &placements;
108 placement->busy_placement = &placements;
109 placement->num_placement = 1;
110 placement->num_busy_placement = 1;
111 return;
112 }
113
114 abo = ttm_to_amdgpu_bo(bo);
115 if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) {
116 struct dma_fence *fence;
117 struct dma_resv *resv = &bo->base._resv;
118
119 rcu_read_lock();
120 fence = rcu_dereference(resv->fence_excl);
121 if (fence && !fence->ops->signaled)
122 dma_fence_enable_sw_signaling(fence);
123
124 placement->num_placement = 0;
125 placement->num_busy_placement = 0;
126 rcu_read_unlock();
127 return;
128 }
129
130 switch (bo->resource->mem_type) {
131 case AMDGPU_PL_GDS:
132 case AMDGPU_PL_GWS:
133 case AMDGPU_PL_OA:
134 placement->num_placement = 0;
135 placement->num_busy_placement = 0;
136 return;
137
138 case TTM_PL_VRAM:
139 if (!adev->mman.buffer_funcs_enabled) {
140 /* Move to system memory */
141 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
142 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
143 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
144 amdgpu_bo_in_cpu_visible_vram(abo)) {
145
146 /* Try evicting to the CPU inaccessible part of VRAM
147 * first, but only set GTT as busy placement, so this
148 * BO will be evicted to GTT rather than causing other
149 * BOs to be evicted from VRAM
150 */
151 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
152 AMDGPU_GEM_DOMAIN_GTT |
153 AMDGPU_GEM_DOMAIN_CPU);
154 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
155 abo->placements[0].lpfn = 0;
156 abo->placement.busy_placement = &abo->placements[1];
157 abo->placement.num_busy_placement = 1;
158 } else {
159 /* Move to GTT memory */
160 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT |
161 AMDGPU_GEM_DOMAIN_CPU);
162 }
163 break;
164 case TTM_PL_TT:
165 case AMDGPU_PL_PREEMPT:
166 default:
167 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
168 break;
169 }
170 *placement = abo->placement;
171 }
172
173 /**
174 * amdgpu_ttm_map_buffer - Map memory into the GART windows
175 * @bo: buffer object to map
176 * @mem: memory object to map
177 * @mm_cur: range to map
178 * @num_pages: number of pages to map
179 * @window: which GART window to use
180 * @ring: DMA ring to use for the copy
181 * @tmz: if we should setup a TMZ enabled mapping
182 * @addr: resulting address inside the MC address space
183 *
184 * Setup one of the GART windows to access a specific piece of memory or return
185 * the physical address for local memory.
186 */
amdgpu_ttm_map_buffer(struct ttm_buffer_object * bo,struct ttm_resource * mem,struct amdgpu_res_cursor * mm_cur,unsigned num_pages,unsigned window,struct amdgpu_ring * ring,bool tmz,uint64_t * addr)187 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
188 struct ttm_resource *mem,
189 struct amdgpu_res_cursor *mm_cur,
190 unsigned num_pages, unsigned window,
191 struct amdgpu_ring *ring, bool tmz,
192 uint64_t *addr)
193 {
194 struct amdgpu_device *adev = ring->adev;
195 struct amdgpu_job *job;
196 unsigned num_dw, num_bytes;
197 struct dma_fence *fence;
198 uint64_t src_addr, dst_addr;
199 void *cpu_addr;
200 uint64_t flags;
201 unsigned int i;
202 int r;
203
204 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
205 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
206 BUG_ON(mem->mem_type == AMDGPU_PL_PREEMPT);
207
208 /* Map only what can't be accessed directly */
209 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
210 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
211 mm_cur->start;
212 return 0;
213 }
214
215 *addr = adev->gmc.gart_start;
216 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
217 AMDGPU_GPU_PAGE_SIZE;
218 *addr += mm_cur->start & ~PAGE_MASK;
219
220 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
221 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
222
223 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
224 AMDGPU_IB_POOL_DELAYED, &job);
225 if (r)
226 return r;
227
228 src_addr = num_dw * 4;
229 src_addr += job->ibs[0].gpu_addr;
230
231 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
232 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
233 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
234 dst_addr, num_bytes, false);
235
236 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
237 WARN_ON(job->ibs[0].length_dw > num_dw);
238
239 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
240 if (tmz)
241 flags |= AMDGPU_PTE_TMZ;
242
243 cpu_addr = &job->ibs[0].ptr[num_dw];
244
245 if (mem->mem_type == TTM_PL_TT) {
246 dma_addr_t *dma_addr;
247
248 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
249 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags,
250 cpu_addr);
251 if (r)
252 goto error_free;
253 } else {
254 dma_addr_t dma_address;
255
256 dma_address = mm_cur->start;
257 dma_address += adev->vm_manager.vram_base_offset;
258
259 for (i = 0; i < num_pages; ++i) {
260 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
261 &dma_address, flags, cpu_addr);
262 if (r)
263 goto error_free;
264
265 dma_address += PAGE_SIZE;
266 }
267 }
268
269 r = amdgpu_job_submit(job, &adev->mman.entity,
270 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
271 if (r)
272 goto error_free;
273
274 dma_fence_put(fence);
275
276 return r;
277
278 error_free:
279 amdgpu_job_free(job);
280 return r;
281 }
282
283 /**
284 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy
285 * @adev: amdgpu device
286 * @src: buffer/address where to read from
287 * @dst: buffer/address where to write to
288 * @size: number of bytes to copy
289 * @tmz: if a secure copy should be used
290 * @resv: resv object to sync to
291 * @f: Returns the last fence if multiple jobs are submitted.
292 *
293 * The function copies @size bytes from {src->mem + src->offset} to
294 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
295 * move and different for a BO to BO copy.
296 *
297 */
amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device * adev,const struct amdgpu_copy_mem * src,const struct amdgpu_copy_mem * dst,uint64_t size,bool tmz,struct dma_resv * resv,struct dma_fence ** f)298 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
299 const struct amdgpu_copy_mem *src,
300 const struct amdgpu_copy_mem *dst,
301 uint64_t size, bool tmz,
302 struct dma_resv *resv,
303 struct dma_fence **f)
304 {
305 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
306 AMDGPU_GPU_PAGE_SIZE);
307
308 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
309 struct amdgpu_res_cursor src_mm, dst_mm;
310 struct dma_fence *fence = NULL;
311 int r = 0;
312
313 if (!adev->mman.buffer_funcs_enabled) {
314 DRM_ERROR("Trying to move memory with ring turned off.\n");
315 return -EINVAL;
316 }
317
318 amdgpu_res_first(src->mem, src->offset, size, &src_mm);
319 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
320
321 mutex_lock(&adev->mman.gtt_window_lock);
322 while (src_mm.remaining) {
323 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK;
324 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK;
325 struct dma_fence *next;
326 uint32_t cur_size;
327 uint64_t from, to;
328
329 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
330 * begins at an offset, then adjust the size accordingly
331 */
332 cur_size = max(src_page_offset, dst_page_offset);
333 cur_size = min(min3(src_mm.size, dst_mm.size, size),
334 (uint64_t)(GTT_MAX_BYTES - cur_size));
335
336 /* Map src to window 0 and dst to window 1. */
337 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
338 PFN_UP(cur_size + src_page_offset),
339 0, ring, tmz, &from);
340 if (r)
341 goto error;
342
343 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
344 PFN_UP(cur_size + dst_page_offset),
345 1, ring, tmz, &to);
346 if (r)
347 goto error;
348
349 r = amdgpu_copy_buffer(ring, from, to, cur_size,
350 resv, &next, false, true, tmz);
351 if (r)
352 goto error;
353
354 dma_fence_put(fence);
355 fence = next;
356
357 amdgpu_res_next(&src_mm, cur_size);
358 amdgpu_res_next(&dst_mm, cur_size);
359 }
360 error:
361 mutex_unlock(&adev->mman.gtt_window_lock);
362 if (f)
363 *f = dma_fence_get(fence);
364 dma_fence_put(fence);
365 return r;
366 }
367
368 /*
369 * amdgpu_move_blit - Copy an entire buffer to another buffer
370 *
371 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
372 * help move buffers to and from VRAM.
373 */
amdgpu_move_blit(struct ttm_buffer_object * bo,bool evict,struct ttm_resource * new_mem,struct ttm_resource * old_mem)374 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
375 bool evict,
376 struct ttm_resource *new_mem,
377 struct ttm_resource *old_mem)
378 {
379 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
380 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
381 struct amdgpu_copy_mem src, dst;
382 struct dma_fence *fence = NULL;
383 int r;
384
385 src.bo = bo;
386 dst.bo = bo;
387 src.mem = old_mem;
388 dst.mem = new_mem;
389 src.offset = 0;
390 dst.offset = 0;
391
392 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
393 new_mem->num_pages << PAGE_SHIFT,
394 amdgpu_bo_encrypted(abo),
395 bo->base.resv, &fence);
396 if (r)
397 goto error;
398
399 /* clear the space being freed */
400 if (old_mem->mem_type == TTM_PL_VRAM &&
401 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
402 struct dma_fence *wipe_fence = NULL;
403
404 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
405 NULL, &wipe_fence);
406 if (r) {
407 goto error;
408 } else if (wipe_fence) {
409 dma_fence_put(fence);
410 fence = wipe_fence;
411 }
412 }
413
414 /* Always block for VM page tables before committing the new location */
415 if (bo->type == ttm_bo_type_kernel)
416 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
417 else
418 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
419 dma_fence_put(fence);
420 return r;
421
422 error:
423 if (fence)
424 dma_fence_wait(fence, false);
425 dma_fence_put(fence);
426 return r;
427 }
428
429 /*
430 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
431 *
432 * Called by amdgpu_bo_move()
433 */
amdgpu_mem_visible(struct amdgpu_device * adev,struct ttm_resource * mem)434 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
435 struct ttm_resource *mem)
436 {
437 uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT;
438 struct amdgpu_res_cursor cursor;
439
440 if (mem->mem_type == TTM_PL_SYSTEM ||
441 mem->mem_type == TTM_PL_TT)
442 return true;
443 if (mem->mem_type != TTM_PL_VRAM)
444 return false;
445
446 amdgpu_res_first(mem, 0, mem_size, &cursor);
447
448 /* ttm_resource_ioremap only supports contiguous memory */
449 if (cursor.size != mem_size)
450 return false;
451
452 return cursor.start + cursor.size <= adev->gmc.visible_vram_size;
453 }
454
455 /*
456 * amdgpu_bo_move - Move a buffer object to a new memory location
457 *
458 * Called by ttm_bo_handle_move_mem()
459 */
amdgpu_bo_move(struct ttm_buffer_object * bo,bool evict,struct ttm_operation_ctx * ctx,struct ttm_resource * new_mem,struct ttm_place * hop)460 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
461 struct ttm_operation_ctx *ctx,
462 struct ttm_resource *new_mem,
463 struct ttm_place *hop)
464 {
465 struct amdgpu_device *adev;
466 struct amdgpu_bo *abo;
467 struct ttm_resource *old_mem = bo->resource;
468 int r;
469
470 if (new_mem->mem_type == TTM_PL_TT ||
471 new_mem->mem_type == AMDGPU_PL_PREEMPT) {
472 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
473 if (r)
474 return r;
475 }
476
477 /* Can't move a pinned BO */
478 abo = ttm_to_amdgpu_bo(bo);
479 if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
480 return -EINVAL;
481
482 adev = amdgpu_ttm_adev(bo->bdev);
483
484 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
485 ttm_bo_move_null(bo, new_mem);
486 goto out;
487 }
488 if (old_mem->mem_type == TTM_PL_SYSTEM &&
489 (new_mem->mem_type == TTM_PL_TT ||
490 new_mem->mem_type == AMDGPU_PL_PREEMPT)) {
491 ttm_bo_move_null(bo, new_mem);
492 goto out;
493 }
494 if ((old_mem->mem_type == TTM_PL_TT ||
495 old_mem->mem_type == AMDGPU_PL_PREEMPT) &&
496 new_mem->mem_type == TTM_PL_SYSTEM) {
497 r = ttm_bo_wait_ctx(bo, ctx);
498 if (r)
499 return r;
500
501 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
502 ttm_resource_free(bo, &bo->resource);
503 ttm_bo_assign_mem(bo, new_mem);
504 goto out;
505 }
506
507 if (old_mem->mem_type == AMDGPU_PL_GDS ||
508 old_mem->mem_type == AMDGPU_PL_GWS ||
509 old_mem->mem_type == AMDGPU_PL_OA ||
510 new_mem->mem_type == AMDGPU_PL_GDS ||
511 new_mem->mem_type == AMDGPU_PL_GWS ||
512 new_mem->mem_type == AMDGPU_PL_OA) {
513 /* Nothing to save here */
514 ttm_bo_move_null(bo, new_mem);
515 goto out;
516 }
517
518 if (bo->type == ttm_bo_type_device &&
519 new_mem->mem_type == TTM_PL_VRAM &&
520 old_mem->mem_type != TTM_PL_VRAM) {
521 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
522 * accesses the BO after it's moved.
523 */
524 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
525 }
526
527 if (adev->mman.buffer_funcs_enabled) {
528 if (((old_mem->mem_type == TTM_PL_SYSTEM &&
529 new_mem->mem_type == TTM_PL_VRAM) ||
530 (old_mem->mem_type == TTM_PL_VRAM &&
531 new_mem->mem_type == TTM_PL_SYSTEM))) {
532 hop->fpfn = 0;
533 hop->lpfn = 0;
534 hop->mem_type = TTM_PL_TT;
535 hop->flags = TTM_PL_FLAG_TEMPORARY;
536 return -EMULTIHOP;
537 }
538
539 r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
540 } else {
541 r = -ENODEV;
542 }
543
544 if (r) {
545 /* Check that all memory is CPU accessible */
546 if (!amdgpu_mem_visible(adev, old_mem) ||
547 !amdgpu_mem_visible(adev, new_mem)) {
548 pr_err("Move buffer fallback to memcpy unavailable\n");
549 return r;
550 }
551
552 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
553 if (r)
554 return r;
555 }
556
557 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
558 out:
559 /* update statistics */
560 atomic64_add(bo->base.size, &adev->num_bytes_moved);
561 amdgpu_bo_move_notify(bo, evict);
562 return 0;
563 }
564
565 /*
566 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
567 *
568 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
569 */
amdgpu_ttm_io_mem_reserve(struct ttm_device * bdev,struct ttm_resource * mem)570 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
571 struct ttm_resource *mem)
572 {
573 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
574 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
575
576 switch (mem->mem_type) {
577 case TTM_PL_SYSTEM:
578 /* system memory */
579 return 0;
580 case TTM_PL_TT:
581 case AMDGPU_PL_PREEMPT:
582 break;
583 case TTM_PL_VRAM:
584 mem->bus.offset = mem->start << PAGE_SHIFT;
585 /* check if it's visible */
586 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
587 return -EINVAL;
588
589 if (adev->mman.aper_base_kaddr &&
590 mem->placement & TTM_PL_FLAG_CONTIGUOUS)
591 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
592 mem->bus.offset;
593
594 mem->bus.offset += adev->gmc.aper_base;
595 mem->bus.is_iomem = true;
596 break;
597 default:
598 return -EINVAL;
599 }
600 return 0;
601 }
602
amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object * bo,unsigned long page_offset)603 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
604 unsigned long page_offset)
605 {
606 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
607 struct amdgpu_res_cursor cursor;
608
609 amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,
610 &cursor);
611 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
612 }
613
614 /**
615 * amdgpu_ttm_domain_start - Returns GPU start address
616 * @adev: amdgpu device object
617 * @type: type of the memory
618 *
619 * Returns:
620 * GPU start address of a memory domain
621 */
622
amdgpu_ttm_domain_start(struct amdgpu_device * adev,uint32_t type)623 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
624 {
625 switch (type) {
626 case TTM_PL_TT:
627 return adev->gmc.gart_start;
628 case TTM_PL_VRAM:
629 return adev->gmc.vram_start;
630 }
631
632 return 0;
633 }
634
635 /*
636 * TTM backend functions.
637 */
638 struct amdgpu_ttm_tt {
639 struct ttm_tt ttm;
640 struct drm_gem_object *gobj;
641 u64 offset;
642 uint64_t userptr;
643 struct task_struct *usertask;
644 uint32_t userflags;
645 bool bound;
646 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
647 struct hmm_range *range;
648 #endif
649 };
650
651 #ifdef CONFIG_DRM_AMDGPU_USERPTR
652 /*
653 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
654 * memory and start HMM tracking CPU page table update
655 *
656 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
657 * once afterwards to stop HMM tracking
658 */
amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo * bo,struct page ** pages)659 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
660 {
661 struct ttm_tt *ttm = bo->tbo.ttm;
662 struct amdgpu_ttm_tt *gtt = (void *)ttm;
663 unsigned long start = gtt->userptr;
664 struct vm_area_struct *vma;
665 struct mm_struct *mm;
666 bool readonly;
667 int r = 0;
668
669 mm = bo->notifier.mm;
670 if (unlikely(!mm)) {
671 DRM_DEBUG_DRIVER("BO is not registered?\n");
672 return -EFAULT;
673 }
674
675 /* Another get_user_pages is running at the same time?? */
676 if (WARN_ON(gtt->range))
677 return -EFAULT;
678
679 if (!mmget_not_zero(mm)) /* Happens during process shutdown */
680 return -ESRCH;
681
682 mmap_read_lock(mm);
683 vma = vma_lookup(mm, start);
684 if (unlikely(!vma)) {
685 r = -EFAULT;
686 goto out_unlock;
687 }
688 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
689 vma->vm_file)) {
690 r = -EPERM;
691 goto out_unlock;
692 }
693
694 readonly = amdgpu_ttm_tt_is_readonly(ttm);
695 r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start,
696 ttm->num_pages, >t->range, readonly,
697 true, NULL);
698 out_unlock:
699 mmap_read_unlock(mm);
700 mmput(mm);
701
702 return r;
703 }
704
705 /*
706 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
707 * Check if the pages backing this ttm range have been invalidated
708 *
709 * Returns: true if pages are still valid
710 */
amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt * ttm)711 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
712 {
713 struct amdgpu_ttm_tt *gtt = (void *)ttm;
714 bool r = false;
715
716 if (!gtt || !gtt->userptr)
717 return false;
718
719 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
720 gtt->userptr, ttm->num_pages);
721
722 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
723 "No user pages to check\n");
724
725 if (gtt->range) {
726 /*
727 * FIXME: Must always hold notifier_lock for this, and must
728 * not ignore the return code.
729 */
730 r = amdgpu_hmm_range_get_pages_done(gtt->range);
731 gtt->range = NULL;
732 }
733
734 return !r;
735 }
736 #endif
737
738 /*
739 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
740 *
741 * Called by amdgpu_cs_list_validate(). This creates the page list
742 * that backs user memory and will ultimately be mapped into the device
743 * address space.
744 */
amdgpu_ttm_tt_set_user_pages(struct ttm_tt * ttm,struct page ** pages)745 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
746 {
747 unsigned long i;
748
749 for (i = 0; i < ttm->num_pages; ++i)
750 ttm->pages[i] = pages ? pages[i] : NULL;
751 }
752
753 /*
754 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
755 *
756 * Called by amdgpu_ttm_backend_bind()
757 **/
amdgpu_ttm_tt_pin_userptr(struct ttm_device * bdev,struct ttm_tt * ttm)758 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
759 struct ttm_tt *ttm)
760 {
761 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
762 struct amdgpu_ttm_tt *gtt = (void *)ttm;
763 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
764 enum dma_data_direction direction = write ?
765 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
766 int r;
767
768 /* Allocate an SG array and squash pages into it */
769 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
770 (u64)ttm->num_pages << PAGE_SHIFT,
771 GFP_KERNEL);
772 if (r)
773 goto release_sg;
774
775 /* Map SG to device */
776 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
777 if (r)
778 goto release_sg;
779
780 /* convert SG to linear array of pages and dma addresses */
781 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
782 ttm->num_pages);
783
784 return 0;
785
786 release_sg:
787 kfree(ttm->sg);
788 ttm->sg = NULL;
789 return r;
790 }
791
792 /*
793 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
794 */
amdgpu_ttm_tt_unpin_userptr(struct ttm_device * bdev,struct ttm_tt * ttm)795 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
796 struct ttm_tt *ttm)
797 {
798 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
799 struct amdgpu_ttm_tt *gtt = (void *)ttm;
800 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
801 enum dma_data_direction direction = write ?
802 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
803
804 /* double check that we don't free the table twice */
805 if (!ttm->sg || !ttm->sg->sgl)
806 return;
807
808 /* unmap the pages mapped to the device */
809 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
810 sg_free_table(ttm->sg);
811
812 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
813 if (gtt->range) {
814 unsigned long i;
815
816 for (i = 0; i < ttm->num_pages; i++) {
817 if (ttm->pages[i] !=
818 hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
819 break;
820 }
821
822 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
823 }
824 #endif
825 }
826
amdgpu_ttm_gart_bind(struct amdgpu_device * adev,struct ttm_buffer_object * tbo,uint64_t flags)827 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
828 struct ttm_buffer_object *tbo,
829 uint64_t flags)
830 {
831 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
832 struct ttm_tt *ttm = tbo->ttm;
833 struct amdgpu_ttm_tt *gtt = (void *)ttm;
834 int r;
835
836 if (amdgpu_bo_encrypted(abo))
837 flags |= AMDGPU_PTE_TMZ;
838
839 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
840 uint64_t page_idx = 1;
841
842 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
843 gtt->ttm.dma_address, flags);
844 if (r)
845 goto gart_bind_fail;
846
847 /* The memory type of the first page defaults to UC. Now
848 * modify the memory type to NC from the second page of
849 * the BO onward.
850 */
851 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
852 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
853
854 r = amdgpu_gart_bind(adev,
855 gtt->offset + (page_idx << PAGE_SHIFT),
856 ttm->num_pages - page_idx,
857 &(gtt->ttm.dma_address[page_idx]), flags);
858 } else {
859 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
860 gtt->ttm.dma_address, flags);
861 }
862
863 gart_bind_fail:
864 if (r)
865 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
866 ttm->num_pages, gtt->offset);
867
868 return r;
869 }
870
871 /*
872 * amdgpu_ttm_backend_bind - Bind GTT memory
873 *
874 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
875 * This handles binding GTT memory to the device address space.
876 */
amdgpu_ttm_backend_bind(struct ttm_device * bdev,struct ttm_tt * ttm,struct ttm_resource * bo_mem)877 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
878 struct ttm_tt *ttm,
879 struct ttm_resource *bo_mem)
880 {
881 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
882 struct amdgpu_ttm_tt *gtt = (void*)ttm;
883 uint64_t flags;
884 int r = 0;
885
886 if (!bo_mem)
887 return -EINVAL;
888
889 if (gtt->bound)
890 return 0;
891
892 if (gtt->userptr) {
893 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
894 if (r) {
895 DRM_ERROR("failed to pin userptr\n");
896 return r;
897 }
898 } else if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
899 if (!ttm->sg) {
900 struct dma_buf_attachment *attach;
901 struct sg_table *sgt;
902
903 attach = gtt->gobj->import_attach;
904 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
905 if (IS_ERR(sgt))
906 return PTR_ERR(sgt);
907
908 ttm->sg = sgt;
909 }
910
911 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
912 ttm->num_pages);
913 }
914
915 if (!ttm->num_pages) {
916 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
917 ttm->num_pages, bo_mem, ttm);
918 }
919
920 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
921 bo_mem->mem_type == AMDGPU_PL_GWS ||
922 bo_mem->mem_type == AMDGPU_PL_OA)
923 return -EINVAL;
924
925 if (bo_mem->mem_type != TTM_PL_TT ||
926 !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
927 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
928 return 0;
929 }
930
931 /* compute PTE flags relevant to this BO memory */
932 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
933
934 /* bind pages into GART page tables */
935 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
936 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
937 gtt->ttm.dma_address, flags);
938
939 if (r)
940 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
941 ttm->num_pages, gtt->offset);
942 gtt->bound = true;
943 return r;
944 }
945
946 /*
947 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
948 * through AGP or GART aperture.
949 *
950 * If bo is accessible through AGP aperture, then use AGP aperture
951 * to access bo; otherwise allocate logical space in GART aperture
952 * and map bo to GART aperture.
953 */
amdgpu_ttm_alloc_gart(struct ttm_buffer_object * bo)954 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
955 {
956 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
957 struct ttm_operation_ctx ctx = { false, false };
958 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
959 struct ttm_placement placement;
960 struct ttm_place placements;
961 struct ttm_resource *tmp;
962 uint64_t addr, flags;
963 int r;
964
965 if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET)
966 return 0;
967
968 addr = amdgpu_gmc_agp_addr(bo);
969 if (addr != AMDGPU_BO_INVALID_OFFSET) {
970 bo->resource->start = addr >> PAGE_SHIFT;
971 return 0;
972 }
973
974 /* allocate GART space */
975 placement.num_placement = 1;
976 placement.placement = &placements;
977 placement.num_busy_placement = 1;
978 placement.busy_placement = &placements;
979 placements.fpfn = 0;
980 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
981 placements.mem_type = TTM_PL_TT;
982 placements.flags = bo->resource->placement;
983
984 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
985 if (unlikely(r))
986 return r;
987
988 /* compute PTE flags for this buffer object */
989 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp);
990
991 /* Bind pages */
992 gtt->offset = (u64)tmp->start << PAGE_SHIFT;
993 r = amdgpu_ttm_gart_bind(adev, bo, flags);
994 if (unlikely(r)) {
995 ttm_resource_free(bo, &tmp);
996 return r;
997 }
998
999 amdgpu_gart_invalidate_tlb(adev);
1000 ttm_resource_free(bo, &bo->resource);
1001 ttm_bo_assign_mem(bo, tmp);
1002
1003 return 0;
1004 }
1005
1006 /*
1007 * amdgpu_ttm_recover_gart - Rebind GTT pages
1008 *
1009 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1010 * rebind GTT pages during a GPU reset.
1011 */
amdgpu_ttm_recover_gart(struct ttm_buffer_object * tbo)1012 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1013 {
1014 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1015 uint64_t flags;
1016 int r;
1017
1018 if (!tbo->ttm)
1019 return 0;
1020
1021 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource);
1022 r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1023
1024 return r;
1025 }
1026
1027 /*
1028 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1029 *
1030 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1031 * ttm_tt_destroy().
1032 */
amdgpu_ttm_backend_unbind(struct ttm_device * bdev,struct ttm_tt * ttm)1033 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
1034 struct ttm_tt *ttm)
1035 {
1036 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1037 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1038 int r;
1039
1040 /* if the pages have userptr pinning then clear that first */
1041 if (gtt->userptr) {
1042 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1043 } else if (ttm->sg && gtt->gobj->import_attach) {
1044 struct dma_buf_attachment *attach;
1045
1046 attach = gtt->gobj->import_attach;
1047 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1048 ttm->sg = NULL;
1049 }
1050
1051 if (!gtt->bound)
1052 return;
1053
1054 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1055 return;
1056
1057 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1058 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1059 if (r)
1060 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n",
1061 gtt->ttm.num_pages, gtt->offset);
1062 gtt->bound = false;
1063 }
1064
amdgpu_ttm_backend_destroy(struct ttm_device * bdev,struct ttm_tt * ttm)1065 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1066 struct ttm_tt *ttm)
1067 {
1068 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1069
1070 amdgpu_ttm_backend_unbind(bdev, ttm);
1071 ttm_tt_destroy_common(bdev, ttm);
1072 if (gtt->usertask)
1073 put_task_struct(gtt->usertask);
1074
1075 ttm_tt_fini(>t->ttm);
1076 kfree(gtt);
1077 }
1078
1079 /**
1080 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1081 *
1082 * @bo: The buffer object to create a GTT ttm_tt object around
1083 * @page_flags: Page flags to be added to the ttm_tt object
1084 *
1085 * Called by ttm_tt_create().
1086 */
amdgpu_ttm_tt_create(struct ttm_buffer_object * bo,uint32_t page_flags)1087 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1088 uint32_t page_flags)
1089 {
1090 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1091 struct amdgpu_ttm_tt *gtt;
1092 enum ttm_caching caching;
1093
1094 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1095 if (gtt == NULL) {
1096 return NULL;
1097 }
1098 gtt->gobj = &bo->base;
1099
1100 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1101 caching = ttm_write_combined;
1102 else
1103 caching = ttm_cached;
1104
1105 /* allocate space for the uninitialized page entries */
1106 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) {
1107 kfree(gtt);
1108 return NULL;
1109 }
1110 return >t->ttm;
1111 }
1112
1113 /*
1114 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1115 *
1116 * Map the pages of a ttm_tt object to an address space visible
1117 * to the underlying device.
1118 */
amdgpu_ttm_tt_populate(struct ttm_device * bdev,struct ttm_tt * ttm,struct ttm_operation_ctx * ctx)1119 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1120 struct ttm_tt *ttm,
1121 struct ttm_operation_ctx *ctx)
1122 {
1123 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1124 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1125
1126 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1127 if (gtt->userptr) {
1128 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1129 if (!ttm->sg)
1130 return -ENOMEM;
1131 return 0;
1132 }
1133
1134 if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1135 return 0;
1136
1137 return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1138 }
1139
1140 /*
1141 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1142 *
1143 * Unmaps pages of a ttm_tt object from the device address space and
1144 * unpopulates the page array backing it.
1145 */
amdgpu_ttm_tt_unpopulate(struct ttm_device * bdev,struct ttm_tt * ttm)1146 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1147 struct ttm_tt *ttm)
1148 {
1149 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1150 struct amdgpu_device *adev;
1151
1152 if (gtt->userptr) {
1153 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1154 kfree(ttm->sg);
1155 ttm->sg = NULL;
1156 return;
1157 }
1158
1159 if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1160 return;
1161
1162 adev = amdgpu_ttm_adev(bdev);
1163 return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1164 }
1165
1166 /**
1167 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1168 * task
1169 *
1170 * @bo: The ttm_buffer_object to bind this userptr to
1171 * @addr: The address in the current tasks VM space to use
1172 * @flags: Requirements of userptr object.
1173 *
1174 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1175 * to current task
1176 */
amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object * bo,uint64_t addr,uint32_t flags)1177 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1178 uint64_t addr, uint32_t flags)
1179 {
1180 struct amdgpu_ttm_tt *gtt;
1181
1182 if (!bo->ttm) {
1183 /* TODO: We want a separate TTM object type for userptrs */
1184 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1185 if (bo->ttm == NULL)
1186 return -ENOMEM;
1187 }
1188
1189 /* Set TTM_PAGE_FLAG_SG before populate but after create. */
1190 bo->ttm->page_flags |= TTM_PAGE_FLAG_SG;
1191
1192 gtt = (void *)bo->ttm;
1193 gtt->userptr = addr;
1194 gtt->userflags = flags;
1195
1196 if (gtt->usertask)
1197 put_task_struct(gtt->usertask);
1198 gtt->usertask = current->group_leader;
1199 get_task_struct(gtt->usertask);
1200
1201 return 0;
1202 }
1203
1204 /*
1205 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1206 */
amdgpu_ttm_tt_get_usermm(struct ttm_tt * ttm)1207 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1208 {
1209 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1210
1211 if (gtt == NULL)
1212 return NULL;
1213
1214 if (gtt->usertask == NULL)
1215 return NULL;
1216
1217 return gtt->usertask->mm;
1218 }
1219
1220 /*
1221 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1222 * address range for the current task.
1223 *
1224 */
amdgpu_ttm_tt_affect_userptr(struct ttm_tt * ttm,unsigned long start,unsigned long end)1225 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1226 unsigned long end)
1227 {
1228 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1229 unsigned long size;
1230
1231 if (gtt == NULL || !gtt->userptr)
1232 return false;
1233
1234 /* Return false if no part of the ttm_tt object lies within
1235 * the range
1236 */
1237 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1238 if (gtt->userptr > end || gtt->userptr + size <= start)
1239 return false;
1240
1241 return true;
1242 }
1243
1244 /*
1245 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1246 */
amdgpu_ttm_tt_is_userptr(struct ttm_tt * ttm)1247 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1248 {
1249 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1250
1251 if (gtt == NULL || !gtt->userptr)
1252 return false;
1253
1254 return true;
1255 }
1256
1257 /*
1258 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1259 */
amdgpu_ttm_tt_is_readonly(struct ttm_tt * ttm)1260 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1261 {
1262 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1263
1264 if (gtt == NULL)
1265 return false;
1266
1267 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1268 }
1269
1270 /**
1271 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1272 *
1273 * @ttm: The ttm_tt object to compute the flags for
1274 * @mem: The memory registry backing this ttm_tt object
1275 *
1276 * Figure out the flags to use for a VM PDE (Page Directory Entry).
1277 */
amdgpu_ttm_tt_pde_flags(struct ttm_tt * ttm,struct ttm_resource * mem)1278 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1279 {
1280 uint64_t flags = 0;
1281
1282 if (mem && mem->mem_type != TTM_PL_SYSTEM)
1283 flags |= AMDGPU_PTE_VALID;
1284
1285 if (mem && (mem->mem_type == TTM_PL_TT ||
1286 mem->mem_type == AMDGPU_PL_PREEMPT)) {
1287 flags |= AMDGPU_PTE_SYSTEM;
1288
1289 if (ttm->caching == ttm_cached)
1290 flags |= AMDGPU_PTE_SNOOPED;
1291 }
1292
1293 if (mem && mem->mem_type == TTM_PL_VRAM &&
1294 mem->bus.caching == ttm_cached)
1295 flags |= AMDGPU_PTE_SNOOPED;
1296
1297 return flags;
1298 }
1299
1300 /**
1301 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1302 *
1303 * @adev: amdgpu_device pointer
1304 * @ttm: The ttm_tt object to compute the flags for
1305 * @mem: The memory registry backing this ttm_tt object
1306 *
1307 * Figure out the flags to use for a VM PTE (Page Table Entry).
1308 */
amdgpu_ttm_tt_pte_flags(struct amdgpu_device * adev,struct ttm_tt * ttm,struct ttm_resource * mem)1309 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1310 struct ttm_resource *mem)
1311 {
1312 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1313
1314 flags |= adev->gart.gart_pte_flags;
1315 flags |= AMDGPU_PTE_READABLE;
1316
1317 if (!amdgpu_ttm_tt_is_readonly(ttm))
1318 flags |= AMDGPU_PTE_WRITEABLE;
1319
1320 return flags;
1321 }
1322
1323 /*
1324 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1325 * object.
1326 *
1327 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1328 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1329 * it can find space for a new object and by ttm_bo_force_list_clean() which is
1330 * used to clean out a memory space.
1331 */
amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object * bo,const struct ttm_place * place)1332 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1333 const struct ttm_place *place)
1334 {
1335 unsigned long num_pages = bo->resource->num_pages;
1336 struct amdgpu_res_cursor cursor;
1337 struct dma_resv_list *flist;
1338 struct dma_fence *f;
1339 int i;
1340
1341 /* Swapout? */
1342 if (bo->resource->mem_type == TTM_PL_SYSTEM)
1343 return true;
1344
1345 if (bo->type == ttm_bo_type_kernel &&
1346 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1347 return false;
1348
1349 /* If bo is a KFD BO, check if the bo belongs to the current process.
1350 * If true, then return false as any KFD process needs all its BOs to
1351 * be resident to run successfully
1352 */
1353 flist = dma_resv_shared_list(bo->base.resv);
1354 if (flist) {
1355 for (i = 0; i < flist->shared_count; ++i) {
1356 f = rcu_dereference_protected(flist->shared[i],
1357 dma_resv_held(bo->base.resv));
1358 if (amdkfd_fence_check_mm(f, current->mm))
1359 return false;
1360 }
1361 }
1362
1363 switch (bo->resource->mem_type) {
1364 case AMDGPU_PL_PREEMPT:
1365 /* Preemptible BOs don't own system resources managed by the
1366 * driver (pages, VRAM, GART space). They point to resources
1367 * owned by someone else (e.g. pageable memory in user mode
1368 * or a DMABuf). They are used in a preemptible context so we
1369 * can guarantee no deadlocks and good QoS in case of MMU
1370 * notifiers or DMABuf move notifiers from the resource owner.
1371 */
1372 return false;
1373 case TTM_PL_TT:
1374 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1375 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1376 return false;
1377 return true;
1378
1379 case TTM_PL_VRAM:
1380 /* Check each drm MM node individually */
1381 amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT,
1382 &cursor);
1383 while (cursor.remaining) {
1384 if (place->fpfn < PFN_DOWN(cursor.start + cursor.size)
1385 && !(place->lpfn &&
1386 place->lpfn <= PFN_DOWN(cursor.start)))
1387 return true;
1388
1389 amdgpu_res_next(&cursor, cursor.size);
1390 }
1391 return false;
1392
1393 default:
1394 break;
1395 }
1396
1397 return ttm_bo_eviction_valuable(bo, place);
1398 }
1399
amdgpu_ttm_vram_mm_access(struct amdgpu_device * adev,loff_t pos,void * buf,size_t size,bool write)1400 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos,
1401 void *buf, size_t size, bool write)
1402 {
1403 while (size) {
1404 uint64_t aligned_pos = ALIGN_DOWN(pos, 4);
1405 uint64_t bytes = 4 - (pos & 0x3);
1406 uint32_t shift = (pos & 0x3) * 8;
1407 uint32_t mask = 0xffffffff << shift;
1408 uint32_t value = 0;
1409
1410 if (size < bytes) {
1411 mask &= 0xffffffff >> (bytes - size) * 8;
1412 bytes = size;
1413 }
1414
1415 if (mask != 0xffffffff) {
1416 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false);
1417 if (write) {
1418 value &= ~mask;
1419 value |= (*(uint32_t *)buf << shift) & mask;
1420 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true);
1421 } else {
1422 value = (value & mask) >> shift;
1423 memcpy(buf, &value, bytes);
1424 }
1425 } else {
1426 amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write);
1427 }
1428
1429 pos += bytes;
1430 buf += bytes;
1431 size -= bytes;
1432 }
1433 }
1434
1435 /**
1436 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1437 *
1438 * @bo: The buffer object to read/write
1439 * @offset: Offset into buffer object
1440 * @buf: Secondary buffer to write/read from
1441 * @len: Length in bytes of access
1442 * @write: true if writing
1443 *
1444 * This is used to access VRAM that backs a buffer object via MMIO
1445 * access for debugging purposes.
1446 */
amdgpu_ttm_access_memory(struct ttm_buffer_object * bo,unsigned long offset,void * buf,int len,int write)1447 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1448 unsigned long offset, void *buf, int len,
1449 int write)
1450 {
1451 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1452 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1453 struct amdgpu_res_cursor cursor;
1454 int ret = 0;
1455
1456 if (bo->resource->mem_type != TTM_PL_VRAM)
1457 return -EIO;
1458
1459 amdgpu_res_first(bo->resource, offset, len, &cursor);
1460 while (cursor.remaining) {
1461 size_t count, size = cursor.size;
1462 loff_t pos = cursor.start;
1463
1464 count = amdgpu_device_aper_access(adev, pos, buf, size, write);
1465 size -= count;
1466 if (size) {
1467 /* using MM to access rest vram and handle un-aligned address */
1468 pos += count;
1469 buf += count;
1470 amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write);
1471 }
1472
1473 ret += cursor.size;
1474 buf += cursor.size;
1475 amdgpu_res_next(&cursor, cursor.size);
1476 }
1477
1478 return ret;
1479 }
1480
1481 static void
amdgpu_bo_delete_mem_notify(struct ttm_buffer_object * bo)1482 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1483 {
1484 amdgpu_bo_move_notify(bo, false);
1485 }
1486
1487 static struct ttm_device_funcs amdgpu_bo_driver = {
1488 .ttm_tt_create = &amdgpu_ttm_tt_create,
1489 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1490 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1491 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1492 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1493 .evict_flags = &amdgpu_evict_flags,
1494 .move = &amdgpu_bo_move,
1495 .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1496 .release_notify = &amdgpu_bo_release_notify,
1497 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1498 .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1499 .access_memory = &amdgpu_ttm_access_memory,
1500 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1501 };
1502
1503 /*
1504 * Firmware Reservation functions
1505 */
1506 /**
1507 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1508 *
1509 * @adev: amdgpu_device pointer
1510 *
1511 * free fw reserved vram if it has been reserved.
1512 */
amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device * adev)1513 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1514 {
1515 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1516 NULL, &adev->mman.fw_vram_usage_va);
1517 }
1518
1519 /**
1520 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1521 *
1522 * @adev: amdgpu_device pointer
1523 *
1524 * create bo vram reservation from fw.
1525 */
amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device * adev)1526 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1527 {
1528 uint64_t vram_size = adev->gmc.visible_vram_size;
1529
1530 adev->mman.fw_vram_usage_va = NULL;
1531 adev->mman.fw_vram_usage_reserved_bo = NULL;
1532
1533 if (adev->mman.fw_vram_usage_size == 0 ||
1534 adev->mman.fw_vram_usage_size > vram_size)
1535 return 0;
1536
1537 return amdgpu_bo_create_kernel_at(adev,
1538 adev->mman.fw_vram_usage_start_offset,
1539 adev->mman.fw_vram_usage_size,
1540 AMDGPU_GEM_DOMAIN_VRAM,
1541 &adev->mman.fw_vram_usage_reserved_bo,
1542 &adev->mman.fw_vram_usage_va);
1543 }
1544
1545 /*
1546 * Memoy training reservation functions
1547 */
1548
1549 /**
1550 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1551 *
1552 * @adev: amdgpu_device pointer
1553 *
1554 * free memory training reserved vram if it has been reserved.
1555 */
amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device * adev)1556 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1557 {
1558 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1559
1560 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1561 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1562 ctx->c2p_bo = NULL;
1563
1564 return 0;
1565 }
1566
amdgpu_ttm_training_data_block_init(struct amdgpu_device * adev)1567 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1568 {
1569 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1570
1571 memset(ctx, 0, sizeof(*ctx));
1572
1573 ctx->c2p_train_data_offset =
1574 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1575 ctx->p2c_train_data_offset =
1576 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1577 ctx->train_data_size =
1578 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1579
1580 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1581 ctx->train_data_size,
1582 ctx->p2c_train_data_offset,
1583 ctx->c2p_train_data_offset);
1584 }
1585
1586 /*
1587 * reserve TMR memory at the top of VRAM which holds
1588 * IP Discovery data and is protected by PSP.
1589 */
amdgpu_ttm_reserve_tmr(struct amdgpu_device * adev)1590 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1591 {
1592 int ret;
1593 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1594 bool mem_train_support = false;
1595
1596 if (!amdgpu_sriov_vf(adev)) {
1597 if (amdgpu_atomfirmware_mem_training_supported(adev))
1598 mem_train_support = true;
1599 else
1600 DRM_DEBUG("memory training does not support!\n");
1601 }
1602
1603 /*
1604 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1605 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1606 *
1607 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1608 * discovery data and G6 memory training data respectively
1609 */
1610 adev->mman.discovery_tmr_size =
1611 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1612 if (!adev->mman.discovery_tmr_size)
1613 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1614
1615 if (mem_train_support) {
1616 /* reserve vram for mem train according to TMR location */
1617 amdgpu_ttm_training_data_block_init(adev);
1618 ret = amdgpu_bo_create_kernel_at(adev,
1619 ctx->c2p_train_data_offset,
1620 ctx->train_data_size,
1621 AMDGPU_GEM_DOMAIN_VRAM,
1622 &ctx->c2p_bo,
1623 NULL);
1624 if (ret) {
1625 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1626 amdgpu_ttm_training_reserve_vram_fini(adev);
1627 return ret;
1628 }
1629 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1630 }
1631
1632 ret = amdgpu_bo_create_kernel_at(adev,
1633 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1634 adev->mman.discovery_tmr_size,
1635 AMDGPU_GEM_DOMAIN_VRAM,
1636 &adev->mman.discovery_memory,
1637 NULL);
1638 if (ret) {
1639 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1640 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1641 return ret;
1642 }
1643
1644 return 0;
1645 }
1646
1647 /*
1648 * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1649 * gtt/vram related fields.
1650 *
1651 * This initializes all of the memory space pools that the TTM layer
1652 * will need such as the GTT space (system memory mapped to the device),
1653 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1654 * can be mapped per VMID.
1655 */
amdgpu_ttm_init(struct amdgpu_device * adev)1656 int amdgpu_ttm_init(struct amdgpu_device *adev)
1657 {
1658 uint64_t gtt_size;
1659 int r;
1660 u64 vis_vram_limit;
1661
1662 mutex_init(&adev->mman.gtt_window_lock);
1663
1664 /* No others user of address space so set it to 0 */
1665 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1666 adev_to_drm(adev)->anon_inode->i_mapping,
1667 adev_to_drm(adev)->vma_offset_manager,
1668 adev->need_swiotlb,
1669 dma_addressing_limited(adev->dev));
1670 if (r) {
1671 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1672 return r;
1673 }
1674 adev->mman.initialized = true;
1675
1676 /* Initialize VRAM pool with all of VRAM divided into pages */
1677 r = amdgpu_vram_mgr_init(adev);
1678 if (r) {
1679 DRM_ERROR("Failed initializing VRAM heap.\n");
1680 return r;
1681 }
1682
1683 /* Reduce size of CPU-visible VRAM if requested */
1684 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1685 if (amdgpu_vis_vram_limit > 0 &&
1686 vis_vram_limit <= adev->gmc.visible_vram_size)
1687 adev->gmc.visible_vram_size = vis_vram_limit;
1688
1689 /* Change the size here instead of the init above so only lpfn is affected */
1690 amdgpu_ttm_set_buffer_funcs_status(adev, false);
1691 #ifdef CONFIG_64BIT
1692 #ifdef CONFIG_X86
1693 if (adev->gmc.xgmi.connected_to_cpu)
1694 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1695 adev->gmc.visible_vram_size);
1696
1697 else
1698 #endif
1699 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1700 adev->gmc.visible_vram_size);
1701 #endif
1702
1703 /*
1704 *The reserved vram for firmware must be pinned to the specified
1705 *place on the VRAM, so reserve it early.
1706 */
1707 r = amdgpu_ttm_fw_reserve_vram_init(adev);
1708 if (r) {
1709 return r;
1710 }
1711
1712 /*
1713 * only NAVI10 and onwards ASIC support for IP discovery.
1714 * If IP discovery enabled, a block of memory should be
1715 * reserved for IP discovey.
1716 */
1717 if (adev->mman.discovery_bin) {
1718 r = amdgpu_ttm_reserve_tmr(adev);
1719 if (r)
1720 return r;
1721 }
1722
1723 /* allocate memory as required for VGA
1724 * This is used for VGA emulation and pre-OS scanout buffers to
1725 * avoid display artifacts while transitioning between pre-OS
1726 * and driver. */
1727 r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1728 AMDGPU_GEM_DOMAIN_VRAM,
1729 &adev->mman.stolen_vga_memory,
1730 NULL);
1731 if (r)
1732 return r;
1733 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1734 adev->mman.stolen_extended_size,
1735 AMDGPU_GEM_DOMAIN_VRAM,
1736 &adev->mman.stolen_extended_memory,
1737 NULL);
1738 if (r)
1739 return r;
1740 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset,
1741 adev->mman.stolen_reserved_size,
1742 AMDGPU_GEM_DOMAIN_VRAM,
1743 &adev->mman.stolen_reserved_memory,
1744 NULL);
1745 if (r)
1746 return r;
1747
1748 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1749 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1750
1751 /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1752 * or whatever the user passed on module init */
1753 if (amdgpu_gtt_size == -1) {
1754 struct sysinfo si;
1755
1756 si_meminfo(&si);
1757 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1758 adev->gmc.mc_vram_size),
1759 ((uint64_t)si.totalram * si.mem_unit * 3/4));
1760 }
1761 else
1762 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1763
1764 /* Initialize GTT memory pool */
1765 r = amdgpu_gtt_mgr_init(adev, gtt_size);
1766 if (r) {
1767 DRM_ERROR("Failed initializing GTT heap.\n");
1768 return r;
1769 }
1770 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1771 (unsigned)(gtt_size / (1024 * 1024)));
1772
1773 /* Initialize preemptible memory pool */
1774 r = amdgpu_preempt_mgr_init(adev);
1775 if (r) {
1776 DRM_ERROR("Failed initializing PREEMPT heap.\n");
1777 return r;
1778 }
1779
1780 /* Initialize various on-chip memory pools */
1781 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1782 if (r) {
1783 DRM_ERROR("Failed initializing GDS heap.\n");
1784 return r;
1785 }
1786
1787 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1788 if (r) {
1789 DRM_ERROR("Failed initializing gws heap.\n");
1790 return r;
1791 }
1792
1793 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1794 if (r) {
1795 DRM_ERROR("Failed initializing oa heap.\n");
1796 return r;
1797 }
1798
1799 return 0;
1800 }
1801
1802 /*
1803 * amdgpu_ttm_fini - De-initialize the TTM memory pools
1804 */
amdgpu_ttm_fini(struct amdgpu_device * adev)1805 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1806 {
1807 if (!adev->mman.initialized)
1808 return;
1809
1810 amdgpu_ttm_training_reserve_vram_fini(adev);
1811 /* return the stolen vga memory back to VRAM */
1812 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1813 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1814 /* return the IP Discovery TMR memory back to VRAM */
1815 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1816 if (adev->mman.stolen_reserved_size)
1817 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory,
1818 NULL, NULL);
1819 amdgpu_ttm_fw_reserve_vram_fini(adev);
1820
1821 amdgpu_vram_mgr_fini(adev);
1822 amdgpu_gtt_mgr_fini(adev);
1823 amdgpu_preempt_mgr_fini(adev);
1824 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1825 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1826 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1827 ttm_device_fini(&adev->mman.bdev);
1828 adev->mman.initialized = false;
1829 DRM_INFO("amdgpu: ttm finalized\n");
1830 }
1831
1832 /**
1833 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1834 *
1835 * @adev: amdgpu_device pointer
1836 * @enable: true when we can use buffer functions.
1837 *
1838 * Enable/disable use of buffer functions during suspend/resume. This should
1839 * only be called at bootup or when userspace isn't running.
1840 */
amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device * adev,bool enable)1841 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1842 {
1843 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1844 uint64_t size;
1845 int r;
1846
1847 if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
1848 adev->mman.buffer_funcs_enabled == enable)
1849 return;
1850
1851 if (enable) {
1852 struct amdgpu_ring *ring;
1853 struct drm_gpu_scheduler *sched;
1854
1855 ring = adev->mman.buffer_funcs_ring;
1856 sched = &ring->sched;
1857 r = drm_sched_entity_init(&adev->mman.entity,
1858 DRM_SCHED_PRIORITY_KERNEL, &sched,
1859 1, NULL);
1860 if (r) {
1861 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1862 r);
1863 return;
1864 }
1865 } else {
1866 drm_sched_entity_destroy(&adev->mman.entity);
1867 dma_fence_put(man->move);
1868 man->move = NULL;
1869 }
1870
1871 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1872 if (enable)
1873 size = adev->gmc.real_vram_size;
1874 else
1875 size = adev->gmc.visible_vram_size;
1876 man->size = size >> PAGE_SHIFT;
1877 adev->mman.buffer_funcs_enabled = enable;
1878 }
1879
amdgpu_copy_buffer(struct amdgpu_ring * ring,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,struct dma_resv * resv,struct dma_fence ** fence,bool direct_submit,bool vm_needs_flush,bool tmz)1880 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1881 uint64_t dst_offset, uint32_t byte_count,
1882 struct dma_resv *resv,
1883 struct dma_fence **fence, bool direct_submit,
1884 bool vm_needs_flush, bool tmz)
1885 {
1886 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
1887 AMDGPU_IB_POOL_DELAYED;
1888 struct amdgpu_device *adev = ring->adev;
1889 struct amdgpu_job *job;
1890
1891 uint32_t max_bytes;
1892 unsigned num_loops, num_dw;
1893 unsigned i;
1894 int r;
1895
1896 if (!direct_submit && !ring->sched.ready) {
1897 DRM_ERROR("Trying to move memory with ring turned off.\n");
1898 return -EINVAL;
1899 }
1900
1901 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1902 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1903 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
1904
1905 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
1906 if (r)
1907 return r;
1908
1909 if (vm_needs_flush) {
1910 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
1911 adev->gmc.pdb0_bo : adev->gart.bo);
1912 job->vm_needs_flush = true;
1913 }
1914 if (resv) {
1915 r = amdgpu_sync_resv(adev, &job->sync, resv,
1916 AMDGPU_SYNC_ALWAYS,
1917 AMDGPU_FENCE_OWNER_UNDEFINED);
1918 if (r) {
1919 DRM_ERROR("sync failed (%d).\n", r);
1920 goto error_free;
1921 }
1922 }
1923
1924 for (i = 0; i < num_loops; i++) {
1925 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1926
1927 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1928 dst_offset, cur_size_in_bytes, tmz);
1929
1930 src_offset += cur_size_in_bytes;
1931 dst_offset += cur_size_in_bytes;
1932 byte_count -= cur_size_in_bytes;
1933 }
1934
1935 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1936 WARN_ON(job->ibs[0].length_dw > num_dw);
1937 if (direct_submit)
1938 r = amdgpu_job_submit_direct(job, ring, fence);
1939 else
1940 r = amdgpu_job_submit(job, &adev->mman.entity,
1941 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1942 if (r)
1943 goto error_free;
1944
1945 return r;
1946
1947 error_free:
1948 amdgpu_job_free(job);
1949 DRM_ERROR("Error scheduling IBs (%d)\n", r);
1950 return r;
1951 }
1952
amdgpu_fill_buffer(struct amdgpu_bo * bo,uint32_t src_data,struct dma_resv * resv,struct dma_fence ** fence)1953 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1954 uint32_t src_data,
1955 struct dma_resv *resv,
1956 struct dma_fence **fence)
1957 {
1958 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1959 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1960 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1961
1962 struct amdgpu_res_cursor cursor;
1963 unsigned int num_loops, num_dw;
1964 uint64_t num_bytes;
1965
1966 struct amdgpu_job *job;
1967 int r;
1968
1969 if (!adev->mman.buffer_funcs_enabled) {
1970 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1971 return -EINVAL;
1972 }
1973
1974 if (bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT) {
1975 DRM_ERROR("Trying to clear preemptible memory.\n");
1976 return -EINVAL;
1977 }
1978
1979 if (bo->tbo.resource->mem_type == TTM_PL_TT) {
1980 r = amdgpu_ttm_alloc_gart(&bo->tbo);
1981 if (r)
1982 return r;
1983 }
1984
1985 num_bytes = bo->tbo.resource->num_pages << PAGE_SHIFT;
1986 num_loops = 0;
1987
1988 amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor);
1989 while (cursor.remaining) {
1990 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes);
1991 amdgpu_res_next(&cursor, cursor.size);
1992 }
1993 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1994
1995 /* for IB padding */
1996 num_dw += 64;
1997
1998 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
1999 &job);
2000 if (r)
2001 return r;
2002
2003 if (resv) {
2004 r = amdgpu_sync_resv(adev, &job->sync, resv,
2005 AMDGPU_SYNC_ALWAYS,
2006 AMDGPU_FENCE_OWNER_UNDEFINED);
2007 if (r) {
2008 DRM_ERROR("sync failed (%d).\n", r);
2009 goto error_free;
2010 }
2011 }
2012
2013 amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor);
2014 while (cursor.remaining) {
2015 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes);
2016 uint64_t dst_addr = cursor.start;
2017
2018 dst_addr += amdgpu_ttm_domain_start(adev,
2019 bo->tbo.resource->mem_type);
2020 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2021 cur_size);
2022
2023 amdgpu_res_next(&cursor, cur_size);
2024 }
2025
2026 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2027 WARN_ON(job->ibs[0].length_dw > num_dw);
2028 r = amdgpu_job_submit(job, &adev->mman.entity,
2029 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2030 if (r)
2031 goto error_free;
2032
2033 return 0;
2034
2035 error_free:
2036 amdgpu_job_free(job);
2037 return r;
2038 }
2039
2040 /**
2041 * amdgpu_ttm_evict_resources - evict memory buffers
2042 * @adev: amdgpu device object
2043 * @mem_type: evicted BO's memory type
2044 *
2045 * Evicts all @mem_type buffers on the lru list of the memory type.
2046 *
2047 * Returns:
2048 * 0 for success or a negative error code on failure.
2049 */
amdgpu_ttm_evict_resources(struct amdgpu_device * adev,int mem_type)2050 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type)
2051 {
2052 struct ttm_resource_manager *man;
2053
2054 switch (mem_type) {
2055 case TTM_PL_VRAM:
2056 case TTM_PL_TT:
2057 case AMDGPU_PL_GWS:
2058 case AMDGPU_PL_GDS:
2059 case AMDGPU_PL_OA:
2060 man = ttm_manager_type(&adev->mman.bdev, mem_type);
2061 break;
2062 default:
2063 DRM_ERROR("Trying to evict invalid memory type\n");
2064 return -EINVAL;
2065 }
2066
2067 return ttm_resource_manager_evict_all(&adev->mman.bdev, man);
2068 }
2069
2070 #if defined(CONFIG_DEBUG_FS)
2071
amdgpu_mm_vram_table_show(struct seq_file * m,void * unused)2072 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused)
2073 {
2074 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2075 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2076 TTM_PL_VRAM);
2077 struct drm_printer p = drm_seq_file_printer(m);
2078
2079 man->func->debug(man, &p);
2080 return 0;
2081 }
2082
amdgpu_ttm_page_pool_show(struct seq_file * m,void * unused)2083 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2084 {
2085 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2086
2087 return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2088 }
2089
amdgpu_mm_tt_table_show(struct seq_file * m,void * unused)2090 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused)
2091 {
2092 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2093 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2094 TTM_PL_TT);
2095 struct drm_printer p = drm_seq_file_printer(m);
2096
2097 man->func->debug(man, &p);
2098 return 0;
2099 }
2100
amdgpu_mm_gds_table_show(struct seq_file * m,void * unused)2101 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused)
2102 {
2103 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2104 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2105 AMDGPU_PL_GDS);
2106 struct drm_printer p = drm_seq_file_printer(m);
2107
2108 man->func->debug(man, &p);
2109 return 0;
2110 }
2111
amdgpu_mm_gws_table_show(struct seq_file * m,void * unused)2112 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused)
2113 {
2114 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2115 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2116 AMDGPU_PL_GWS);
2117 struct drm_printer p = drm_seq_file_printer(m);
2118
2119 man->func->debug(man, &p);
2120 return 0;
2121 }
2122
amdgpu_mm_oa_table_show(struct seq_file * m,void * unused)2123 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused)
2124 {
2125 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2126 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2127 AMDGPU_PL_OA);
2128 struct drm_printer p = drm_seq_file_printer(m);
2129
2130 man->func->debug(man, &p);
2131 return 0;
2132 }
2133
2134 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table);
2135 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table);
2136 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table);
2137 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table);
2138 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table);
2139 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2140
2141 /*
2142 * amdgpu_ttm_vram_read - Linear read access to VRAM
2143 *
2144 * Accesses VRAM via MMIO for debugging purposes.
2145 */
amdgpu_ttm_vram_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2146 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2147 size_t size, loff_t *pos)
2148 {
2149 struct amdgpu_device *adev = file_inode(f)->i_private;
2150 ssize_t result = 0;
2151
2152 if (size & 0x3 || *pos & 0x3)
2153 return -EINVAL;
2154
2155 if (*pos >= adev->gmc.mc_vram_size)
2156 return -ENXIO;
2157
2158 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2159 while (size) {
2160 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2161 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2162
2163 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2164 if (copy_to_user(buf, value, bytes))
2165 return -EFAULT;
2166
2167 result += bytes;
2168 buf += bytes;
2169 *pos += bytes;
2170 size -= bytes;
2171 }
2172
2173 return result;
2174 }
2175
2176 /*
2177 * amdgpu_ttm_vram_write - Linear write access to VRAM
2178 *
2179 * Accesses VRAM via MMIO for debugging purposes.
2180 */
amdgpu_ttm_vram_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2181 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2182 size_t size, loff_t *pos)
2183 {
2184 struct amdgpu_device *adev = file_inode(f)->i_private;
2185 ssize_t result = 0;
2186 int r;
2187
2188 if (size & 0x3 || *pos & 0x3)
2189 return -EINVAL;
2190
2191 if (*pos >= adev->gmc.mc_vram_size)
2192 return -ENXIO;
2193
2194 while (size) {
2195 uint32_t value;
2196
2197 if (*pos >= adev->gmc.mc_vram_size)
2198 return result;
2199
2200 r = get_user(value, (uint32_t *)buf);
2201 if (r)
2202 return r;
2203
2204 amdgpu_device_mm_access(adev, *pos, &value, 4, true);
2205
2206 result += 4;
2207 buf += 4;
2208 *pos += 4;
2209 size -= 4;
2210 }
2211
2212 return result;
2213 }
2214
2215 static const struct file_operations amdgpu_ttm_vram_fops = {
2216 .owner = THIS_MODULE,
2217 .read = amdgpu_ttm_vram_read,
2218 .write = amdgpu_ttm_vram_write,
2219 .llseek = default_llseek,
2220 };
2221
2222 /*
2223 * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2224 *
2225 * This function is used to read memory that has been mapped to the
2226 * GPU and the known addresses are not physical addresses but instead
2227 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2228 */
amdgpu_iomem_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2229 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2230 size_t size, loff_t *pos)
2231 {
2232 struct amdgpu_device *adev = file_inode(f)->i_private;
2233 struct iommu_domain *dom;
2234 ssize_t result = 0;
2235 int r;
2236
2237 /* retrieve the IOMMU domain if any for this device */
2238 dom = iommu_get_domain_for_dev(adev->dev);
2239
2240 while (size) {
2241 phys_addr_t addr = *pos & PAGE_MASK;
2242 loff_t off = *pos & ~PAGE_MASK;
2243 size_t bytes = PAGE_SIZE - off;
2244 unsigned long pfn;
2245 struct page *p;
2246 void *ptr;
2247
2248 bytes = bytes < size ? bytes : size;
2249
2250 /* Translate the bus address to a physical address. If
2251 * the domain is NULL it means there is no IOMMU active
2252 * and the address translation is the identity
2253 */
2254 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2255
2256 pfn = addr >> PAGE_SHIFT;
2257 if (!pfn_valid(pfn))
2258 return -EPERM;
2259
2260 p = pfn_to_page(pfn);
2261 if (p->mapping != adev->mman.bdev.dev_mapping)
2262 return -EPERM;
2263
2264 ptr = kmap(p);
2265 r = copy_to_user(buf, ptr + off, bytes);
2266 kunmap(p);
2267 if (r)
2268 return -EFAULT;
2269
2270 size -= bytes;
2271 *pos += bytes;
2272 result += bytes;
2273 }
2274
2275 return result;
2276 }
2277
2278 /*
2279 * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2280 *
2281 * This function is used to write memory that has been mapped to the
2282 * GPU and the known addresses are not physical addresses but instead
2283 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2284 */
amdgpu_iomem_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2285 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2286 size_t size, loff_t *pos)
2287 {
2288 struct amdgpu_device *adev = file_inode(f)->i_private;
2289 struct iommu_domain *dom;
2290 ssize_t result = 0;
2291 int r;
2292
2293 dom = iommu_get_domain_for_dev(adev->dev);
2294
2295 while (size) {
2296 phys_addr_t addr = *pos & PAGE_MASK;
2297 loff_t off = *pos & ~PAGE_MASK;
2298 size_t bytes = PAGE_SIZE - off;
2299 unsigned long pfn;
2300 struct page *p;
2301 void *ptr;
2302
2303 bytes = bytes < size ? bytes : size;
2304
2305 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2306
2307 pfn = addr >> PAGE_SHIFT;
2308 if (!pfn_valid(pfn))
2309 return -EPERM;
2310
2311 p = pfn_to_page(pfn);
2312 if (p->mapping != adev->mman.bdev.dev_mapping)
2313 return -EPERM;
2314
2315 ptr = kmap(p);
2316 r = copy_from_user(ptr + off, buf, bytes);
2317 kunmap(p);
2318 if (r)
2319 return -EFAULT;
2320
2321 size -= bytes;
2322 *pos += bytes;
2323 result += bytes;
2324 }
2325
2326 return result;
2327 }
2328
2329 static const struct file_operations amdgpu_ttm_iomem_fops = {
2330 .owner = THIS_MODULE,
2331 .read = amdgpu_iomem_read,
2332 .write = amdgpu_iomem_write,
2333 .llseek = default_llseek
2334 };
2335
2336 #endif
2337
amdgpu_ttm_debugfs_init(struct amdgpu_device * adev)2338 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2339 {
2340 #if defined(CONFIG_DEBUG_FS)
2341 struct drm_minor *minor = adev_to_drm(adev)->primary;
2342 struct dentry *root = minor->debugfs_root;
2343
2344 debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2345 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2346 debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2347 &amdgpu_ttm_iomem_fops);
2348 debugfs_create_file("amdgpu_vram_mm", 0444, root, adev,
2349 &amdgpu_mm_vram_table_fops);
2350 debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev,
2351 &amdgpu_mm_tt_table_fops);
2352 debugfs_create_file("amdgpu_gds_mm", 0444, root, adev,
2353 &amdgpu_mm_gds_table_fops);
2354 debugfs_create_file("amdgpu_gws_mm", 0444, root, adev,
2355 &amdgpu_mm_gws_table_fops);
2356 debugfs_create_file("amdgpu_oa_mm", 0444, root, adev,
2357 &amdgpu_mm_oa_table_fops);
2358 debugfs_create_file("ttm_page_pool", 0444, root, adev,
2359 &amdgpu_ttm_page_pool_fops);
2360 #endif
2361 }
2362