1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 /* forward declaration */ 46 struct aux_payload; 47 48 #define DC_VER "3.2.149" 49 50 #define MAX_SURFACES 3 51 #define MAX_PLANES 6 52 #define MAX_STREAMS 6 53 #define MAX_SINKS_PER_LINK 4 54 #define MIN_VIEWPORT_SIZE 12 55 #define MAX_NUM_EDP 2 56 57 /******************************************************************************* 58 * Display Core Interfaces 59 ******************************************************************************/ 60 struct dc_versions { 61 const char *dc_ver; 62 struct dmcu_version dmcu_version; 63 }; 64 65 enum dp_protocol_version { 66 DP_VERSION_1_4, 67 }; 68 69 enum dc_plane_type { 70 DC_PLANE_TYPE_INVALID, 71 DC_PLANE_TYPE_DCE_RGB, 72 DC_PLANE_TYPE_DCE_UNDERLAY, 73 DC_PLANE_TYPE_DCN_UNIVERSAL, 74 }; 75 76 struct dc_plane_cap { 77 enum dc_plane_type type; 78 uint32_t blends_with_above : 1; 79 uint32_t blends_with_below : 1; 80 uint32_t per_pixel_alpha : 1; 81 struct { 82 uint32_t argb8888 : 1; 83 uint32_t nv12 : 1; 84 uint32_t fp16 : 1; 85 uint32_t p010 : 1; 86 uint32_t ayuv : 1; 87 } pixel_format_support; 88 // max upscaling factor x1000 89 // upscaling factors are always >= 1 90 // for example, 1080p -> 8K is 4.0, or 4000 raw value 91 struct { 92 uint32_t argb8888; 93 uint32_t nv12; 94 uint32_t fp16; 95 } max_upscale_factor; 96 // max downscale factor x1000 97 // downscale factors are always <= 1 98 // for example, 8K -> 1080p is 0.25, or 250 raw value 99 struct { 100 uint32_t argb8888; 101 uint32_t nv12; 102 uint32_t fp16; 103 } max_downscale_factor; 104 // minimal width/height 105 uint32_t min_width; 106 uint32_t min_height; 107 }; 108 109 // Color management caps (DPP and MPC) 110 struct rom_curve_caps { 111 uint16_t srgb : 1; 112 uint16_t bt2020 : 1; 113 uint16_t gamma2_2 : 1; 114 uint16_t pq : 1; 115 uint16_t hlg : 1; 116 }; 117 118 struct dpp_color_caps { 119 uint16_t dcn_arch : 1; // all DCE generations treated the same 120 // input lut is different than most LUTs, just plain 256-entry lookup 121 uint16_t input_lut_shared : 1; // shared with DGAM 122 uint16_t icsc : 1; 123 uint16_t dgam_ram : 1; 124 uint16_t post_csc : 1; // before gamut remap 125 uint16_t gamma_corr : 1; 126 127 // hdr_mult and gamut remap always available in DPP (in that order) 128 // 3d lut implies shaper LUT, 129 // it may be shared with MPC - check MPC:shared_3d_lut flag 130 uint16_t hw_3d_lut : 1; 131 uint16_t ogam_ram : 1; // blnd gam 132 uint16_t ocsc : 1; 133 uint16_t dgam_rom_for_yuv : 1; 134 struct rom_curve_caps dgam_rom_caps; 135 struct rom_curve_caps ogam_rom_caps; 136 }; 137 138 struct mpc_color_caps { 139 uint16_t gamut_remap : 1; 140 uint16_t ogam_ram : 1; 141 uint16_t ocsc : 1; 142 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 143 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 144 145 struct rom_curve_caps ogam_rom_caps; 146 }; 147 148 struct dc_color_caps { 149 struct dpp_color_caps dpp; 150 struct mpc_color_caps mpc; 151 }; 152 153 struct dc_caps { 154 uint32_t max_streams; 155 uint32_t max_links; 156 uint32_t max_audios; 157 uint32_t max_slave_planes; 158 uint32_t max_slave_yuv_planes; 159 uint32_t max_slave_rgb_planes; 160 uint32_t max_planes; 161 uint32_t max_downscale_ratio; 162 uint32_t i2c_speed_in_khz; 163 uint32_t i2c_speed_in_khz_hdcp; 164 uint32_t dmdata_alloc_size; 165 unsigned int max_cursor_size; 166 unsigned int max_video_width; 167 /* 168 * max video plane width that can be safely assumed to be always 169 * supported by single DPP pipe. 170 */ 171 unsigned int max_optimizable_video_width; 172 unsigned int min_horizontal_blanking_period; 173 int linear_pitch_alignment; 174 bool dcc_const_color; 175 bool dynamic_audio; 176 bool is_apu; 177 bool dual_link_dvi; 178 bool post_blend_color_processing; 179 bool force_dp_tps4_for_cp2520; 180 bool disable_dp_clk_share; 181 bool psp_setup_panel_mode; 182 bool extended_aux_timeout_support; 183 bool dmcub_support; 184 uint32_t num_of_internal_disp; 185 enum dp_protocol_version max_dp_protocol_version; 186 unsigned int mall_size_per_mem_channel; 187 unsigned int mall_size_total; 188 unsigned int cursor_cache_size; 189 struct dc_plane_cap planes[MAX_PLANES]; 190 struct dc_color_caps color; 191 bool vbios_lttpr_aware; 192 bool vbios_lttpr_enable; 193 uint32_t max_otg_num; 194 }; 195 196 struct dc_bug_wa { 197 bool no_connect_phy_config; 198 bool dedcn20_305_wa; 199 bool skip_clock_update; 200 bool lt_early_cr_pattern; 201 }; 202 203 struct dc_dcc_surface_param { 204 struct dc_size surface_size; 205 enum surface_pixel_format format; 206 enum swizzle_mode_values swizzle_mode; 207 enum dc_scan_direction scan; 208 }; 209 210 struct dc_dcc_setting { 211 unsigned int max_compressed_blk_size; 212 unsigned int max_uncompressed_blk_size; 213 bool independent_64b_blks; 214 #if defined(CONFIG_DRM_AMD_DC_DCN) 215 //These bitfields to be used starting with DCN 3.0 216 struct { 217 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 218 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 219 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 220 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 221 } dcc_controls; 222 #endif 223 }; 224 225 struct dc_surface_dcc_cap { 226 union { 227 struct { 228 struct dc_dcc_setting rgb; 229 } grph; 230 231 struct { 232 struct dc_dcc_setting luma; 233 struct dc_dcc_setting chroma; 234 } video; 235 }; 236 237 bool capable; 238 bool const_color_support; 239 }; 240 241 struct dc_static_screen_params { 242 struct { 243 bool force_trigger; 244 bool cursor_update; 245 bool surface_update; 246 bool overlay_update; 247 } triggers; 248 unsigned int num_frames; 249 }; 250 251 252 /* Surface update type is used by dc_update_surfaces_and_stream 253 * The update type is determined at the very beginning of the function based 254 * on parameters passed in and decides how much programming (or updating) is 255 * going to be done during the call. 256 * 257 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 258 * logical calculations or hardware register programming. This update MUST be 259 * ISR safe on windows. Currently fast update will only be used to flip surface 260 * address. 261 * 262 * UPDATE_TYPE_MED is used for slower updates which require significant hw 263 * re-programming however do not affect bandwidth consumption or clock 264 * requirements. At present, this is the level at which front end updates 265 * that do not require us to run bw_calcs happen. These are in/out transfer func 266 * updates, viewport offset changes, recout size changes and pixel depth changes. 267 * This update can be done at ISR, but we want to minimize how often this happens. 268 * 269 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 270 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 271 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 272 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 273 * a full update. This cannot be done at ISR level and should be a rare event. 274 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 275 * underscan we don't expect to see this call at all. 276 */ 277 278 enum surface_update_type { 279 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 280 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 281 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 282 }; 283 284 /* Forward declaration*/ 285 struct dc; 286 struct dc_plane_state; 287 struct dc_state; 288 289 290 struct dc_cap_funcs { 291 bool (*get_dcc_compression_cap)(const struct dc *dc, 292 const struct dc_dcc_surface_param *input, 293 struct dc_surface_dcc_cap *output); 294 }; 295 296 struct link_training_settings; 297 298 299 /* Structure to hold configuration flags set by dm at dc creation. */ 300 struct dc_config { 301 bool gpu_vm_support; 302 bool disable_disp_pll_sharing; 303 bool fbc_support; 304 bool disable_fractional_pwm; 305 bool allow_seamless_boot_optimization; 306 bool power_down_display_on_boot; 307 bool edp_not_connected; 308 bool edp_no_power_sequencing; 309 bool force_enum_edp; 310 bool forced_clocks; 311 bool allow_lttpr_non_transparent_mode; 312 bool multi_mon_pp_mclk_switch; 313 bool disable_dmcu; 314 bool enable_4to1MPC; 315 bool allow_edp_hotplug_detection; 316 #if defined(CONFIG_DRM_AMD_DC_DCN) 317 bool clamp_min_dcfclk; 318 #endif 319 uint64_t vblank_alignment_dto_params; 320 uint8_t vblank_alignment_max_frame_time_diff; 321 bool is_asymmetric_memory; 322 bool is_single_rank_dimm; 323 }; 324 325 enum visual_confirm { 326 VISUAL_CONFIRM_DISABLE = 0, 327 VISUAL_CONFIRM_SURFACE = 1, 328 VISUAL_CONFIRM_HDR = 2, 329 VISUAL_CONFIRM_MPCTREE = 4, 330 VISUAL_CONFIRM_PSR = 5, 331 VISUAL_CONFIRM_SWIZZLE = 9, 332 }; 333 334 enum dcc_option { 335 DCC_ENABLE = 0, 336 DCC_DISABLE = 1, 337 DCC_HALF_REQ_DISALBE = 2, 338 }; 339 340 enum pipe_split_policy { 341 MPC_SPLIT_DYNAMIC = 0, 342 MPC_SPLIT_AVOID = 1, 343 MPC_SPLIT_AVOID_MULT_DISP = 2, 344 }; 345 346 enum wm_report_mode { 347 WM_REPORT_DEFAULT = 0, 348 WM_REPORT_OVERRIDE = 1, 349 }; 350 enum dtm_pstate{ 351 dtm_level_p0 = 0,/*highest voltage*/ 352 dtm_level_p1, 353 dtm_level_p2, 354 dtm_level_p3, 355 dtm_level_p4,/*when active_display_count = 0*/ 356 }; 357 358 enum dcn_pwr_state { 359 DCN_PWR_STATE_UNKNOWN = -1, 360 DCN_PWR_STATE_MISSION_MODE = 0, 361 DCN_PWR_STATE_LOW_POWER = 3, 362 }; 363 364 #if defined(CONFIG_DRM_AMD_DC_DCN) 365 enum dcn_zstate_support_state { 366 DCN_ZSTATE_SUPPORT_UNKNOWN, 367 DCN_ZSTATE_SUPPORT_ALLOW, 368 DCN_ZSTATE_SUPPORT_DISALLOW, 369 }; 370 #endif 371 /* 372 * For any clocks that may differ per pipe 373 * only the max is stored in this structure 374 */ 375 struct dc_clocks { 376 int dispclk_khz; 377 int actual_dispclk_khz; 378 int dppclk_khz; 379 int actual_dppclk_khz; 380 int disp_dpp_voltage_level_khz; 381 int dcfclk_khz; 382 int socclk_khz; 383 int dcfclk_deep_sleep_khz; 384 int fclk_khz; 385 int phyclk_khz; 386 int dramclk_khz; 387 bool p_state_change_support; 388 #if defined(CONFIG_DRM_AMD_DC_DCN) 389 enum dcn_zstate_support_state zstate_support; 390 bool dtbclk_en; 391 #endif 392 enum dcn_pwr_state pwr_state; 393 /* 394 * Elements below are not compared for the purposes of 395 * optimization required 396 */ 397 bool prev_p_state_change_support; 398 enum dtm_pstate dtm_level; 399 int max_supported_dppclk_khz; 400 int max_supported_dispclk_khz; 401 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 402 int bw_dispclk_khz; 403 }; 404 405 struct dc_bw_validation_profile { 406 bool enable; 407 408 unsigned long long total_ticks; 409 unsigned long long voltage_level_ticks; 410 unsigned long long watermark_ticks; 411 unsigned long long rq_dlg_ticks; 412 413 unsigned long long total_count; 414 unsigned long long skip_fast_count; 415 unsigned long long skip_pass_count; 416 unsigned long long skip_fail_count; 417 }; 418 419 #define BW_VAL_TRACE_SETUP() \ 420 unsigned long long end_tick = 0; \ 421 unsigned long long voltage_level_tick = 0; \ 422 unsigned long long watermark_tick = 0; \ 423 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 424 dm_get_timestamp(dc->ctx) : 0 425 426 #define BW_VAL_TRACE_COUNT() \ 427 if (dc->debug.bw_val_profile.enable) \ 428 dc->debug.bw_val_profile.total_count++ 429 430 #define BW_VAL_TRACE_SKIP(status) \ 431 if (dc->debug.bw_val_profile.enable) { \ 432 if (!voltage_level_tick) \ 433 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 434 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 435 } 436 437 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 438 if (dc->debug.bw_val_profile.enable) \ 439 voltage_level_tick = dm_get_timestamp(dc->ctx) 440 441 #define BW_VAL_TRACE_END_WATERMARKS() \ 442 if (dc->debug.bw_val_profile.enable) \ 443 watermark_tick = dm_get_timestamp(dc->ctx) 444 445 #define BW_VAL_TRACE_FINISH() \ 446 if (dc->debug.bw_val_profile.enable) { \ 447 end_tick = dm_get_timestamp(dc->ctx); \ 448 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 449 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 450 if (watermark_tick) { \ 451 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 452 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 453 } \ 454 } 455 456 union mem_low_power_enable_options { 457 struct { 458 bool vga: 1; 459 bool i2c: 1; 460 bool dmcu: 1; 461 bool dscl: 1; 462 bool cm: 1; 463 bool mpc: 1; 464 bool optc: 1; 465 } bits; 466 uint32_t u32All; 467 }; 468 469 struct dc_debug_data { 470 uint32_t ltFailCount; 471 uint32_t i2cErrorCount; 472 uint32_t auxErrorCount; 473 }; 474 475 struct dc_phy_addr_space_config { 476 struct { 477 uint64_t start_addr; 478 uint64_t end_addr; 479 uint64_t fb_top; 480 uint64_t fb_offset; 481 uint64_t fb_base; 482 uint64_t agp_top; 483 uint64_t agp_bot; 484 uint64_t agp_base; 485 } system_aperture; 486 487 struct { 488 uint64_t page_table_start_addr; 489 uint64_t page_table_end_addr; 490 uint64_t page_table_base_addr; 491 bool base_addr_is_mc_addr; 492 } gart_config; 493 494 bool valid; 495 bool is_hvm_enabled; 496 uint64_t page_table_default_page_addr; 497 }; 498 499 struct dc_virtual_addr_space_config { 500 uint64_t page_table_base_addr; 501 uint64_t page_table_start_addr; 502 uint64_t page_table_end_addr; 503 uint32_t page_table_block_size_in_bytes; 504 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 505 }; 506 507 struct dc_bounding_box_overrides { 508 int sr_exit_time_ns; 509 int sr_enter_plus_exit_time_ns; 510 int urgent_latency_ns; 511 int percent_of_ideal_drambw; 512 int dram_clock_change_latency_ns; 513 int dummy_clock_change_latency_ns; 514 /* This forces a hard min on the DCFCLK we use 515 * for DML. Unlike the debug option for forcing 516 * DCFCLK, this override affects watermark calculations 517 */ 518 int min_dcfclk_mhz; 519 }; 520 521 struct dc_state; 522 struct resource_pool; 523 struct dce_hwseq; 524 525 struct dc_debug_options { 526 bool native422_support; 527 bool disable_dsc; 528 enum visual_confirm visual_confirm; 529 bool sanity_checks; 530 bool max_disp_clk; 531 bool surface_trace; 532 bool timing_trace; 533 bool clock_trace; 534 bool validation_trace; 535 bool bandwidth_calcs_trace; 536 int max_downscale_src_width; 537 538 /* stutter efficiency related */ 539 bool disable_stutter; 540 bool use_max_lb; 541 enum dcc_option disable_dcc; 542 enum pipe_split_policy pipe_split_policy; 543 bool force_single_disp_pipe_split; 544 bool voltage_align_fclk; 545 bool disable_min_fclk; 546 547 bool disable_dfs_bypass; 548 bool disable_dpp_power_gate; 549 bool disable_hubp_power_gate; 550 bool disable_dsc_power_gate; 551 int dsc_min_slice_height_override; 552 int dsc_bpp_increment_div; 553 bool disable_pplib_wm_range; 554 enum wm_report_mode pplib_wm_report_mode; 555 unsigned int min_disp_clk_khz; 556 unsigned int min_dpp_clk_khz; 557 int sr_exit_time_dpm0_ns; 558 int sr_enter_plus_exit_time_dpm0_ns; 559 int sr_exit_time_ns; 560 int sr_enter_plus_exit_time_ns; 561 int urgent_latency_ns; 562 uint32_t underflow_assert_delay_us; 563 int percent_of_ideal_drambw; 564 int dram_clock_change_latency_ns; 565 bool optimized_watermark; 566 int always_scale; 567 bool disable_pplib_clock_request; 568 bool disable_clock_gate; 569 bool disable_mem_low_power; 570 #if defined(CONFIG_DRM_AMD_DC_DCN) 571 bool pstate_enabled; 572 #endif 573 bool disable_dmcu; 574 bool disable_psr; 575 bool force_abm_enable; 576 bool disable_stereo_support; 577 bool vsr_support; 578 bool performance_trace; 579 bool az_endpoint_mute_only; 580 bool always_use_regamma; 581 bool recovery_enabled; 582 bool avoid_vbios_exec_table; 583 bool scl_reset_length10; 584 bool hdmi20_disable; 585 bool skip_detection_link_training; 586 uint32_t edid_read_retry_times; 587 bool remove_disconnect_edp; 588 unsigned int force_odm_combine; //bit vector based on otg inst 589 #if defined(CONFIG_DRM_AMD_DC_DCN) 590 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 591 bool disable_z9_mpc; 592 #endif 593 unsigned int force_fclk_khz; 594 bool enable_tri_buf; 595 bool dmub_offload_enabled; 596 bool dmcub_emulation; 597 #if defined(CONFIG_DRM_AMD_DC_DCN) 598 bool disable_idle_power_optimizations; 599 unsigned int mall_size_override; 600 unsigned int mall_additional_timer_percent; 601 bool mall_error_as_fatal; 602 #endif 603 bool dmub_command_table; /* for testing only */ 604 struct dc_bw_validation_profile bw_val_profile; 605 bool disable_fec; 606 bool disable_48mhz_pwrdwn; 607 /* This forces a hard min on the DCFCLK requested to SMU/PP 608 * watermarks are not affected. 609 */ 610 unsigned int force_min_dcfclk_mhz; 611 #if defined(CONFIG_DRM_AMD_DC_DCN) 612 int dwb_fi_phase; 613 #endif 614 bool disable_timing_sync; 615 bool cm_in_bypass; 616 int force_clock_mode;/*every mode change.*/ 617 618 bool disable_dram_clock_change_vactive_support; 619 bool validate_dml_output; 620 bool enable_dmcub_surface_flip; 621 bool usbc_combo_phy_reset_wa; 622 bool enable_dram_clock_change_one_display_vactive; 623 union mem_low_power_enable_options enable_mem_low_power; 624 bool force_vblank_alignment; 625 626 /* Enable dmub aux for legacy ddc */ 627 bool enable_dmub_aux_for_legacy_ddc; 628 bool optimize_edp_link_rate; /* eDP ILR */ 629 /* force enable edp FEC */ 630 bool force_enable_edp_fec; 631 /* FEC/PSR1 sequence enable delay in 100us */ 632 uint8_t fec_enable_delay_in100us; 633 #if defined(CONFIG_DRM_AMD_DC_DCN) 634 bool disable_z10; 635 bool enable_sw_cntl_psr; 636 #endif 637 }; 638 639 struct gpu_info_soc_bounding_box_v1_0; 640 struct dc { 641 struct dc_debug_options debug; 642 struct dc_versions versions; 643 struct dc_caps caps; 644 struct dc_cap_funcs cap_funcs; 645 struct dc_config config; 646 struct dc_bounding_box_overrides bb_overrides; 647 struct dc_bug_wa work_arounds; 648 struct dc_context *ctx; 649 struct dc_phy_addr_space_config vm_pa_config; 650 651 uint8_t link_count; 652 struct dc_link *links[MAX_PIPES * 2]; 653 654 struct dc_state *current_state; 655 struct resource_pool *res_pool; 656 657 struct clk_mgr *clk_mgr; 658 659 /* Display Engine Clock levels */ 660 struct dm_pp_clock_levels sclk_lvls; 661 662 /* Inputs into BW and WM calculations. */ 663 struct bw_calcs_dceip *bw_dceip; 664 struct bw_calcs_vbios *bw_vbios; 665 #ifdef CONFIG_DRM_AMD_DC_DCN 666 struct dcn_soc_bounding_box *dcn_soc; 667 struct dcn_ip_params *dcn_ip; 668 struct display_mode_lib dml; 669 #endif 670 671 /* HW functions */ 672 struct hw_sequencer_funcs hwss; 673 struct dce_hwseq *hwseq; 674 675 /* Require to optimize clocks and bandwidth for added/removed planes */ 676 bool optimized_required; 677 bool wm_optimized_required; 678 #if defined(CONFIG_DRM_AMD_DC_DCN) 679 bool idle_optimizations_allowed; 680 #endif 681 682 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 683 684 /* FBC compressor */ 685 struct compressor *fbc_compressor; 686 687 struct dc_debug_data debug_data; 688 struct dpcd_vendor_signature vendor_signature; 689 690 const char *build_id; 691 struct vm_helper *vm_helper; 692 }; 693 694 enum frame_buffer_mode { 695 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 696 FRAME_BUFFER_MODE_ZFB_ONLY, 697 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 698 } ; 699 700 struct dchub_init_data { 701 int64_t zfb_phys_addr_base; 702 int64_t zfb_mc_base_addr; 703 uint64_t zfb_size_in_byte; 704 enum frame_buffer_mode fb_mode; 705 bool dchub_initialzied; 706 bool dchub_info_valid; 707 }; 708 709 struct dc_init_data { 710 struct hw_asic_id asic_id; 711 void *driver; /* ctx */ 712 struct cgs_device *cgs_device; 713 struct dc_bounding_box_overrides bb_overrides; 714 715 int num_virtual_links; 716 /* 717 * If 'vbios_override' not NULL, it will be called instead 718 * of the real VBIOS. Intended use is Diagnostics on FPGA. 719 */ 720 struct dc_bios *vbios_override; 721 enum dce_environment dce_environment; 722 723 struct dmub_offload_funcs *dmub_if; 724 struct dc_reg_helper_state *dmub_offload; 725 726 struct dc_config flags; 727 uint64_t log_mask; 728 729 struct dpcd_vendor_signature vendor_signature; 730 #if defined(CONFIG_DRM_AMD_DC_DCN) 731 bool force_smu_not_present; 732 #endif 733 }; 734 735 struct dc_callback_init { 736 #ifdef CONFIG_DRM_AMD_DC_HDCP 737 struct cp_psp cp_psp; 738 #else 739 uint8_t reserved; 740 #endif 741 }; 742 743 struct dc *dc_create(const struct dc_init_data *init_params); 744 void dc_hardware_init(struct dc *dc); 745 746 int dc_get_vmid_use_vector(struct dc *dc); 747 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 748 /* Returns the number of vmids supported */ 749 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 750 void dc_init_callbacks(struct dc *dc, 751 const struct dc_callback_init *init_params); 752 void dc_deinit_callbacks(struct dc *dc); 753 void dc_destroy(struct dc **dc); 754 755 /******************************************************************************* 756 * Surface Interfaces 757 ******************************************************************************/ 758 759 enum { 760 TRANSFER_FUNC_POINTS = 1025 761 }; 762 763 struct dc_hdr_static_metadata { 764 /* display chromaticities and white point in units of 0.00001 */ 765 unsigned int chromaticity_green_x; 766 unsigned int chromaticity_green_y; 767 unsigned int chromaticity_blue_x; 768 unsigned int chromaticity_blue_y; 769 unsigned int chromaticity_red_x; 770 unsigned int chromaticity_red_y; 771 unsigned int chromaticity_white_point_x; 772 unsigned int chromaticity_white_point_y; 773 774 uint32_t min_luminance; 775 uint32_t max_luminance; 776 uint32_t maximum_content_light_level; 777 uint32_t maximum_frame_average_light_level; 778 }; 779 780 enum dc_transfer_func_type { 781 TF_TYPE_PREDEFINED, 782 TF_TYPE_DISTRIBUTED_POINTS, 783 TF_TYPE_BYPASS, 784 TF_TYPE_HWPWL 785 }; 786 787 struct dc_transfer_func_distributed_points { 788 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 789 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 790 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 791 792 uint16_t end_exponent; 793 uint16_t x_point_at_y1_red; 794 uint16_t x_point_at_y1_green; 795 uint16_t x_point_at_y1_blue; 796 }; 797 798 enum dc_transfer_func_predefined { 799 TRANSFER_FUNCTION_SRGB, 800 TRANSFER_FUNCTION_BT709, 801 TRANSFER_FUNCTION_PQ, 802 TRANSFER_FUNCTION_LINEAR, 803 TRANSFER_FUNCTION_UNITY, 804 TRANSFER_FUNCTION_HLG, 805 TRANSFER_FUNCTION_HLG12, 806 TRANSFER_FUNCTION_GAMMA22, 807 TRANSFER_FUNCTION_GAMMA24, 808 TRANSFER_FUNCTION_GAMMA26 809 }; 810 811 812 struct dc_transfer_func { 813 struct kref refcount; 814 enum dc_transfer_func_type type; 815 enum dc_transfer_func_predefined tf; 816 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 817 uint32_t sdr_ref_white_level; 818 union { 819 struct pwl_params pwl; 820 struct dc_transfer_func_distributed_points tf_pts; 821 }; 822 }; 823 824 825 union dc_3dlut_state { 826 struct { 827 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 828 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 829 uint32_t rmu_mux_num:3; /*index of mux to use*/ 830 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 831 uint32_t mpc_rmu1_mux:4; 832 uint32_t mpc_rmu2_mux:4; 833 uint32_t reserved:15; 834 } bits; 835 uint32_t raw; 836 }; 837 838 839 struct dc_3dlut { 840 struct kref refcount; 841 struct tetrahedral_params lut_3d; 842 struct fixed31_32 hdr_multiplier; 843 union dc_3dlut_state state; 844 }; 845 /* 846 * This structure is filled in by dc_surface_get_status and contains 847 * the last requested address and the currently active address so the called 848 * can determine if there are any outstanding flips 849 */ 850 struct dc_plane_status { 851 struct dc_plane_address requested_address; 852 struct dc_plane_address current_address; 853 bool is_flip_pending; 854 bool is_right_eye; 855 }; 856 857 union surface_update_flags { 858 859 struct { 860 uint32_t addr_update:1; 861 /* Medium updates */ 862 uint32_t dcc_change:1; 863 uint32_t color_space_change:1; 864 uint32_t horizontal_mirror_change:1; 865 uint32_t per_pixel_alpha_change:1; 866 uint32_t global_alpha_change:1; 867 uint32_t hdr_mult:1; 868 uint32_t rotation_change:1; 869 uint32_t swizzle_change:1; 870 uint32_t scaling_change:1; 871 uint32_t position_change:1; 872 uint32_t in_transfer_func_change:1; 873 uint32_t input_csc_change:1; 874 uint32_t coeff_reduction_change:1; 875 uint32_t output_tf_change:1; 876 uint32_t pixel_format_change:1; 877 uint32_t plane_size_change:1; 878 uint32_t gamut_remap_change:1; 879 880 /* Full updates */ 881 uint32_t new_plane:1; 882 uint32_t bpp_change:1; 883 uint32_t gamma_change:1; 884 uint32_t bandwidth_change:1; 885 uint32_t clock_change:1; 886 uint32_t stereo_format_change:1; 887 uint32_t full_update:1; 888 } bits; 889 890 uint32_t raw; 891 }; 892 893 struct dc_plane_state { 894 struct dc_plane_address address; 895 struct dc_plane_flip_time time; 896 bool triplebuffer_flips; 897 struct scaling_taps scaling_quality; 898 struct rect src_rect; 899 struct rect dst_rect; 900 struct rect clip_rect; 901 902 struct plane_size plane_size; 903 union dc_tiling_info tiling_info; 904 905 struct dc_plane_dcc_param dcc; 906 907 struct dc_gamma *gamma_correction; 908 struct dc_transfer_func *in_transfer_func; 909 struct dc_bias_and_scale *bias_and_scale; 910 struct dc_csc_transform input_csc_color_matrix; 911 struct fixed31_32 coeff_reduction_factor; 912 struct fixed31_32 hdr_mult; 913 struct colorspace_transform gamut_remap_matrix; 914 915 // TODO: No longer used, remove 916 struct dc_hdr_static_metadata hdr_static_ctx; 917 918 enum dc_color_space color_space; 919 920 struct dc_3dlut *lut3d_func; 921 struct dc_transfer_func *in_shaper_func; 922 struct dc_transfer_func *blend_tf; 923 924 #if defined(CONFIG_DRM_AMD_DC_DCN) 925 struct dc_transfer_func *gamcor_tf; 926 #endif 927 enum surface_pixel_format format; 928 enum dc_rotation_angle rotation; 929 enum plane_stereo_format stereo_format; 930 931 bool is_tiling_rotated; 932 bool per_pixel_alpha; 933 bool global_alpha; 934 int global_alpha_value; 935 bool visible; 936 bool flip_immediate; 937 bool horizontal_mirror; 938 int layer_index; 939 940 union surface_update_flags update_flags; 941 bool flip_int_enabled; 942 bool skip_manual_trigger; 943 944 /* private to DC core */ 945 struct dc_plane_status status; 946 struct dc_context *ctx; 947 948 /* HACK: Workaround for forcing full reprogramming under some conditions */ 949 bool force_full_update; 950 951 /* private to dc_surface.c */ 952 enum dc_irq_source irq_source; 953 struct kref refcount; 954 }; 955 956 struct dc_plane_info { 957 struct plane_size plane_size; 958 union dc_tiling_info tiling_info; 959 struct dc_plane_dcc_param dcc; 960 enum surface_pixel_format format; 961 enum dc_rotation_angle rotation; 962 enum plane_stereo_format stereo_format; 963 enum dc_color_space color_space; 964 bool horizontal_mirror; 965 bool visible; 966 bool per_pixel_alpha; 967 bool global_alpha; 968 int global_alpha_value; 969 bool input_csc_enabled; 970 int layer_index; 971 }; 972 973 struct dc_scaling_info { 974 struct rect src_rect; 975 struct rect dst_rect; 976 struct rect clip_rect; 977 struct scaling_taps scaling_quality; 978 }; 979 980 struct dc_surface_update { 981 struct dc_plane_state *surface; 982 983 /* isr safe update parameters. null means no updates */ 984 const struct dc_flip_addrs *flip_addr; 985 const struct dc_plane_info *plane_info; 986 const struct dc_scaling_info *scaling_info; 987 struct fixed31_32 hdr_mult; 988 /* following updates require alloc/sleep/spin that is not isr safe, 989 * null means no updates 990 */ 991 const struct dc_gamma *gamma; 992 const struct dc_transfer_func *in_transfer_func; 993 994 const struct dc_csc_transform *input_csc_color_matrix; 995 const struct fixed31_32 *coeff_reduction_factor; 996 const struct dc_transfer_func *func_shaper; 997 const struct dc_3dlut *lut3d_func; 998 const struct dc_transfer_func *blend_tf; 999 const struct colorspace_transform *gamut_remap_matrix; 1000 }; 1001 1002 /* 1003 * Create a new surface with default parameters; 1004 */ 1005 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 1006 const struct dc_plane_status *dc_plane_get_status( 1007 const struct dc_plane_state *plane_state); 1008 1009 void dc_plane_state_retain(struct dc_plane_state *plane_state); 1010 void dc_plane_state_release(struct dc_plane_state *plane_state); 1011 1012 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1013 void dc_gamma_release(struct dc_gamma **dc_gamma); 1014 struct dc_gamma *dc_create_gamma(void); 1015 1016 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1017 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1018 struct dc_transfer_func *dc_create_transfer_func(void); 1019 1020 struct dc_3dlut *dc_create_3dlut_func(void); 1021 void dc_3dlut_func_release(struct dc_3dlut *lut); 1022 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1023 /* 1024 * This structure holds a surface address. There could be multiple addresses 1025 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 1026 * as frame durations and DCC format can also be set. 1027 */ 1028 struct dc_flip_addrs { 1029 struct dc_plane_address address; 1030 unsigned int flip_timestamp_in_us; 1031 bool flip_immediate; 1032 /* TODO: add flip duration for FreeSync */ 1033 bool triplebuffer_flips; 1034 }; 1035 1036 void dc_post_update_surfaces_to_stream( 1037 struct dc *dc); 1038 1039 #include "dc_stream.h" 1040 1041 /* 1042 * Structure to store surface/stream associations for validation 1043 */ 1044 struct dc_validation_set { 1045 struct dc_stream_state *stream; 1046 struct dc_plane_state *plane_states[MAX_SURFACES]; 1047 uint8_t plane_count; 1048 }; 1049 1050 bool dc_validate_seamless_boot_timing(const struct dc *dc, 1051 const struct dc_sink *sink, 1052 struct dc_crtc_timing *crtc_timing); 1053 1054 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1055 1056 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 1057 1058 bool dc_set_generic_gpio_for_stereo(bool enable, 1059 struct gpio_service *gpio_service); 1060 1061 /* 1062 * fast_validate: we return after determining if we can support the new state, 1063 * but before we populate the programming info 1064 */ 1065 enum dc_status dc_validate_global_state( 1066 struct dc *dc, 1067 struct dc_state *new_ctx, 1068 bool fast_validate); 1069 1070 1071 void dc_resource_state_construct( 1072 const struct dc *dc, 1073 struct dc_state *dst_ctx); 1074 1075 #if defined(CONFIG_DRM_AMD_DC_DCN) 1076 bool dc_acquire_release_mpc_3dlut( 1077 struct dc *dc, bool acquire, 1078 struct dc_stream_state *stream, 1079 struct dc_3dlut **lut, 1080 struct dc_transfer_func **shaper); 1081 #endif 1082 1083 void dc_resource_state_copy_construct( 1084 const struct dc_state *src_ctx, 1085 struct dc_state *dst_ctx); 1086 1087 void dc_resource_state_copy_construct_current( 1088 const struct dc *dc, 1089 struct dc_state *dst_ctx); 1090 1091 void dc_resource_state_destruct(struct dc_state *context); 1092 1093 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1094 1095 /* 1096 * TODO update to make it about validation sets 1097 * Set up streams and links associated to drive sinks 1098 * The streams parameter is an absolute set of all active streams. 1099 * 1100 * After this call: 1101 * Phy, Encoder, Timing Generator are programmed and enabled. 1102 * New streams are enabled with blank stream; no memory read. 1103 */ 1104 bool dc_commit_state(struct dc *dc, struct dc_state *context); 1105 1106 struct dc_state *dc_create_state(struct dc *dc); 1107 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 1108 void dc_retain_state(struct dc_state *context); 1109 void dc_release_state(struct dc_state *context); 1110 1111 /******************************************************************************* 1112 * Link Interfaces 1113 ******************************************************************************/ 1114 1115 struct dpcd_caps { 1116 union dpcd_rev dpcd_rev; 1117 union max_lane_count max_ln_count; 1118 union max_down_spread max_down_spread; 1119 union dprx_feature dprx_feature; 1120 1121 /* valid only for eDP v1.4 or higher*/ 1122 uint8_t edp_supported_link_rates_count; 1123 enum dc_link_rate edp_supported_link_rates[8]; 1124 1125 /* dongle type (DP converter, CV smart dongle) */ 1126 enum display_dongle_type dongle_type; 1127 /* branch device or sink device */ 1128 bool is_branch_dev; 1129 /* Dongle's downstream count. */ 1130 union sink_count sink_count; 1131 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1132 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1133 struct dc_dongle_caps dongle_caps; 1134 1135 uint32_t sink_dev_id; 1136 int8_t sink_dev_id_str[6]; 1137 int8_t sink_hw_revision; 1138 int8_t sink_fw_revision[2]; 1139 1140 uint32_t branch_dev_id; 1141 int8_t branch_dev_name[6]; 1142 int8_t branch_hw_revision; 1143 int8_t branch_fw_revision[2]; 1144 1145 bool allow_invalid_MSA_timing_param; 1146 bool panel_mode_edp; 1147 bool dpcd_display_control_capable; 1148 bool ext_receiver_cap_field_present; 1149 bool dynamic_backlight_capable_edp; 1150 union dpcd_fec_capability fec_cap; 1151 struct dpcd_dsc_capabilities dsc_caps; 1152 struct dc_lttpr_caps lttpr_caps; 1153 struct psr_caps psr_caps; 1154 1155 }; 1156 1157 union dpcd_sink_ext_caps { 1158 struct { 1159 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1160 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1161 */ 1162 uint8_t sdr_aux_backlight_control : 1; 1163 uint8_t hdr_aux_backlight_control : 1; 1164 uint8_t reserved_1 : 2; 1165 uint8_t oled : 1; 1166 uint8_t reserved : 3; 1167 } bits; 1168 uint8_t raw; 1169 }; 1170 1171 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1172 union hdcp_rx_caps { 1173 struct { 1174 uint8_t version; 1175 uint8_t reserved; 1176 struct { 1177 uint8_t repeater : 1; 1178 uint8_t hdcp_capable : 1; 1179 uint8_t reserved : 6; 1180 } byte0; 1181 } fields; 1182 uint8_t raw[3]; 1183 }; 1184 1185 union hdcp_bcaps { 1186 struct { 1187 uint8_t HDCP_CAPABLE:1; 1188 uint8_t REPEATER:1; 1189 uint8_t RESERVED:6; 1190 } bits; 1191 uint8_t raw; 1192 }; 1193 1194 struct hdcp_caps { 1195 union hdcp_rx_caps rx_caps; 1196 union hdcp_bcaps bcaps; 1197 }; 1198 #endif 1199 1200 #include "dc_link.h" 1201 1202 #if defined(CONFIG_DRM_AMD_DC_DCN) 1203 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1204 1205 #endif 1206 /******************************************************************************* 1207 * Sink Interfaces - A sink corresponds to a display output device 1208 ******************************************************************************/ 1209 1210 struct dc_container_id { 1211 // 128bit GUID in binary form 1212 unsigned char guid[16]; 1213 // 8 byte port ID -> ELD.PortID 1214 unsigned int portId[2]; 1215 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1216 unsigned short manufacturerName; 1217 // 2 byte product code -> ELD.ProductCode 1218 unsigned short productCode; 1219 }; 1220 1221 1222 struct dc_sink_dsc_caps { 1223 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1224 // 'false' if they are sink's DSC caps 1225 bool is_virtual_dpcd_dsc; 1226 struct dsc_dec_dpcd_caps dsc_dec_caps; 1227 }; 1228 1229 struct dc_sink_fec_caps { 1230 bool is_rx_fec_supported; 1231 bool is_topology_fec_supported; 1232 }; 1233 1234 /* 1235 * The sink structure contains EDID and other display device properties 1236 */ 1237 struct dc_sink { 1238 enum signal_type sink_signal; 1239 struct dc_edid dc_edid; /* raw edid */ 1240 struct dc_edid_caps edid_caps; /* parse display caps */ 1241 struct dc_container_id *dc_container_id; 1242 uint32_t dongle_max_pix_clk; 1243 void *priv; 1244 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1245 bool converter_disable_audio; 1246 1247 struct dc_sink_dsc_caps dsc_caps; 1248 struct dc_sink_fec_caps fec_caps; 1249 1250 bool is_vsc_sdp_colorimetry_supported; 1251 1252 /* private to DC core */ 1253 struct dc_link *link; 1254 struct dc_context *ctx; 1255 1256 uint32_t sink_id; 1257 1258 /* private to dc_sink.c */ 1259 // refcount must be the last member in dc_sink, since we want the 1260 // sink structure to be logically cloneable up to (but not including) 1261 // refcount 1262 struct kref refcount; 1263 }; 1264 1265 void dc_sink_retain(struct dc_sink *sink); 1266 void dc_sink_release(struct dc_sink *sink); 1267 1268 struct dc_sink_init_data { 1269 enum signal_type sink_signal; 1270 struct dc_link *link; 1271 uint32_t dongle_max_pix_clk; 1272 bool converter_disable_audio; 1273 }; 1274 1275 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1276 1277 /* Newer interfaces */ 1278 struct dc_cursor { 1279 struct dc_plane_address address; 1280 struct dc_cursor_attributes attributes; 1281 }; 1282 1283 1284 /******************************************************************************* 1285 * Interrupt interfaces 1286 ******************************************************************************/ 1287 enum dc_irq_source dc_interrupt_to_irq_source( 1288 struct dc *dc, 1289 uint32_t src_id, 1290 uint32_t ext_id); 1291 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1292 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1293 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1294 struct dc *dc, uint32_t link_index); 1295 1296 /******************************************************************************* 1297 * Power Interfaces 1298 ******************************************************************************/ 1299 1300 void dc_set_power_state( 1301 struct dc *dc, 1302 enum dc_acpi_cm_power_state power_state); 1303 void dc_resume(struct dc *dc); 1304 1305 void dc_power_down_on_boot(struct dc *dc); 1306 1307 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1308 /* 1309 * HDCP Interfaces 1310 */ 1311 enum hdcp_message_status dc_process_hdcp_msg( 1312 enum signal_type signal, 1313 struct dc_link *link, 1314 struct hdcp_protection_message *message_info); 1315 #endif 1316 bool dc_is_dmcu_initialized(struct dc *dc); 1317 1318 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1319 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1320 #if defined(CONFIG_DRM_AMD_DC_DCN) 1321 1322 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane, 1323 struct dc_cursor_attributes *cursor_attr); 1324 1325 void dc_allow_idle_optimizations(struct dc *dc, bool allow); 1326 1327 /* 1328 * blank all streams, and set min and max memory clock to 1329 * lowest and highest DPM level, respectively 1330 */ 1331 void dc_unlock_memory_clock_frequency(struct dc *dc); 1332 1333 /* 1334 * set min memory clock to the min required for current mode, 1335 * max to maxDPM, and unblank streams 1336 */ 1337 void dc_lock_memory_clock_frequency(struct dc *dc); 1338 1339 /* cleanup on driver unload */ 1340 void dc_hardware_release(struct dc *dc); 1341 1342 #endif 1343 1344 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1345 #if defined(CONFIG_DRM_AMD_DC_DCN) 1346 void dc_z10_restore(struct dc *dc); 1347 void dc_z10_save_init(struct dc *dc); 1348 #endif 1349 1350 bool dc_enable_dmub_notifications(struct dc *dc); 1351 1352 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 1353 uint32_t link_index, 1354 struct aux_payload *payload); 1355 1356 /******************************************************************************* 1357 * DSC Interfaces 1358 ******************************************************************************/ 1359 #include "dc_dsc.h" 1360 1361 /******************************************************************************* 1362 * Disable acc mode Interfaces 1363 ******************************************************************************/ 1364 void dc_disable_accelerated_mode(struct dc *dc); 1365 1366 #endif /* DC_INTERFACE_H_ */ 1367