1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2017 Impinj, Inc
4 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
5 *
6 * Based on the code of analogus driver:
7 *
8 * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_domain.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/reset.h>
19 #include <linux/sizes.h>
20 #include <dt-bindings/power/imx7-power.h>
21 #include <dt-bindings/power/imx8mq-power.h>
22 #include <dt-bindings/power/imx8mm-power.h>
23 #include <dt-bindings/power/imx8mn-power.h>
24
25 #define GPC_LPCR_A_CORE_BSC 0x000
26
27 #define GPC_PGC_CPU_MAPPING 0x0ec
28
29 #define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN BIT(6)
30 #define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN BIT(5)
31 #define IMX7_USB_OTG1_PHY_A_CORE_DOMAIN BIT(4)
32 #define IMX7_PCIE_PHY_A_CORE_DOMAIN BIT(3)
33 #define IMX7_MIPI_PHY_A_CORE_DOMAIN BIT(2)
34
35 #define IMX8M_PCIE2_A53_DOMAIN BIT(15)
36 #define IMX8M_MIPI_CSI2_A53_DOMAIN BIT(14)
37 #define IMX8M_MIPI_CSI1_A53_DOMAIN BIT(13)
38 #define IMX8M_DISP_A53_DOMAIN BIT(12)
39 #define IMX8M_HDMI_A53_DOMAIN BIT(11)
40 #define IMX8M_VPU_A53_DOMAIN BIT(10)
41 #define IMX8M_GPU_A53_DOMAIN BIT(9)
42 #define IMX8M_DDR2_A53_DOMAIN BIT(8)
43 #define IMX8M_DDR1_A53_DOMAIN BIT(7)
44 #define IMX8M_OTG2_A53_DOMAIN BIT(5)
45 #define IMX8M_OTG1_A53_DOMAIN BIT(4)
46 #define IMX8M_PCIE1_A53_DOMAIN BIT(3)
47 #define IMX8M_MIPI_A53_DOMAIN BIT(2)
48
49 #define IMX8MM_VPUH1_A53_DOMAIN BIT(15)
50 #define IMX8MM_VPUG2_A53_DOMAIN BIT(14)
51 #define IMX8MM_VPUG1_A53_DOMAIN BIT(13)
52 #define IMX8MM_DISPMIX_A53_DOMAIN BIT(12)
53 #define IMX8MM_VPUMIX_A53_DOMAIN BIT(10)
54 #define IMX8MM_GPUMIX_A53_DOMAIN BIT(9)
55 #define IMX8MM_GPU_A53_DOMAIN (BIT(8) | BIT(11))
56 #define IMX8MM_DDR1_A53_DOMAIN BIT(7)
57 #define IMX8MM_OTG2_A53_DOMAIN BIT(5)
58 #define IMX8MM_OTG1_A53_DOMAIN BIT(4)
59 #define IMX8MM_PCIE_A53_DOMAIN BIT(3)
60 #define IMX8MM_MIPI_A53_DOMAIN BIT(2)
61
62 #define IMX8MN_DISPMIX_A53_DOMAIN BIT(12)
63 #define IMX8MN_GPUMIX_A53_DOMAIN BIT(9)
64 #define IMX8MN_DDR1_A53_DOMAIN BIT(7)
65 #define IMX8MN_OTG1_A53_DOMAIN BIT(4)
66 #define IMX8MN_MIPI_A53_DOMAIN BIT(2)
67
68 #define GPC_PU_PGC_SW_PUP_REQ 0x0f8
69 #define GPC_PU_PGC_SW_PDN_REQ 0x104
70
71 #define IMX7_USB_HSIC_PHY_SW_Pxx_REQ BIT(4)
72 #define IMX7_USB_OTG2_PHY_SW_Pxx_REQ BIT(3)
73 #define IMX7_USB_OTG1_PHY_SW_Pxx_REQ BIT(2)
74 #define IMX7_PCIE_PHY_SW_Pxx_REQ BIT(1)
75 #define IMX7_MIPI_PHY_SW_Pxx_REQ BIT(0)
76
77 #define IMX8M_PCIE2_SW_Pxx_REQ BIT(13)
78 #define IMX8M_MIPI_CSI2_SW_Pxx_REQ BIT(12)
79 #define IMX8M_MIPI_CSI1_SW_Pxx_REQ BIT(11)
80 #define IMX8M_DISP_SW_Pxx_REQ BIT(10)
81 #define IMX8M_HDMI_SW_Pxx_REQ BIT(9)
82 #define IMX8M_VPU_SW_Pxx_REQ BIT(8)
83 #define IMX8M_GPU_SW_Pxx_REQ BIT(7)
84 #define IMX8M_DDR2_SW_Pxx_REQ BIT(6)
85 #define IMX8M_DDR1_SW_Pxx_REQ BIT(5)
86 #define IMX8M_OTG2_SW_Pxx_REQ BIT(3)
87 #define IMX8M_OTG1_SW_Pxx_REQ BIT(2)
88 #define IMX8M_PCIE1_SW_Pxx_REQ BIT(1)
89 #define IMX8M_MIPI_SW_Pxx_REQ BIT(0)
90
91 #define IMX8MM_VPUH1_SW_Pxx_REQ BIT(13)
92 #define IMX8MM_VPUG2_SW_Pxx_REQ BIT(12)
93 #define IMX8MM_VPUG1_SW_Pxx_REQ BIT(11)
94 #define IMX8MM_DISPMIX_SW_Pxx_REQ BIT(10)
95 #define IMX8MM_VPUMIX_SW_Pxx_REQ BIT(8)
96 #define IMX8MM_GPUMIX_SW_Pxx_REQ BIT(7)
97 #define IMX8MM_GPU_SW_Pxx_REQ (BIT(6) | BIT(9))
98 #define IMX8MM_DDR1_SW_Pxx_REQ BIT(5)
99 #define IMX8MM_OTG2_SW_Pxx_REQ BIT(3)
100 #define IMX8MM_OTG1_SW_Pxx_REQ BIT(2)
101 #define IMX8MM_PCIE_SW_Pxx_REQ BIT(1)
102 #define IMX8MM_MIPI_SW_Pxx_REQ BIT(0)
103
104 #define IMX8MN_DISPMIX_SW_Pxx_REQ BIT(10)
105 #define IMX8MN_GPUMIX_SW_Pxx_REQ BIT(7)
106 #define IMX8MN_DDR1_SW_Pxx_REQ BIT(5)
107 #define IMX8MN_OTG1_SW_Pxx_REQ BIT(2)
108 #define IMX8MN_MIPI_SW_Pxx_REQ BIT(0)
109
110 #define GPC_M4_PU_PDN_FLG 0x1bc
111
112 #define GPC_PU_PWRHSK 0x1fc
113
114 #define IMX8M_GPU_HSK_PWRDNACKN BIT(26)
115 #define IMX8M_VPU_HSK_PWRDNACKN BIT(25)
116 #define IMX8M_DISP_HSK_PWRDNACKN BIT(24)
117 #define IMX8M_GPU_HSK_PWRDNREQN BIT(6)
118 #define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
119 #define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
120
121
122 #define IMX8MM_GPUMIX_HSK_PWRDNACKN BIT(29)
123 #define IMX8MM_GPU_HSK_PWRDNACKN (BIT(27) | BIT(28))
124 #define IMX8MM_VPUMIX_HSK_PWRDNACKN BIT(26)
125 #define IMX8MM_DISPMIX_HSK_PWRDNACKN BIT(25)
126 #define IMX8MM_HSIO_HSK_PWRDNACKN (BIT(23) | BIT(24))
127 #define IMX8MM_GPUMIX_HSK_PWRDNREQN BIT(11)
128 #define IMX8MM_GPU_HSK_PWRDNREQN (BIT(9) | BIT(10))
129 #define IMX8MM_VPUMIX_HSK_PWRDNREQN BIT(8)
130 #define IMX8MM_DISPMIX_HSK_PWRDNREQN BIT(7)
131 #define IMX8MM_HSIO_HSK_PWRDNREQN (BIT(5) | BIT(6))
132
133 #define IMX8MN_GPUMIX_HSK_PWRDNACKN (BIT(29) | BIT(27))
134 #define IMX8MN_DISPMIX_HSK_PWRDNACKN BIT(25)
135 #define IMX8MN_HSIO_HSK_PWRDNACKN BIT(23)
136 #define IMX8MN_GPUMIX_HSK_PWRDNREQN (BIT(11) | BIT(9))
137 #define IMX8MN_DISPMIX_HSK_PWRDNREQN BIT(7)
138 #define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5)
139
140 /*
141 * The PGC offset values in Reference Manual
142 * (Rev. 1, 01/2018 and the older ones) GPC chapter's
143 * GPC_PGC memory map are incorrect, below offset
144 * values are from design RTL.
145 */
146 #define IMX7_PGC_MIPI 16
147 #define IMX7_PGC_PCIE 17
148 #define IMX7_PGC_USB_HSIC 20
149
150 #define IMX8M_PGC_MIPI 16
151 #define IMX8M_PGC_PCIE1 17
152 #define IMX8M_PGC_OTG1 18
153 #define IMX8M_PGC_OTG2 19
154 #define IMX8M_PGC_DDR1 21
155 #define IMX8M_PGC_GPU 23
156 #define IMX8M_PGC_VPU 24
157 #define IMX8M_PGC_DISP 26
158 #define IMX8M_PGC_MIPI_CSI1 27
159 #define IMX8M_PGC_MIPI_CSI2 28
160 #define IMX8M_PGC_PCIE2 29
161
162 #define IMX8MM_PGC_MIPI 16
163 #define IMX8MM_PGC_PCIE 17
164 #define IMX8MM_PGC_OTG1 18
165 #define IMX8MM_PGC_OTG2 19
166 #define IMX8MM_PGC_DDR1 21
167 #define IMX8MM_PGC_GPU2D 22
168 #define IMX8MM_PGC_GPUMIX 23
169 #define IMX8MM_PGC_VPUMIX 24
170 #define IMX8MM_PGC_GPU3D 25
171 #define IMX8MM_PGC_DISPMIX 26
172 #define IMX8MM_PGC_VPUG1 27
173 #define IMX8MM_PGC_VPUG2 28
174 #define IMX8MM_PGC_VPUH1 29
175
176 #define IMX8MN_PGC_MIPI 16
177 #define IMX8MN_PGC_OTG1 18
178 #define IMX8MN_PGC_DDR1 21
179 #define IMX8MN_PGC_GPUMIX 23
180 #define IMX8MN_PGC_DISPMIX 26
181
182 #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
183 #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
184
185 #define GPC_PGC_CTRL_PCR BIT(0)
186
187 struct imx_pgc_domain {
188 struct generic_pm_domain genpd;
189 struct regmap *regmap;
190 struct regulator *regulator;
191 struct reset_control *reset;
192 struct clk_bulk_data *clks;
193 int num_clks;
194
195 unsigned int pgc;
196
197 const struct {
198 u32 pxx;
199 u32 map;
200 u32 hskreq;
201 u32 hskack;
202 } bits;
203
204 const int voltage;
205 struct device *dev;
206 };
207
208 struct imx_pgc_domain_data {
209 const struct imx_pgc_domain *domains;
210 size_t domains_num;
211 const struct regmap_access_table *reg_access_table;
212 };
213
214 static inline struct imx_pgc_domain *
to_imx_pgc_domain(struct generic_pm_domain * genpd)215 to_imx_pgc_domain(struct generic_pm_domain *genpd)
216 {
217 return container_of(genpd, struct imx_pgc_domain, genpd);
218 }
219
imx_pgc_power_up(struct generic_pm_domain * genpd)220 static int imx_pgc_power_up(struct generic_pm_domain *genpd)
221 {
222 struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
223 u32 reg_val;
224 int ret;
225
226 ret = pm_runtime_get_sync(domain->dev);
227 if (ret < 0) {
228 pm_runtime_put_noidle(domain->dev);
229 return ret;
230 }
231
232 if (!IS_ERR(domain->regulator)) {
233 ret = regulator_enable(domain->regulator);
234 if (ret) {
235 dev_err(domain->dev, "failed to enable regulator\n");
236 goto out_put_pm;
237 }
238 }
239
240 reset_control_assert(domain->reset);
241
242 /* Enable reset clocks for all devices in the domain */
243 ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
244 if (ret) {
245 dev_err(domain->dev, "failed to enable reset clocks\n");
246 goto out_regulator_disable;
247 }
248
249 /* delays for reset to propagate */
250 udelay(5);
251
252 if (domain->bits.pxx) {
253 /* request the domain to power up */
254 regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
255 domain->bits.pxx, domain->bits.pxx);
256 /*
257 * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
258 * for PUP_REQ/PDN_REQ bit to be cleared
259 */
260 ret = regmap_read_poll_timeout(domain->regmap,
261 GPC_PU_PGC_SW_PUP_REQ, reg_val,
262 !(reg_val & domain->bits.pxx),
263 0, USEC_PER_MSEC);
264 if (ret) {
265 dev_err(domain->dev, "failed to command PGC\n");
266 goto out_clk_disable;
267 }
268
269 /* disable power control */
270 regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
271 GPC_PGC_CTRL_PCR);
272 }
273
274 /* delay for reset to propagate */
275 udelay(5);
276
277 reset_control_deassert(domain->reset);
278
279 /* request the ADB400 to power up */
280 if (domain->bits.hskreq) {
281 regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
282 domain->bits.hskreq, domain->bits.hskreq);
283
284 /*
285 * ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, reg_val,
286 * (reg_val & domain->bits.hskack), 0,
287 * USEC_PER_MSEC);
288 * Technically we need the commented code to wait handshake. But that needs
289 * the BLK-CTL module BUS clk-en bit being set.
290 *
291 * There is a separate BLK-CTL module and we will have such a driver for it,
292 * that driver will set the BUS clk-en bit and handshake will be triggered
293 * automatically there. Just add a delay and suppose the handshake finish
294 * after that.
295 */
296 }
297
298 /* Disable reset clocks for all devices in the domain */
299 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
300
301 return 0;
302
303 out_clk_disable:
304 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
305 out_regulator_disable:
306 if (!IS_ERR(domain->regulator))
307 regulator_disable(domain->regulator);
308 out_put_pm:
309 pm_runtime_put(domain->dev);
310
311 return ret;
312 }
313
imx_pgc_power_down(struct generic_pm_domain * genpd)314 static int imx_pgc_power_down(struct generic_pm_domain *genpd)
315 {
316 struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd);
317 u32 reg_val;
318 int ret;
319
320 /* Enable reset clocks for all devices in the domain */
321 ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
322 if (ret) {
323 dev_err(domain->dev, "failed to enable reset clocks\n");
324 return ret;
325 }
326
327 /* request the ADB400 to power down */
328 if (domain->bits.hskreq) {
329 regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK,
330 domain->bits.hskreq);
331
332 ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK,
333 reg_val,
334 !(reg_val & domain->bits.hskack),
335 0, USEC_PER_MSEC);
336 if (ret) {
337 dev_err(domain->dev, "failed to power down ADB400\n");
338 goto out_clk_disable;
339 }
340 }
341
342 if (domain->bits.pxx) {
343 /* enable power control */
344 regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
345 GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
346
347 /* request the domain to power down */
348 regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
349 domain->bits.pxx, domain->bits.pxx);
350 /*
351 * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
352 * for PUP_REQ/PDN_REQ bit to be cleared
353 */
354 ret = regmap_read_poll_timeout(domain->regmap,
355 GPC_PU_PGC_SW_PDN_REQ, reg_val,
356 !(reg_val & domain->bits.pxx),
357 0, USEC_PER_MSEC);
358 if (ret) {
359 dev_err(domain->dev, "failed to command PGC\n");
360 goto out_clk_disable;
361 }
362 }
363
364 /* Disable reset clocks for all devices in the domain */
365 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
366
367 if (!IS_ERR(domain->regulator)) {
368 ret = regulator_disable(domain->regulator);
369 if (ret) {
370 dev_err(domain->dev, "failed to disable regulator\n");
371 return ret;
372 }
373 }
374
375 pm_runtime_put_sync_suspend(domain->dev);
376
377 return 0;
378
379 out_clk_disable:
380 clk_bulk_disable_unprepare(domain->num_clks, domain->clks);
381
382 return ret;
383 }
384
385 static const struct imx_pgc_domain imx7_pgc_domains[] = {
386 [IMX7_POWER_DOMAIN_MIPI_PHY] = {
387 .genpd = {
388 .name = "mipi-phy",
389 },
390 .bits = {
391 .pxx = IMX7_MIPI_PHY_SW_Pxx_REQ,
392 .map = IMX7_MIPI_PHY_A_CORE_DOMAIN,
393 },
394 .voltage = 1000000,
395 .pgc = IMX7_PGC_MIPI,
396 },
397
398 [IMX7_POWER_DOMAIN_PCIE_PHY] = {
399 .genpd = {
400 .name = "pcie-phy",
401 },
402 .bits = {
403 .pxx = IMX7_PCIE_PHY_SW_Pxx_REQ,
404 .map = IMX7_PCIE_PHY_A_CORE_DOMAIN,
405 },
406 .voltage = 1000000,
407 .pgc = IMX7_PGC_PCIE,
408 },
409
410 [IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
411 .genpd = {
412 .name = "usb-hsic-phy",
413 },
414 .bits = {
415 .pxx = IMX7_USB_HSIC_PHY_SW_Pxx_REQ,
416 .map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN,
417 },
418 .voltage = 1200000,
419 .pgc = IMX7_PGC_USB_HSIC,
420 },
421 };
422
423 static const struct regmap_range imx7_yes_ranges[] = {
424 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
425 GPC_M4_PU_PDN_FLG),
426 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_MIPI),
427 GPC_PGC_SR(IMX7_PGC_MIPI)),
428 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_PCIE),
429 GPC_PGC_SR(IMX7_PGC_PCIE)),
430 regmap_reg_range(GPC_PGC_CTRL(IMX7_PGC_USB_HSIC),
431 GPC_PGC_SR(IMX7_PGC_USB_HSIC)),
432 };
433
434 static const struct regmap_access_table imx7_access_table = {
435 .yes_ranges = imx7_yes_ranges,
436 .n_yes_ranges = ARRAY_SIZE(imx7_yes_ranges),
437 };
438
439 static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
440 .domains = imx7_pgc_domains,
441 .domains_num = ARRAY_SIZE(imx7_pgc_domains),
442 .reg_access_table = &imx7_access_table,
443 };
444
445 static const struct imx_pgc_domain imx8m_pgc_domains[] = {
446 [IMX8M_POWER_DOMAIN_MIPI] = {
447 .genpd = {
448 .name = "mipi",
449 },
450 .bits = {
451 .pxx = IMX8M_MIPI_SW_Pxx_REQ,
452 .map = IMX8M_MIPI_A53_DOMAIN,
453 },
454 .pgc = IMX8M_PGC_MIPI,
455 },
456
457 [IMX8M_POWER_DOMAIN_PCIE1] = {
458 .genpd = {
459 .name = "pcie1",
460 },
461 .bits = {
462 .pxx = IMX8M_PCIE1_SW_Pxx_REQ,
463 .map = IMX8M_PCIE1_A53_DOMAIN,
464 },
465 .pgc = IMX8M_PGC_PCIE1,
466 },
467
468 [IMX8M_POWER_DOMAIN_USB_OTG1] = {
469 .genpd = {
470 .name = "usb-otg1",
471 },
472 .bits = {
473 .pxx = IMX8M_OTG1_SW_Pxx_REQ,
474 .map = IMX8M_OTG1_A53_DOMAIN,
475 },
476 .pgc = IMX8M_PGC_OTG1,
477 },
478
479 [IMX8M_POWER_DOMAIN_USB_OTG2] = {
480 .genpd = {
481 .name = "usb-otg2",
482 },
483 .bits = {
484 .pxx = IMX8M_OTG2_SW_Pxx_REQ,
485 .map = IMX8M_OTG2_A53_DOMAIN,
486 },
487 .pgc = IMX8M_PGC_OTG2,
488 },
489
490 [IMX8M_POWER_DOMAIN_DDR1] = {
491 .genpd = {
492 .name = "ddr1",
493 },
494 .bits = {
495 .pxx = IMX8M_DDR1_SW_Pxx_REQ,
496 .map = IMX8M_DDR2_A53_DOMAIN,
497 },
498 .pgc = IMX8M_PGC_DDR1,
499 },
500
501 [IMX8M_POWER_DOMAIN_GPU] = {
502 .genpd = {
503 .name = "gpu",
504 },
505 .bits = {
506 .pxx = IMX8M_GPU_SW_Pxx_REQ,
507 .map = IMX8M_GPU_A53_DOMAIN,
508 .hskreq = IMX8M_GPU_HSK_PWRDNREQN,
509 .hskack = IMX8M_GPU_HSK_PWRDNACKN,
510 },
511 .pgc = IMX8M_PGC_GPU,
512 },
513
514 [IMX8M_POWER_DOMAIN_VPU] = {
515 .genpd = {
516 .name = "vpu",
517 },
518 .bits = {
519 .pxx = IMX8M_VPU_SW_Pxx_REQ,
520 .map = IMX8M_VPU_A53_DOMAIN,
521 .hskreq = IMX8M_VPU_HSK_PWRDNREQN,
522 .hskack = IMX8M_VPU_HSK_PWRDNACKN,
523 },
524 .pgc = IMX8M_PGC_VPU,
525 },
526
527 [IMX8M_POWER_DOMAIN_DISP] = {
528 .genpd = {
529 .name = "disp",
530 },
531 .bits = {
532 .pxx = IMX8M_DISP_SW_Pxx_REQ,
533 .map = IMX8M_DISP_A53_DOMAIN,
534 .hskreq = IMX8M_DISP_HSK_PWRDNREQN,
535 .hskack = IMX8M_DISP_HSK_PWRDNACKN,
536 },
537 .pgc = IMX8M_PGC_DISP,
538 },
539
540 [IMX8M_POWER_DOMAIN_MIPI_CSI1] = {
541 .genpd = {
542 .name = "mipi-csi1",
543 },
544 .bits = {
545 .pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ,
546 .map = IMX8M_MIPI_CSI1_A53_DOMAIN,
547 },
548 .pgc = IMX8M_PGC_MIPI_CSI1,
549 },
550
551 [IMX8M_POWER_DOMAIN_MIPI_CSI2] = {
552 .genpd = {
553 .name = "mipi-csi2",
554 },
555 .bits = {
556 .pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ,
557 .map = IMX8M_MIPI_CSI2_A53_DOMAIN,
558 },
559 .pgc = IMX8M_PGC_MIPI_CSI2,
560 },
561
562 [IMX8M_POWER_DOMAIN_PCIE2] = {
563 .genpd = {
564 .name = "pcie2",
565 },
566 .bits = {
567 .pxx = IMX8M_PCIE2_SW_Pxx_REQ,
568 .map = IMX8M_PCIE2_A53_DOMAIN,
569 },
570 .pgc = IMX8M_PGC_PCIE2,
571 },
572 };
573
574 static const struct regmap_range imx8m_yes_ranges[] = {
575 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
576 GPC_PU_PWRHSK),
577 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI),
578 GPC_PGC_SR(IMX8M_PGC_MIPI)),
579 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE1),
580 GPC_PGC_SR(IMX8M_PGC_PCIE1)),
581 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG1),
582 GPC_PGC_SR(IMX8M_PGC_OTG1)),
583 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_OTG2),
584 GPC_PGC_SR(IMX8M_PGC_OTG2)),
585 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DDR1),
586 GPC_PGC_SR(IMX8M_PGC_DDR1)),
587 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_GPU),
588 GPC_PGC_SR(IMX8M_PGC_GPU)),
589 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_VPU),
590 GPC_PGC_SR(IMX8M_PGC_VPU)),
591 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_DISP),
592 GPC_PGC_SR(IMX8M_PGC_DISP)),
593 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI1),
594 GPC_PGC_SR(IMX8M_PGC_MIPI_CSI1)),
595 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_MIPI_CSI2),
596 GPC_PGC_SR(IMX8M_PGC_MIPI_CSI2)),
597 regmap_reg_range(GPC_PGC_CTRL(IMX8M_PGC_PCIE2),
598 GPC_PGC_SR(IMX8M_PGC_PCIE2)),
599 };
600
601 static const struct regmap_access_table imx8m_access_table = {
602 .yes_ranges = imx8m_yes_ranges,
603 .n_yes_ranges = ARRAY_SIZE(imx8m_yes_ranges),
604 };
605
606 static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
607 .domains = imx8m_pgc_domains,
608 .domains_num = ARRAY_SIZE(imx8m_pgc_domains),
609 .reg_access_table = &imx8m_access_table,
610 };
611
612 static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
613 [IMX8MM_POWER_DOMAIN_HSIOMIX] = {
614 .genpd = {
615 .name = "hsiomix",
616 },
617 .bits = {
618 .pxx = 0, /* no power sequence control */
619 .map = 0, /* no power sequence control */
620 .hskreq = IMX8MM_HSIO_HSK_PWRDNREQN,
621 .hskack = IMX8MM_HSIO_HSK_PWRDNACKN,
622 },
623 },
624
625 [IMX8MM_POWER_DOMAIN_PCIE] = {
626 .genpd = {
627 .name = "pcie",
628 },
629 .bits = {
630 .pxx = IMX8MM_PCIE_SW_Pxx_REQ,
631 .map = IMX8MM_PCIE_A53_DOMAIN,
632 },
633 .pgc = IMX8MM_PGC_PCIE,
634 },
635
636 [IMX8MM_POWER_DOMAIN_OTG1] = {
637 .genpd = {
638 .name = "usb-otg1",
639 },
640 .bits = {
641 .pxx = IMX8MM_OTG1_SW_Pxx_REQ,
642 .map = IMX8MM_OTG1_A53_DOMAIN,
643 },
644 .pgc = IMX8MM_PGC_OTG1,
645 },
646
647 [IMX8MM_POWER_DOMAIN_OTG2] = {
648 .genpd = {
649 .name = "usb-otg2",
650 },
651 .bits = {
652 .pxx = IMX8MM_OTG2_SW_Pxx_REQ,
653 .map = IMX8MM_OTG2_A53_DOMAIN,
654 },
655 .pgc = IMX8MM_PGC_OTG2,
656 },
657
658 [IMX8MM_POWER_DOMAIN_GPUMIX] = {
659 .genpd = {
660 .name = "gpumix",
661 },
662 .bits = {
663 .pxx = IMX8MM_GPUMIX_SW_Pxx_REQ,
664 .map = IMX8MM_GPUMIX_A53_DOMAIN,
665 .hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN,
666 .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN,
667 },
668 .pgc = IMX8MM_PGC_GPUMIX,
669 },
670
671 [IMX8MM_POWER_DOMAIN_GPU] = {
672 .genpd = {
673 .name = "gpu",
674 },
675 .bits = {
676 .pxx = IMX8MM_GPU_SW_Pxx_REQ,
677 .map = IMX8MM_GPU_A53_DOMAIN,
678 .hskreq = IMX8MM_GPU_HSK_PWRDNREQN,
679 .hskack = IMX8MM_GPU_HSK_PWRDNACKN,
680 },
681 .pgc = IMX8MM_PGC_GPU2D,
682 },
683
684 [IMX8MM_POWER_DOMAIN_VPUMIX] = {
685 .genpd = {
686 .name = "vpumix",
687 },
688 .bits = {
689 .pxx = IMX8MM_VPUMIX_SW_Pxx_REQ,
690 .map = IMX8MM_VPUMIX_A53_DOMAIN,
691 .hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN,
692 .hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN,
693 },
694 .pgc = IMX8MM_PGC_VPUMIX,
695 },
696
697 [IMX8MM_POWER_DOMAIN_VPUG1] = {
698 .genpd = {
699 .name = "vpu-g1",
700 },
701 .bits = {
702 .pxx = IMX8MM_VPUG1_SW_Pxx_REQ,
703 .map = IMX8MM_VPUG1_A53_DOMAIN,
704 },
705 .pgc = IMX8MM_PGC_VPUG1,
706 },
707
708 [IMX8MM_POWER_DOMAIN_VPUG2] = {
709 .genpd = {
710 .name = "vpu-g2",
711 },
712 .bits = {
713 .pxx = IMX8MM_VPUG2_SW_Pxx_REQ,
714 .map = IMX8MM_VPUG2_A53_DOMAIN,
715 },
716 .pgc = IMX8MM_PGC_VPUG2,
717 },
718
719 [IMX8MM_POWER_DOMAIN_VPUH1] = {
720 .genpd = {
721 .name = "vpu-h1",
722 },
723 .bits = {
724 .pxx = IMX8MM_VPUH1_SW_Pxx_REQ,
725 .map = IMX8MM_VPUH1_A53_DOMAIN,
726 },
727 .pgc = IMX8MM_PGC_VPUH1,
728 },
729
730 [IMX8MM_POWER_DOMAIN_DISPMIX] = {
731 .genpd = {
732 .name = "dispmix",
733 },
734 .bits = {
735 .pxx = IMX8MM_DISPMIX_SW_Pxx_REQ,
736 .map = IMX8MM_DISPMIX_A53_DOMAIN,
737 .hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN,
738 .hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN,
739 },
740 .pgc = IMX8MM_PGC_DISPMIX,
741 },
742
743 [IMX8MM_POWER_DOMAIN_MIPI] = {
744 .genpd = {
745 .name = "mipi",
746 },
747 .bits = {
748 .pxx = IMX8MM_MIPI_SW_Pxx_REQ,
749 .map = IMX8MM_MIPI_A53_DOMAIN,
750 },
751 .pgc = IMX8MM_PGC_MIPI,
752 },
753 };
754
755 static const struct regmap_range imx8mm_yes_ranges[] = {
756 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
757 GPC_PU_PWRHSK),
758 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_MIPI),
759 GPC_PGC_SR(IMX8MM_PGC_MIPI)),
760 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_PCIE),
761 GPC_PGC_SR(IMX8MM_PGC_PCIE)),
762 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1),
763 GPC_PGC_SR(IMX8MM_PGC_OTG1)),
764 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2),
765 GPC_PGC_SR(IMX8MM_PGC_OTG2)),
766 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DDR1),
767 GPC_PGC_SR(IMX8MM_PGC_DDR1)),
768 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU2D),
769 GPC_PGC_SR(IMX8MM_PGC_GPU2D)),
770 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPUMIX),
771 GPC_PGC_SR(IMX8MM_PGC_GPUMIX)),
772 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUMIX),
773 GPC_PGC_SR(IMX8MM_PGC_VPUMIX)),
774 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU3D),
775 GPC_PGC_SR(IMX8MM_PGC_GPU3D)),
776 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DISPMIX),
777 GPC_PGC_SR(IMX8MM_PGC_DISPMIX)),
778 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG1),
779 GPC_PGC_SR(IMX8MM_PGC_VPUG1)),
780 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG2),
781 GPC_PGC_SR(IMX8MM_PGC_VPUG2)),
782 regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUH1),
783 GPC_PGC_SR(IMX8MM_PGC_VPUH1)),
784 };
785
786 static const struct regmap_access_table imx8mm_access_table = {
787 .yes_ranges = imx8mm_yes_ranges,
788 .n_yes_ranges = ARRAY_SIZE(imx8mm_yes_ranges),
789 };
790
791 static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
792 .domains = imx8mm_pgc_domains,
793 .domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
794 .reg_access_table = &imx8mm_access_table,
795 };
796
797 static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
798 [IMX8MN_POWER_DOMAIN_HSIOMIX] = {
799 .genpd = {
800 .name = "hsiomix",
801 },
802 .bits = {
803 .pxx = 0, /* no power sequence control */
804 .map = 0, /* no power sequence control */
805 .hskreq = IMX8MN_HSIO_HSK_PWRDNREQN,
806 .hskack = IMX8MN_HSIO_HSK_PWRDNACKN,
807 },
808 },
809
810 [IMX8MN_POWER_DOMAIN_OTG1] = {
811 .genpd = {
812 .name = "usb-otg1",
813 },
814 .bits = {
815 .pxx = IMX8MN_OTG1_SW_Pxx_REQ,
816 .map = IMX8MN_OTG1_A53_DOMAIN,
817 },
818 .pgc = IMX8MN_PGC_OTG1,
819 },
820
821 [IMX8MN_POWER_DOMAIN_GPUMIX] = {
822 .genpd = {
823 .name = "gpumix",
824 },
825 .bits = {
826 .pxx = IMX8MN_GPUMIX_SW_Pxx_REQ,
827 .map = IMX8MN_GPUMIX_A53_DOMAIN,
828 .hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN,
829 .hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN,
830 },
831 .pgc = IMX8MN_PGC_GPUMIX,
832 },
833 };
834
835 static const struct regmap_range imx8mn_yes_ranges[] = {
836 regmap_reg_range(GPC_LPCR_A_CORE_BSC,
837 GPC_PU_PWRHSK),
838 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_MIPI),
839 GPC_PGC_SR(IMX8MN_PGC_MIPI)),
840 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_OTG1),
841 GPC_PGC_SR(IMX8MN_PGC_OTG1)),
842 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DDR1),
843 GPC_PGC_SR(IMX8MN_PGC_DDR1)),
844 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_GPUMIX),
845 GPC_PGC_SR(IMX8MN_PGC_GPUMIX)),
846 regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DISPMIX),
847 GPC_PGC_SR(IMX8MN_PGC_DISPMIX)),
848 };
849
850 static const struct regmap_access_table imx8mn_access_table = {
851 .yes_ranges = imx8mn_yes_ranges,
852 .n_yes_ranges = ARRAY_SIZE(imx8mn_yes_ranges),
853 };
854
855 static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
856 .domains = imx8mn_pgc_domains,
857 .domains_num = ARRAY_SIZE(imx8mn_pgc_domains),
858 .reg_access_table = &imx8mn_access_table,
859 };
860
imx_pgc_domain_probe(struct platform_device * pdev)861 static int imx_pgc_domain_probe(struct platform_device *pdev)
862 {
863 struct imx_pgc_domain *domain = pdev->dev.platform_data;
864 int ret;
865
866 domain->dev = &pdev->dev;
867
868 domain->regulator = devm_regulator_get_optional(domain->dev, "power");
869 if (IS_ERR(domain->regulator)) {
870 if (PTR_ERR(domain->regulator) != -ENODEV)
871 return dev_err_probe(domain->dev, PTR_ERR(domain->regulator),
872 "Failed to get domain's regulator\n");
873 } else if (domain->voltage) {
874 regulator_set_voltage(domain->regulator,
875 domain->voltage, domain->voltage);
876 }
877
878 domain->num_clks = devm_clk_bulk_get_all(domain->dev, &domain->clks);
879 if (domain->num_clks < 0)
880 return dev_err_probe(domain->dev, domain->num_clks,
881 "Failed to get domain's clocks\n");
882
883 domain->reset = devm_reset_control_array_get_optional_exclusive(domain->dev);
884 if (IS_ERR(domain->reset))
885 return dev_err_probe(domain->dev, PTR_ERR(domain->reset),
886 "Failed to get domain's resets\n");
887
888 pm_runtime_enable(domain->dev);
889
890 if (domain->bits.map)
891 regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
892 domain->bits.map, domain->bits.map);
893
894 ret = pm_genpd_init(&domain->genpd, NULL, true);
895 if (ret) {
896 dev_err(domain->dev, "Failed to init power domain\n");
897 goto out_domain_unmap;
898 }
899
900 ret = of_genpd_add_provider_simple(domain->dev->of_node,
901 &domain->genpd);
902 if (ret) {
903 dev_err(domain->dev, "Failed to add genpd provider\n");
904 goto out_genpd_remove;
905 }
906
907 return 0;
908
909 out_genpd_remove:
910 pm_genpd_remove(&domain->genpd);
911 out_domain_unmap:
912 if (domain->bits.map)
913 regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
914 domain->bits.map, 0);
915 pm_runtime_disable(domain->dev);
916
917 return ret;
918 }
919
imx_pgc_domain_remove(struct platform_device * pdev)920 static int imx_pgc_domain_remove(struct platform_device *pdev)
921 {
922 struct imx_pgc_domain *domain = pdev->dev.platform_data;
923
924 of_genpd_del_provider(domain->dev->of_node);
925 pm_genpd_remove(&domain->genpd);
926
927 if (domain->bits.map)
928 regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
929 domain->bits.map, 0);
930
931 pm_runtime_disable(domain->dev);
932
933 return 0;
934 }
935
936 static const struct platform_device_id imx_pgc_domain_id[] = {
937 { "imx-pgc-domain", },
938 { },
939 };
940
941 static struct platform_driver imx_pgc_domain_driver = {
942 .driver = {
943 .name = "imx-pgc",
944 },
945 .probe = imx_pgc_domain_probe,
946 .remove = imx_pgc_domain_remove,
947 .id_table = imx_pgc_domain_id,
948 };
builtin_platform_driver(imx_pgc_domain_driver)949 builtin_platform_driver(imx_pgc_domain_driver)
950
951 static int imx_gpcv2_probe(struct platform_device *pdev)
952 {
953 const struct imx_pgc_domain_data *domain_data =
954 of_device_get_match_data(&pdev->dev);
955
956 struct regmap_config regmap_config = {
957 .reg_bits = 32,
958 .val_bits = 32,
959 .reg_stride = 4,
960 .rd_table = domain_data->reg_access_table,
961 .wr_table = domain_data->reg_access_table,
962 .max_register = SZ_4K,
963 };
964 struct device *dev = &pdev->dev;
965 struct device_node *pgc_np, *np;
966 struct regmap *regmap;
967 void __iomem *base;
968 int ret;
969
970 pgc_np = of_get_child_by_name(dev->of_node, "pgc");
971 if (!pgc_np) {
972 dev_err(dev, "No power domains specified in DT\n");
973 return -EINVAL;
974 }
975
976 base = devm_platform_ioremap_resource(pdev, 0);
977 if (IS_ERR(base))
978 return PTR_ERR(base);
979
980 regmap = devm_regmap_init_mmio(dev, base, ®map_config);
981 if (IS_ERR(regmap)) {
982 ret = PTR_ERR(regmap);
983 dev_err(dev, "failed to init regmap (%d)\n", ret);
984 return ret;
985 }
986
987 for_each_child_of_node(pgc_np, np) {
988 struct platform_device *pd_pdev;
989 struct imx_pgc_domain *domain;
990 u32 domain_index;
991
992 ret = of_property_read_u32(np, "reg", &domain_index);
993 if (ret) {
994 dev_err(dev, "Failed to read 'reg' property\n");
995 of_node_put(np);
996 return ret;
997 }
998
999 if (domain_index >= domain_data->domains_num) {
1000 dev_warn(dev,
1001 "Domain index %d is out of bounds\n",
1002 domain_index);
1003 continue;
1004 }
1005
1006 pd_pdev = platform_device_alloc("imx-pgc-domain",
1007 domain_index);
1008 if (!pd_pdev) {
1009 dev_err(dev, "Failed to allocate platform device\n");
1010 of_node_put(np);
1011 return -ENOMEM;
1012 }
1013
1014 ret = platform_device_add_data(pd_pdev,
1015 &domain_data->domains[domain_index],
1016 sizeof(domain_data->domains[domain_index]));
1017 if (ret) {
1018 platform_device_put(pd_pdev);
1019 of_node_put(np);
1020 return ret;
1021 }
1022
1023 domain = pd_pdev->dev.platform_data;
1024 domain->regmap = regmap;
1025 domain->genpd.power_on = imx_pgc_power_up;
1026 domain->genpd.power_off = imx_pgc_power_down;
1027
1028 pd_pdev->dev.parent = dev;
1029 pd_pdev->dev.of_node = np;
1030
1031 ret = platform_device_add(pd_pdev);
1032 if (ret) {
1033 platform_device_put(pd_pdev);
1034 of_node_put(np);
1035 return ret;
1036 }
1037 }
1038
1039 return 0;
1040 }
1041
1042 static const struct of_device_id imx_gpcv2_dt_ids[] = {
1043 { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
1044 { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
1045 { .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
1046 { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
1047 { }
1048 };
1049
1050 static struct platform_driver imx_gpc_driver = {
1051 .driver = {
1052 .name = "imx-gpcv2",
1053 .of_match_table = imx_gpcv2_dt_ids,
1054 },
1055 .probe = imx_gpcv2_probe,
1056 };
1057 builtin_platform_driver(imx_gpc_driver)
1058