1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Local APIC handling, local APIC timers
4 *
5 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 *
7 * Fixes
8 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
9 * thanks to Eric Gilmore
10 * and Rolf G. Tews
11 * for testing these extensively.
12 * Maciej W. Rozycki : Various updates and fixes.
13 * Mikael Pettersson : Power Management for UP-APIC.
14 * Pavel Machek and
15 * Mikael Pettersson : PM converted to driver model.
16 */
17
18 #include <linux/perf_event.h>
19 #include <linux/kernel_stat.h>
20 #include <linux/mc146818rtc.h>
21 #include <linux/acpi_pmtmr.h>
22 #include <linux/clockchips.h>
23 #include <linux/interrupt.h>
24 #include <linux/memblock.h>
25 #include <linux/ftrace.h>
26 #include <linux/ioport.h>
27 #include <linux/export.h>
28 #include <linux/syscore_ops.h>
29 #include <linux/delay.h>
30 #include <linux/timex.h>
31 #include <linux/i8253.h>
32 #include <linux/dmar.h>
33 #include <linux/init.h>
34 #include <linux/cpu.h>
35 #include <linux/dmi.h>
36 #include <linux/smp.h>
37 #include <linux/mm.h>
38
39 #include <asm/trace/irq_vectors.h>
40 #include <asm/irq_remapping.h>
41 #include <asm/pc-conf-reg.h>
42 #include <asm/perf_event.h>
43 #include <asm/x86_init.h>
44 #include <linux/atomic.h>
45 #include <asm/barrier.h>
46 #include <asm/mpspec.h>
47 #include <asm/i8259.h>
48 #include <asm/proto.h>
49 #include <asm/traps.h>
50 #include <asm/apic.h>
51 #include <asm/acpi.h>
52 #include <asm/io_apic.h>
53 #include <asm/desc.h>
54 #include <asm/hpet.h>
55 #include <asm/mtrr.h>
56 #include <asm/time.h>
57 #include <asm/smp.h>
58 #include <asm/mce.h>
59 #include <asm/tsc.h>
60 #include <asm/hypervisor.h>
61 #include <asm/cpu_device_id.h>
62 #include <asm/intel-family.h>
63 #include <asm/irq_regs.h>
64
65 unsigned int num_processors;
66
67 unsigned disabled_cpus;
68
69 /* Processor that is doing the boot up */
70 unsigned int boot_cpu_physical_apicid __ro_after_init = -1U;
71 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
72
73 u8 boot_cpu_apic_version __ro_after_init;
74
75 /*
76 * The highest APIC ID seen during enumeration.
77 */
78 static unsigned int max_physical_apicid;
79
80 /*
81 * Bitmask of physically existing CPUs:
82 */
83 physid_mask_t phys_cpu_present_map;
84
85 /*
86 * Processor to be disabled specified by kernel parameter
87 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
88 * avoid undefined behaviour caused by sending INIT from AP to BSP.
89 */
90 static unsigned int disabled_cpu_apicid __ro_after_init = BAD_APICID;
91
92 /*
93 * This variable controls which CPUs receive external NMIs. By default,
94 * external NMIs are delivered only to the BSP.
95 */
96 static int apic_extnmi __ro_after_init = APIC_EXTNMI_BSP;
97
98 /*
99 * Hypervisor supports 15 bits of APIC ID in MSI Extended Destination ID
100 */
101 static bool virt_ext_dest_id __ro_after_init;
102
103 /*
104 * Map cpu index to physical APIC ID
105 */
106 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
107 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
108 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
109 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
110 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
111 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
112
113 #ifdef CONFIG_X86_32
114
115 /*
116 * On x86_32, the mapping between cpu and logical apicid may vary
117 * depending on apic in use. The following early percpu variable is
118 * used for the mapping. This is where the behaviors of x86_64 and 32
119 * actually diverge. Let's keep it ugly for now.
120 */
121 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
122
123 /* Local APIC was disabled by the BIOS and enabled by the kernel */
124 static int enabled_via_apicbase __ro_after_init;
125
126 /*
127 * Handle interrupt mode configuration register (IMCR).
128 * This register controls whether the interrupt signals
129 * that reach the BSP come from the master PIC or from the
130 * local APIC. Before entering Symmetric I/O Mode, either
131 * the BIOS or the operating system must switch out of
132 * PIC Mode by changing the IMCR.
133 */
imcr_pic_to_apic(void)134 static inline void imcr_pic_to_apic(void)
135 {
136 /* NMI and 8259 INTR go through APIC */
137 pc_conf_set(PC_CONF_MPS_IMCR, 0x01);
138 }
139
imcr_apic_to_pic(void)140 static inline void imcr_apic_to_pic(void)
141 {
142 /* NMI and 8259 INTR go directly to BSP */
143 pc_conf_set(PC_CONF_MPS_IMCR, 0x00);
144 }
145 #endif
146
147 /*
148 * Knob to control our willingness to enable the local APIC.
149 *
150 * +1=force-enable
151 */
152 static int force_enable_local_apic __initdata;
153
154 /*
155 * APIC command line parameters
156 */
parse_lapic(char * arg)157 static int __init parse_lapic(char *arg)
158 {
159 if (IS_ENABLED(CONFIG_X86_32) && !arg)
160 force_enable_local_apic = 1;
161 else if (arg && !strncmp(arg, "notscdeadline", 13))
162 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
163 return 0;
164 }
165 early_param("lapic", parse_lapic);
166
167 #ifdef CONFIG_X86_64
168 static int apic_calibrate_pmtmr __initdata;
setup_apicpmtimer(char * s)169 static __init int setup_apicpmtimer(char *s)
170 {
171 apic_calibrate_pmtmr = 1;
172 notsc_setup(NULL);
173 return 1;
174 }
175 __setup("apicpmtimer", setup_apicpmtimer);
176 #endif
177
178 unsigned long mp_lapic_addr __ro_after_init;
179 int disable_apic __ro_after_init;
180 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
181 static int disable_apic_timer __initdata;
182 /* Local APIC timer works in C2 */
183 int local_apic_timer_c2_ok __ro_after_init;
184 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
185
186 /*
187 * Debug level, exported for io_apic.c
188 */
189 int apic_verbosity __ro_after_init;
190
191 int pic_mode __ro_after_init;
192
193 /* Have we found an MP table */
194 int smp_found_config __ro_after_init;
195
196 static struct resource lapic_resource = {
197 .name = "Local APIC",
198 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
199 };
200
201 unsigned int lapic_timer_period = 0;
202
203 static void apic_pm_activate(void);
204
205 static unsigned long apic_phys __ro_after_init;
206
207 /*
208 * Get the LAPIC version
209 */
lapic_get_version(void)210 static inline int lapic_get_version(void)
211 {
212 return GET_APIC_VERSION(apic_read(APIC_LVR));
213 }
214
215 /*
216 * Check, if the APIC is integrated or a separate chip
217 */
lapic_is_integrated(void)218 static inline int lapic_is_integrated(void)
219 {
220 return APIC_INTEGRATED(lapic_get_version());
221 }
222
223 /*
224 * Check, whether this is a modern or a first generation APIC
225 */
modern_apic(void)226 static int modern_apic(void)
227 {
228 /* AMD systems use old APIC versions, so check the CPU */
229 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
230 boot_cpu_data.x86 >= 0xf)
231 return 1;
232
233 /* Hygon systems use modern APIC */
234 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
235 return 1;
236
237 return lapic_get_version() >= 0x14;
238 }
239
240 /*
241 * right after this call apic become NOOP driven
242 * so apic->write/read doesn't do anything
243 */
apic_disable(void)244 static void __init apic_disable(void)
245 {
246 pr_info("APIC: switched to apic NOOP\n");
247 apic = &apic_noop;
248 }
249
native_apic_wait_icr_idle(void)250 void native_apic_wait_icr_idle(void)
251 {
252 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
253 cpu_relax();
254 }
255
native_safe_apic_wait_icr_idle(void)256 u32 native_safe_apic_wait_icr_idle(void)
257 {
258 u32 send_status;
259 int timeout;
260
261 timeout = 0;
262 do {
263 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
264 if (!send_status)
265 break;
266 inc_irq_stat(icr_read_retry_count);
267 udelay(100);
268 } while (timeout++ < 1000);
269
270 return send_status;
271 }
272
native_apic_icr_write(u32 low,u32 id)273 void native_apic_icr_write(u32 low, u32 id)
274 {
275 unsigned long flags;
276
277 local_irq_save(flags);
278 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
279 apic_write(APIC_ICR, low);
280 local_irq_restore(flags);
281 }
282
native_apic_icr_read(void)283 u64 native_apic_icr_read(void)
284 {
285 u32 icr1, icr2;
286
287 icr2 = apic_read(APIC_ICR2);
288 icr1 = apic_read(APIC_ICR);
289
290 return icr1 | ((u64)icr2 << 32);
291 }
292
293 #ifdef CONFIG_X86_32
294 /**
295 * get_physical_broadcast - Get number of physical broadcast IDs
296 */
get_physical_broadcast(void)297 int get_physical_broadcast(void)
298 {
299 return modern_apic() ? 0xff : 0xf;
300 }
301 #endif
302
303 /**
304 * lapic_get_maxlvt - get the maximum number of local vector table entries
305 */
lapic_get_maxlvt(void)306 int lapic_get_maxlvt(void)
307 {
308 /*
309 * - we always have APIC integrated on 64bit mode
310 * - 82489DXs do not report # of LVT entries
311 */
312 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2;
313 }
314
315 /*
316 * Local APIC timer
317 */
318
319 /* Clock divisor */
320 #define APIC_DIVISOR 16
321 #define TSC_DIVISOR 8
322
323 /*
324 * This function sets up the local APIC timer, with a timeout of
325 * 'clocks' APIC bus clock. During calibration we actually call
326 * this function twice on the boot CPU, once with a bogus timeout
327 * value, second time for real. The other (noncalibrating) CPUs
328 * call this function only once, with the real, calibrated value.
329 *
330 * We do reads before writes even if unnecessary, to get around the
331 * P5 APIC double write bug.
332 */
__setup_APIC_LVTT(unsigned int clocks,int oneshot,int irqen)333 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
334 {
335 unsigned int lvtt_value, tmp_value;
336
337 lvtt_value = LOCAL_TIMER_VECTOR;
338 if (!oneshot)
339 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
340 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
341 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
342
343 if (!lapic_is_integrated())
344 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
345
346 if (!irqen)
347 lvtt_value |= APIC_LVT_MASKED;
348
349 apic_write(APIC_LVTT, lvtt_value);
350
351 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
352 /*
353 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
354 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
355 * According to Intel, MFENCE can do the serialization here.
356 */
357 asm volatile("mfence" : : : "memory");
358 return;
359 }
360
361 /*
362 * Divide PICLK by 16
363 */
364 tmp_value = apic_read(APIC_TDCR);
365 apic_write(APIC_TDCR,
366 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
367 APIC_TDR_DIV_16);
368
369 if (!oneshot)
370 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
371 }
372
373 /*
374 * Setup extended LVT, AMD specific
375 *
376 * Software should use the LVT offsets the BIOS provides. The offsets
377 * are determined by the subsystems using it like those for MCE
378 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
379 * are supported. Beginning with family 10h at least 4 offsets are
380 * available.
381 *
382 * Since the offsets must be consistent for all cores, we keep track
383 * of the LVT offsets in software and reserve the offset for the same
384 * vector also to be used on other cores. An offset is freed by
385 * setting the entry to APIC_EILVT_MASKED.
386 *
387 * If the BIOS is right, there should be no conflicts. Otherwise a
388 * "[Firmware Bug]: ..." error message is generated. However, if
389 * software does not properly determines the offsets, it is not
390 * necessarily a BIOS bug.
391 */
392
393 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
394
eilvt_entry_is_changeable(unsigned int old,unsigned int new)395 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
396 {
397 return (old & APIC_EILVT_MASKED)
398 || (new == APIC_EILVT_MASKED)
399 || ((new & ~APIC_EILVT_MASKED) == old);
400 }
401
reserve_eilvt_offset(int offset,unsigned int new)402 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
403 {
404 unsigned int rsvd, vector;
405
406 if (offset >= APIC_EILVT_NR_MAX)
407 return ~0;
408
409 rsvd = atomic_read(&eilvt_offsets[offset]);
410 do {
411 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
412 if (vector && !eilvt_entry_is_changeable(vector, new))
413 /* may not change if vectors are different */
414 return rsvd;
415 } while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new));
416
417 rsvd = new & ~APIC_EILVT_MASKED;
418 if (rsvd && rsvd != vector)
419 pr_info("LVT offset %d assigned for vector 0x%02x\n",
420 offset, rsvd);
421
422 return new;
423 }
424
425 /*
426 * If mask=1, the LVT entry does not generate interrupts while mask=0
427 * enables the vector. See also the BKDGs. Must be called with
428 * preemption disabled.
429 */
430
setup_APIC_eilvt(u8 offset,u8 vector,u8 msg_type,u8 mask)431 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
432 {
433 unsigned long reg = APIC_EILVTn(offset);
434 unsigned int new, old, reserved;
435
436 new = (mask << 16) | (msg_type << 8) | vector;
437 old = apic_read(reg);
438 reserved = reserve_eilvt_offset(offset, new);
439
440 if (reserved != new) {
441 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
442 "vector 0x%x, but the register is already in use for "
443 "vector 0x%x on another cpu\n",
444 smp_processor_id(), reg, offset, new, reserved);
445 return -EINVAL;
446 }
447
448 if (!eilvt_entry_is_changeable(old, new)) {
449 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
450 "vector 0x%x, but the register is already in use for "
451 "vector 0x%x on this cpu\n",
452 smp_processor_id(), reg, offset, new, old);
453 return -EBUSY;
454 }
455
456 apic_write(reg, new);
457
458 return 0;
459 }
460 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
461
462 /*
463 * Program the next event, relative to now
464 */
lapic_next_event(unsigned long delta,struct clock_event_device * evt)465 static int lapic_next_event(unsigned long delta,
466 struct clock_event_device *evt)
467 {
468 apic_write(APIC_TMICT, delta);
469 return 0;
470 }
471
lapic_next_deadline(unsigned long delta,struct clock_event_device * evt)472 static int lapic_next_deadline(unsigned long delta,
473 struct clock_event_device *evt)
474 {
475 u64 tsc;
476
477 /* This MSR is special and need a special fence: */
478 weak_wrmsr_fence();
479
480 tsc = rdtsc();
481 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
482 return 0;
483 }
484
lapic_timer_shutdown(struct clock_event_device * evt)485 static int lapic_timer_shutdown(struct clock_event_device *evt)
486 {
487 unsigned int v;
488
489 /* Lapic used as dummy for broadcast ? */
490 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
491 return 0;
492
493 v = apic_read(APIC_LVTT);
494 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
495 apic_write(APIC_LVTT, v);
496 apic_write(APIC_TMICT, 0);
497 return 0;
498 }
499
500 static inline int
lapic_timer_set_periodic_oneshot(struct clock_event_device * evt,bool oneshot)501 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
502 {
503 /* Lapic used as dummy for broadcast ? */
504 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
505 return 0;
506
507 __setup_APIC_LVTT(lapic_timer_period, oneshot, 1);
508 return 0;
509 }
510
lapic_timer_set_periodic(struct clock_event_device * evt)511 static int lapic_timer_set_periodic(struct clock_event_device *evt)
512 {
513 return lapic_timer_set_periodic_oneshot(evt, false);
514 }
515
lapic_timer_set_oneshot(struct clock_event_device * evt)516 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
517 {
518 return lapic_timer_set_periodic_oneshot(evt, true);
519 }
520
521 /*
522 * Local APIC timer broadcast function
523 */
lapic_timer_broadcast(const struct cpumask * mask)524 static void lapic_timer_broadcast(const struct cpumask *mask)
525 {
526 #ifdef CONFIG_SMP
527 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
528 #endif
529 }
530
531
532 /*
533 * The local apic timer can be used for any function which is CPU local.
534 */
535 static struct clock_event_device lapic_clockevent = {
536 .name = "lapic",
537 .features = CLOCK_EVT_FEAT_PERIODIC |
538 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
539 | CLOCK_EVT_FEAT_DUMMY,
540 .shift = 32,
541 .set_state_shutdown = lapic_timer_shutdown,
542 .set_state_periodic = lapic_timer_set_periodic,
543 .set_state_oneshot = lapic_timer_set_oneshot,
544 .set_state_oneshot_stopped = lapic_timer_shutdown,
545 .set_next_event = lapic_next_event,
546 .broadcast = lapic_timer_broadcast,
547 .rating = 100,
548 .irq = -1,
549 };
550 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
551
552 static const struct x86_cpu_id deadline_match[] __initconst = {
553 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x2, 0x2), 0x3a), /* EP */
554 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x4, 0x4), 0x0f), /* EX */
555
556 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_X, 0x0b000020),
557
558 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x2, 0x2), 0x00000011),
559 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x3, 0x3), 0x0700000e),
560 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x4, 0x4), 0x0f00000c),
561 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x5, 0x5), 0x0e000003),
562
563 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x3, 0x3), 0x01000136),
564 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x4, 0x4), 0x02000014),
565 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x5, 0xf), 0),
566
567 X86_MATCH_INTEL_FAM6_MODEL( HASWELL, 0x22),
568 X86_MATCH_INTEL_FAM6_MODEL( HASWELL_L, 0x20),
569 X86_MATCH_INTEL_FAM6_MODEL( HASWELL_G, 0x17),
570
571 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL, 0x25),
572 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_G, 0x17),
573
574 X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE_L, 0xb2),
575 X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE, 0xb2),
576
577 X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE_L, 0x52),
578 X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE, 0x52),
579
580 {},
581 };
582
apic_validate_deadline_timer(void)583 static __init bool apic_validate_deadline_timer(void)
584 {
585 const struct x86_cpu_id *m;
586 u32 rev;
587
588 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
589 return false;
590 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
591 return true;
592
593 m = x86_match_cpu(deadline_match);
594 if (!m)
595 return true;
596
597 rev = (u32)m->driver_data;
598
599 if (boot_cpu_data.microcode >= rev)
600 return true;
601
602 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
603 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
604 "please update microcode to version: 0x%x (or later)\n", rev);
605 return false;
606 }
607
608 /*
609 * Setup the local APIC timer for this CPU. Copy the initialized values
610 * of the boot CPU and register the clock event in the framework.
611 */
setup_APIC_timer(void)612 static void setup_APIC_timer(void)
613 {
614 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
615
616 if (this_cpu_has(X86_FEATURE_ARAT)) {
617 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
618 /* Make LAPIC timer preferable over percpu HPET */
619 lapic_clockevent.rating = 150;
620 }
621
622 memcpy(levt, &lapic_clockevent, sizeof(*levt));
623 levt->cpumask = cpumask_of(smp_processor_id());
624
625 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
626 levt->name = "lapic-deadline";
627 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
628 CLOCK_EVT_FEAT_DUMMY);
629 levt->set_next_event = lapic_next_deadline;
630 clockevents_config_and_register(levt,
631 tsc_khz * (1000 / TSC_DIVISOR),
632 0xF, ~0UL);
633 } else
634 clockevents_register_device(levt);
635 }
636
637 /*
638 * Install the updated TSC frequency from recalibration at the TSC
639 * deadline clockevent devices.
640 */
__lapic_update_tsc_freq(void * info)641 static void __lapic_update_tsc_freq(void *info)
642 {
643 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
644
645 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
646 return;
647
648 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
649 }
650
lapic_update_tsc_freq(void)651 void lapic_update_tsc_freq(void)
652 {
653 /*
654 * The clockevent device's ->mult and ->shift can both be
655 * changed. In order to avoid races, schedule the frequency
656 * update code on each CPU.
657 */
658 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
659 }
660
661 /*
662 * In this functions we calibrate APIC bus clocks to the external timer.
663 *
664 * We want to do the calibration only once since we want to have local timer
665 * irqs synchronous. CPUs connected by the same APIC bus have the very same bus
666 * frequency.
667 *
668 * This was previously done by reading the PIT/HPET and waiting for a wrap
669 * around to find out, that a tick has elapsed. I have a box, where the PIT
670 * readout is broken, so it never gets out of the wait loop again. This was
671 * also reported by others.
672 *
673 * Monitoring the jiffies value is inaccurate and the clockevents
674 * infrastructure allows us to do a simple substitution of the interrupt
675 * handler.
676 *
677 * The calibration routine also uses the pm_timer when possible, as the PIT
678 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
679 * back to normal later in the boot process).
680 */
681
682 #define LAPIC_CAL_LOOPS (HZ/10)
683
684 static __initdata int lapic_cal_loops = -1;
685 static __initdata long lapic_cal_t1, lapic_cal_t2;
686 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
687 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
688 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
689
690 /*
691 * Temporary interrupt handler and polled calibration function.
692 */
lapic_cal_handler(struct clock_event_device * dev)693 static void __init lapic_cal_handler(struct clock_event_device *dev)
694 {
695 unsigned long long tsc = 0;
696 long tapic = apic_read(APIC_TMCCT);
697 unsigned long pm = acpi_pm_read_early();
698
699 if (boot_cpu_has(X86_FEATURE_TSC))
700 tsc = rdtsc();
701
702 switch (lapic_cal_loops++) {
703 case 0:
704 lapic_cal_t1 = tapic;
705 lapic_cal_tsc1 = tsc;
706 lapic_cal_pm1 = pm;
707 lapic_cal_j1 = jiffies;
708 break;
709
710 case LAPIC_CAL_LOOPS:
711 lapic_cal_t2 = tapic;
712 lapic_cal_tsc2 = tsc;
713 if (pm < lapic_cal_pm1)
714 pm += ACPI_PM_OVRRUN;
715 lapic_cal_pm2 = pm;
716 lapic_cal_j2 = jiffies;
717 break;
718 }
719 }
720
721 static int __init
calibrate_by_pmtimer(long deltapm,long * delta,long * deltatsc)722 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
723 {
724 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
725 const long pm_thresh = pm_100ms / 100;
726 unsigned long mult;
727 u64 res;
728
729 #ifndef CONFIG_X86_PM_TIMER
730 return -1;
731 #endif
732
733 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
734
735 /* Check, if the PM timer is available */
736 if (!deltapm)
737 return -1;
738
739 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
740
741 if (deltapm > (pm_100ms - pm_thresh) &&
742 deltapm < (pm_100ms + pm_thresh)) {
743 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
744 return 0;
745 }
746
747 res = (((u64)deltapm) * mult) >> 22;
748 do_div(res, 1000000);
749 pr_warn("APIC calibration not consistent "
750 "with PM-Timer: %ldms instead of 100ms\n", (long)res);
751
752 /* Correct the lapic counter value */
753 res = (((u64)(*delta)) * pm_100ms);
754 do_div(res, deltapm);
755 pr_info("APIC delta adjusted to PM-Timer: "
756 "%lu (%ld)\n", (unsigned long)res, *delta);
757 *delta = (long)res;
758
759 /* Correct the tsc counter value */
760 if (boot_cpu_has(X86_FEATURE_TSC)) {
761 res = (((u64)(*deltatsc)) * pm_100ms);
762 do_div(res, deltapm);
763 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
764 "PM-Timer: %lu (%ld)\n",
765 (unsigned long)res, *deltatsc);
766 *deltatsc = (long)res;
767 }
768
769 return 0;
770 }
771
lapic_init_clockevent(void)772 static int __init lapic_init_clockevent(void)
773 {
774 if (!lapic_timer_period)
775 return -1;
776
777 /* Calculate the scaled math multiplication factor */
778 lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR,
779 TICK_NSEC, lapic_clockevent.shift);
780 lapic_clockevent.max_delta_ns =
781 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
782 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
783 lapic_clockevent.min_delta_ns =
784 clockevent_delta2ns(0xF, &lapic_clockevent);
785 lapic_clockevent.min_delta_ticks = 0xF;
786
787 return 0;
788 }
789
apic_needs_pit(void)790 bool __init apic_needs_pit(void)
791 {
792 /*
793 * If the frequencies are not known, PIT is required for both TSC
794 * and apic timer calibration.
795 */
796 if (!tsc_khz || !cpu_khz)
797 return true;
798
799 /* Is there an APIC at all or is it disabled? */
800 if (!boot_cpu_has(X86_FEATURE_APIC) || disable_apic)
801 return true;
802
803 /*
804 * If interrupt delivery mode is legacy PIC or virtual wire without
805 * configuration, the local APIC timer wont be set up. Make sure
806 * that the PIT is initialized.
807 */
808 if (apic_intr_mode == APIC_PIC ||
809 apic_intr_mode == APIC_VIRTUAL_WIRE_NO_CONFIG)
810 return true;
811
812 /* Virt guests may lack ARAT, but still have DEADLINE */
813 if (!boot_cpu_has(X86_FEATURE_ARAT))
814 return true;
815
816 /* Deadline timer is based on TSC so no further PIT action required */
817 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
818 return false;
819
820 /* APIC timer disabled? */
821 if (disable_apic_timer)
822 return true;
823 /*
824 * The APIC timer frequency is known already, no PIT calibration
825 * required. If unknown, let the PIT be initialized.
826 */
827 return lapic_timer_period == 0;
828 }
829
calibrate_APIC_clock(void)830 static int __init calibrate_APIC_clock(void)
831 {
832 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
833 u64 tsc_perj = 0, tsc_start = 0;
834 unsigned long jif_start;
835 unsigned long deltaj;
836 long delta, deltatsc;
837 int pm_referenced = 0;
838
839 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
840 return 0;
841
842 /*
843 * Check if lapic timer has already been calibrated by platform
844 * specific routine, such as tsc calibration code. If so just fill
845 * in the clockevent structure and return.
846 */
847 if (!lapic_init_clockevent()) {
848 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
849 lapic_timer_period);
850 /*
851 * Direct calibration methods must have an always running
852 * local APIC timer, no need for broadcast timer.
853 */
854 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
855 return 0;
856 }
857
858 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
859 "calibrating APIC timer ...\n");
860
861 /*
862 * There are platforms w/o global clockevent devices. Instead of
863 * making the calibration conditional on that, use a polling based
864 * approach everywhere.
865 */
866 local_irq_disable();
867
868 /*
869 * Setup the APIC counter to maximum. There is no way the lapic
870 * can underflow in the 100ms detection time frame
871 */
872 __setup_APIC_LVTT(0xffffffff, 0, 0);
873
874 /*
875 * Methods to terminate the calibration loop:
876 * 1) Global clockevent if available (jiffies)
877 * 2) TSC if available and frequency is known
878 */
879 jif_start = READ_ONCE(jiffies);
880
881 if (tsc_khz) {
882 tsc_start = rdtsc();
883 tsc_perj = div_u64((u64)tsc_khz * 1000, HZ);
884 }
885
886 /*
887 * Enable interrupts so the tick can fire, if a global
888 * clockevent device is available
889 */
890 local_irq_enable();
891
892 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) {
893 /* Wait for a tick to elapse */
894 while (1) {
895 if (tsc_khz) {
896 u64 tsc_now = rdtsc();
897 if ((tsc_now - tsc_start) >= tsc_perj) {
898 tsc_start += tsc_perj;
899 break;
900 }
901 } else {
902 unsigned long jif_now = READ_ONCE(jiffies);
903
904 if (time_after(jif_now, jif_start)) {
905 jif_start = jif_now;
906 break;
907 }
908 }
909 cpu_relax();
910 }
911
912 /* Invoke the calibration routine */
913 local_irq_disable();
914 lapic_cal_handler(NULL);
915 local_irq_enable();
916 }
917
918 local_irq_disable();
919
920 /* Build delta t1-t2 as apic timer counts down */
921 delta = lapic_cal_t1 - lapic_cal_t2;
922 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
923
924 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
925
926 /* we trust the PM based calibration if possible */
927 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
928 &delta, &deltatsc);
929
930 lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
931 lapic_init_clockevent();
932
933 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
934 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
935 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
936 lapic_timer_period);
937
938 if (boot_cpu_has(X86_FEATURE_TSC)) {
939 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
940 "%ld.%04ld MHz.\n",
941 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
942 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
943 }
944
945 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
946 "%u.%04u MHz.\n",
947 lapic_timer_period / (1000000 / HZ),
948 lapic_timer_period % (1000000 / HZ));
949
950 /*
951 * Do a sanity check on the APIC calibration result
952 */
953 if (lapic_timer_period < (1000000 / HZ)) {
954 local_irq_enable();
955 pr_warn("APIC frequency too slow, disabling apic timer\n");
956 return -1;
957 }
958
959 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
960
961 /*
962 * PM timer calibration failed or not turned on so lets try APIC
963 * timer based calibration, if a global clockevent device is
964 * available.
965 */
966 if (!pm_referenced && global_clock_event) {
967 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
968
969 /*
970 * Setup the apic timer manually
971 */
972 levt->event_handler = lapic_cal_handler;
973 lapic_timer_set_periodic(levt);
974 lapic_cal_loops = -1;
975
976 /* Let the interrupts run */
977 local_irq_enable();
978
979 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
980 cpu_relax();
981
982 /* Stop the lapic timer */
983 local_irq_disable();
984 lapic_timer_shutdown(levt);
985
986 /* Jiffies delta */
987 deltaj = lapic_cal_j2 - lapic_cal_j1;
988 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
989
990 /* Check, if the jiffies result is consistent */
991 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
992 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
993 else
994 levt->features |= CLOCK_EVT_FEAT_DUMMY;
995 }
996 local_irq_enable();
997
998 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
999 pr_warn("APIC timer disabled due to verification failure\n");
1000 return -1;
1001 }
1002
1003 return 0;
1004 }
1005
1006 /*
1007 * Setup the boot APIC
1008 *
1009 * Calibrate and verify the result.
1010 */
setup_boot_APIC_clock(void)1011 void __init setup_boot_APIC_clock(void)
1012 {
1013 /*
1014 * The local apic timer can be disabled via the kernel
1015 * commandline or from the CPU detection code. Register the lapic
1016 * timer as a dummy clock event source on SMP systems, so the
1017 * broadcast mechanism is used. On UP systems simply ignore it.
1018 */
1019 if (disable_apic_timer) {
1020 pr_info("Disabling APIC timer\n");
1021 /* No broadcast on UP ! */
1022 if (num_possible_cpus() > 1) {
1023 lapic_clockevent.mult = 1;
1024 setup_APIC_timer();
1025 }
1026 return;
1027 }
1028
1029 if (calibrate_APIC_clock()) {
1030 /* No broadcast on UP ! */
1031 if (num_possible_cpus() > 1)
1032 setup_APIC_timer();
1033 return;
1034 }
1035
1036 /*
1037 * If nmi_watchdog is set to IO_APIC, we need the
1038 * PIT/HPET going. Otherwise register lapic as a dummy
1039 * device.
1040 */
1041 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
1042
1043 /* Setup the lapic or request the broadcast */
1044 setup_APIC_timer();
1045 amd_e400_c1e_apic_setup();
1046 }
1047
setup_secondary_APIC_clock(void)1048 void setup_secondary_APIC_clock(void)
1049 {
1050 setup_APIC_timer();
1051 amd_e400_c1e_apic_setup();
1052 }
1053
1054 /*
1055 * The guts of the apic timer interrupt
1056 */
local_apic_timer_interrupt(void)1057 static void local_apic_timer_interrupt(void)
1058 {
1059 struct clock_event_device *evt = this_cpu_ptr(&lapic_events);
1060
1061 /*
1062 * Normally we should not be here till LAPIC has been initialized but
1063 * in some cases like kdump, its possible that there is a pending LAPIC
1064 * timer interrupt from previous kernel's context and is delivered in
1065 * new kernel the moment interrupts are enabled.
1066 *
1067 * Interrupts are enabled early and LAPIC is setup much later, hence
1068 * its possible that when we get here evt->event_handler is NULL.
1069 * Check for event_handler being NULL and discard the interrupt as
1070 * spurious.
1071 */
1072 if (!evt->event_handler) {
1073 pr_warn("Spurious LAPIC timer interrupt on cpu %d\n",
1074 smp_processor_id());
1075 /* Switch it off */
1076 lapic_timer_shutdown(evt);
1077 return;
1078 }
1079
1080 /*
1081 * the NMI deadlock-detector uses this.
1082 */
1083 inc_irq_stat(apic_timer_irqs);
1084
1085 evt->event_handler(evt);
1086 }
1087
1088 /*
1089 * Local APIC timer interrupt. This is the most natural way for doing
1090 * local interrupts, but local timer interrupts can be emulated by
1091 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1092 *
1093 * [ if a single-CPU system runs an SMP kernel then we call the local
1094 * interrupt as well. Thus we cannot inline the local irq ... ]
1095 */
DEFINE_IDTENTRY_SYSVEC(sysvec_apic_timer_interrupt)1096 DEFINE_IDTENTRY_SYSVEC(sysvec_apic_timer_interrupt)
1097 {
1098 struct pt_regs *old_regs = set_irq_regs(regs);
1099
1100 ack_APIC_irq();
1101 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1102 local_apic_timer_interrupt();
1103 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1104
1105 set_irq_regs(old_regs);
1106 }
1107
setup_profiling_timer(unsigned int multiplier)1108 int setup_profiling_timer(unsigned int multiplier)
1109 {
1110 return -EINVAL;
1111 }
1112
1113 /*
1114 * Local APIC start and shutdown
1115 */
1116
1117 /**
1118 * clear_local_APIC - shutdown the local APIC
1119 *
1120 * This is called, when a CPU is disabled and before rebooting, so the state of
1121 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1122 * leftovers during boot.
1123 */
clear_local_APIC(void)1124 void clear_local_APIC(void)
1125 {
1126 int maxlvt;
1127 u32 v;
1128
1129 /* APIC hasn't been mapped yet */
1130 if (!x2apic_mode && !apic_phys)
1131 return;
1132
1133 maxlvt = lapic_get_maxlvt();
1134 /*
1135 * Masking an LVT entry can trigger a local APIC error
1136 * if the vector is zero. Mask LVTERR first to prevent this.
1137 */
1138 if (maxlvt >= 3) {
1139 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1140 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1141 }
1142 /*
1143 * Careful: we have to set masks only first to deassert
1144 * any level-triggered sources.
1145 */
1146 v = apic_read(APIC_LVTT);
1147 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1148 v = apic_read(APIC_LVT0);
1149 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1150 v = apic_read(APIC_LVT1);
1151 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1152 if (maxlvt >= 4) {
1153 v = apic_read(APIC_LVTPC);
1154 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1155 }
1156
1157 /* lets not touch this if we didn't frob it */
1158 #ifdef CONFIG_X86_THERMAL_VECTOR
1159 if (maxlvt >= 5) {
1160 v = apic_read(APIC_LVTTHMR);
1161 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1162 }
1163 #endif
1164 #ifdef CONFIG_X86_MCE_INTEL
1165 if (maxlvt >= 6) {
1166 v = apic_read(APIC_LVTCMCI);
1167 if (!(v & APIC_LVT_MASKED))
1168 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1169 }
1170 #endif
1171
1172 /*
1173 * Clean APIC state for other OSs:
1174 */
1175 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1176 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1177 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1178 if (maxlvt >= 3)
1179 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1180 if (maxlvt >= 4)
1181 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1182
1183 /* Integrated APIC (!82489DX) ? */
1184 if (lapic_is_integrated()) {
1185 if (maxlvt > 3)
1186 /* Clear ESR due to Pentium errata 3AP and 11AP */
1187 apic_write(APIC_ESR, 0);
1188 apic_read(APIC_ESR);
1189 }
1190 }
1191
1192 /**
1193 * apic_soft_disable - Clears and software disables the local APIC on hotplug
1194 *
1195 * Contrary to disable_local_APIC() this does not touch the enable bit in
1196 * MSR_IA32_APICBASE. Clearing that bit on systems based on the 3 wire APIC
1197 * bus would require a hardware reset as the APIC would lose track of bus
1198 * arbitration. On systems with FSB delivery APICBASE could be disabled,
1199 * but it has to be guaranteed that no interrupt is sent to the APIC while
1200 * in that state and it's not clear from the SDM whether it still responds
1201 * to INIT/SIPI messages. Stay on the safe side and use software disable.
1202 */
apic_soft_disable(void)1203 void apic_soft_disable(void)
1204 {
1205 u32 value;
1206
1207 clear_local_APIC();
1208
1209 /* Soft disable APIC (implies clearing of registers for 82489DX!). */
1210 value = apic_read(APIC_SPIV);
1211 value &= ~APIC_SPIV_APIC_ENABLED;
1212 apic_write(APIC_SPIV, value);
1213 }
1214
1215 /**
1216 * disable_local_APIC - clear and disable the local APIC
1217 */
disable_local_APIC(void)1218 void disable_local_APIC(void)
1219 {
1220 /* APIC hasn't been mapped yet */
1221 if (!x2apic_mode && !apic_phys)
1222 return;
1223
1224 apic_soft_disable();
1225
1226 #ifdef CONFIG_X86_32
1227 /*
1228 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1229 * restore the disabled state.
1230 */
1231 if (enabled_via_apicbase) {
1232 unsigned int l, h;
1233
1234 rdmsr(MSR_IA32_APICBASE, l, h);
1235 l &= ~MSR_IA32_APICBASE_ENABLE;
1236 wrmsr(MSR_IA32_APICBASE, l, h);
1237 }
1238 #endif
1239 }
1240
1241 /*
1242 * If Linux enabled the LAPIC against the BIOS default disable it down before
1243 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1244 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1245 * for the case where Linux didn't enable the LAPIC.
1246 */
lapic_shutdown(void)1247 void lapic_shutdown(void)
1248 {
1249 unsigned long flags;
1250
1251 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1252 return;
1253
1254 local_irq_save(flags);
1255
1256 #ifdef CONFIG_X86_32
1257 if (!enabled_via_apicbase)
1258 clear_local_APIC();
1259 else
1260 #endif
1261 disable_local_APIC();
1262
1263
1264 local_irq_restore(flags);
1265 }
1266
1267 /**
1268 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1269 */
sync_Arb_IDs(void)1270 void __init sync_Arb_IDs(void)
1271 {
1272 /*
1273 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1274 * needed on AMD.
1275 */
1276 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1277 return;
1278
1279 /*
1280 * Wait for idle.
1281 */
1282 apic_wait_icr_idle();
1283
1284 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1285 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1286 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1287 }
1288
1289 enum apic_intr_mode_id apic_intr_mode __ro_after_init;
1290
__apic_intr_mode_select(void)1291 static int __init __apic_intr_mode_select(void)
1292 {
1293 /* Check kernel option */
1294 if (disable_apic) {
1295 pr_info("APIC disabled via kernel command line\n");
1296 return APIC_PIC;
1297 }
1298
1299 /* Check BIOS */
1300 #ifdef CONFIG_X86_64
1301 /* On 64-bit, the APIC must be integrated, Check local APIC only */
1302 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1303 disable_apic = 1;
1304 pr_info("APIC disabled by BIOS\n");
1305 return APIC_PIC;
1306 }
1307 #else
1308 /* On 32-bit, the APIC may be integrated APIC or 82489DX */
1309
1310 /* Neither 82489DX nor integrated APIC ? */
1311 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) {
1312 disable_apic = 1;
1313 return APIC_PIC;
1314 }
1315
1316 /* If the BIOS pretends there is an integrated APIC ? */
1317 if (!boot_cpu_has(X86_FEATURE_APIC) &&
1318 APIC_INTEGRATED(boot_cpu_apic_version)) {
1319 disable_apic = 1;
1320 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n",
1321 boot_cpu_physical_apicid);
1322 return APIC_PIC;
1323 }
1324 #endif
1325
1326 /* Check MP table or ACPI MADT configuration */
1327 if (!smp_found_config) {
1328 disable_ioapic_support();
1329 if (!acpi_lapic) {
1330 pr_info("APIC: ACPI MADT or MP tables are not detected\n");
1331 return APIC_VIRTUAL_WIRE_NO_CONFIG;
1332 }
1333 return APIC_VIRTUAL_WIRE;
1334 }
1335
1336 #ifdef CONFIG_SMP
1337 /* If SMP should be disabled, then really disable it! */
1338 if (!setup_max_cpus) {
1339 pr_info("APIC: SMP mode deactivated\n");
1340 return APIC_SYMMETRIC_IO_NO_ROUTING;
1341 }
1342
1343 if (read_apic_id() != boot_cpu_physical_apicid) {
1344 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1345 read_apic_id(), boot_cpu_physical_apicid);
1346 /* Or can we switch back to PIC here? */
1347 }
1348 #endif
1349
1350 return APIC_SYMMETRIC_IO;
1351 }
1352
1353 /* Select the interrupt delivery mode for the BSP */
apic_intr_mode_select(void)1354 void __init apic_intr_mode_select(void)
1355 {
1356 apic_intr_mode = __apic_intr_mode_select();
1357 }
1358
1359 /*
1360 * An initial setup of the virtual wire mode.
1361 */
init_bsp_APIC(void)1362 void __init init_bsp_APIC(void)
1363 {
1364 unsigned int value;
1365
1366 /*
1367 * Don't do the setup now if we have a SMP BIOS as the
1368 * through-I/O-APIC virtual wire mode might be active.
1369 */
1370 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1371 return;
1372
1373 /*
1374 * Do not trust the local APIC being empty at bootup.
1375 */
1376 clear_local_APIC();
1377
1378 /*
1379 * Enable APIC.
1380 */
1381 value = apic_read(APIC_SPIV);
1382 value &= ~APIC_VECTOR_MASK;
1383 value |= APIC_SPIV_APIC_ENABLED;
1384
1385 #ifdef CONFIG_X86_32
1386 /* This bit is reserved on P4/Xeon and should be cleared */
1387 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1388 (boot_cpu_data.x86 == 15))
1389 value &= ~APIC_SPIV_FOCUS_DISABLED;
1390 else
1391 #endif
1392 value |= APIC_SPIV_FOCUS_DISABLED;
1393 value |= SPURIOUS_APIC_VECTOR;
1394 apic_write(APIC_SPIV, value);
1395
1396 /*
1397 * Set up the virtual wire mode.
1398 */
1399 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1400 value = APIC_DM_NMI;
1401 if (!lapic_is_integrated()) /* 82489DX */
1402 value |= APIC_LVT_LEVEL_TRIGGER;
1403 if (apic_extnmi == APIC_EXTNMI_NONE)
1404 value |= APIC_LVT_MASKED;
1405 apic_write(APIC_LVT1, value);
1406 }
1407
1408 static void __init apic_bsp_setup(bool upmode);
1409
1410 /* Init the interrupt delivery mode for the BSP */
apic_intr_mode_init(void)1411 void __init apic_intr_mode_init(void)
1412 {
1413 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT);
1414
1415 switch (apic_intr_mode) {
1416 case APIC_PIC:
1417 pr_info("APIC: Keep in PIC mode(8259)\n");
1418 return;
1419 case APIC_VIRTUAL_WIRE:
1420 pr_info("APIC: Switch to virtual wire mode setup\n");
1421 default_setup_apic_routing();
1422 break;
1423 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1424 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n");
1425 upmode = true;
1426 default_setup_apic_routing();
1427 break;
1428 case APIC_SYMMETRIC_IO:
1429 pr_info("APIC: Switch to symmetric I/O mode setup\n");
1430 default_setup_apic_routing();
1431 break;
1432 case APIC_SYMMETRIC_IO_NO_ROUTING:
1433 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n");
1434 break;
1435 }
1436
1437 if (x86_platform.apic_post_init)
1438 x86_platform.apic_post_init();
1439
1440 apic_bsp_setup(upmode);
1441 }
1442
lapic_setup_esr(void)1443 static void lapic_setup_esr(void)
1444 {
1445 unsigned int oldvalue, value, maxlvt;
1446
1447 if (!lapic_is_integrated()) {
1448 pr_info("No ESR for 82489DX.\n");
1449 return;
1450 }
1451
1452 if (apic->disable_esr) {
1453 /*
1454 * Something untraceable is creating bad interrupts on
1455 * secondary quads ... for the moment, just leave the
1456 * ESR disabled - we can't do anything useful with the
1457 * errors anyway - mbligh
1458 */
1459 pr_info("Leaving ESR disabled.\n");
1460 return;
1461 }
1462
1463 maxlvt = lapic_get_maxlvt();
1464 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1465 apic_write(APIC_ESR, 0);
1466 oldvalue = apic_read(APIC_ESR);
1467
1468 /* enables sending errors */
1469 value = ERROR_APIC_VECTOR;
1470 apic_write(APIC_LVTERR, value);
1471
1472 /*
1473 * spec says clear errors after enabling vector.
1474 */
1475 if (maxlvt > 3)
1476 apic_write(APIC_ESR, 0);
1477 value = apic_read(APIC_ESR);
1478 if (value != oldvalue)
1479 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1480 "vector: 0x%08x after: 0x%08x\n",
1481 oldvalue, value);
1482 }
1483
1484 #define APIC_IR_REGS APIC_ISR_NR
1485 #define APIC_IR_BITS (APIC_IR_REGS * 32)
1486 #define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG)
1487
1488 union apic_ir {
1489 unsigned long map[APIC_IR_MAPSIZE];
1490 u32 regs[APIC_IR_REGS];
1491 };
1492
apic_check_and_ack(union apic_ir * irr,union apic_ir * isr)1493 static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr)
1494 {
1495 int i, bit;
1496
1497 /* Read the IRRs */
1498 for (i = 0; i < APIC_IR_REGS; i++)
1499 irr->regs[i] = apic_read(APIC_IRR + i * 0x10);
1500
1501 /* Read the ISRs */
1502 for (i = 0; i < APIC_IR_REGS; i++)
1503 isr->regs[i] = apic_read(APIC_ISR + i * 0x10);
1504
1505 /*
1506 * If the ISR map is not empty. ACK the APIC and run another round
1507 * to verify whether a pending IRR has been unblocked and turned
1508 * into a ISR.
1509 */
1510 if (!bitmap_empty(isr->map, APIC_IR_BITS)) {
1511 /*
1512 * There can be multiple ISR bits set when a high priority
1513 * interrupt preempted a lower priority one. Issue an ACK
1514 * per set bit.
1515 */
1516 for_each_set_bit(bit, isr->map, APIC_IR_BITS)
1517 ack_APIC_irq();
1518 return true;
1519 }
1520
1521 return !bitmap_empty(irr->map, APIC_IR_BITS);
1522 }
1523
1524 /*
1525 * After a crash, we no longer service the interrupts and a pending
1526 * interrupt from previous kernel might still have ISR bit set.
1527 *
1528 * Most probably by now the CPU has serviced that pending interrupt and it
1529 * might not have done the ack_APIC_irq() because it thought, interrupt
1530 * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear
1531 * the ISR bit and cpu thinks it has already serviced the interrupt. Hence
1532 * a vector might get locked. It was noticed for timer irq (vector
1533 * 0x31). Issue an extra EOI to clear ISR.
1534 *
1535 * If there are pending IRR bits they turn into ISR bits after a higher
1536 * priority ISR bit has been acked.
1537 */
apic_pending_intr_clear(void)1538 static void apic_pending_intr_clear(void)
1539 {
1540 union apic_ir irr, isr;
1541 unsigned int i;
1542
1543 /* 512 loops are way oversized and give the APIC a chance to obey. */
1544 for (i = 0; i < 512; i++) {
1545 if (!apic_check_and_ack(&irr, &isr))
1546 return;
1547 }
1548 /* Dump the IRR/ISR content if that failed */
1549 pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map);
1550 }
1551
1552 /**
1553 * setup_local_APIC - setup the local APIC
1554 *
1555 * Used to setup local APIC while initializing BSP or bringing up APs.
1556 * Always called with preemption disabled.
1557 */
setup_local_APIC(void)1558 static void setup_local_APIC(void)
1559 {
1560 int cpu = smp_processor_id();
1561 unsigned int value;
1562
1563 if (disable_apic) {
1564 disable_ioapic_support();
1565 return;
1566 }
1567
1568 /*
1569 * If this comes from kexec/kcrash the APIC might be enabled in
1570 * SPIV. Soft disable it before doing further initialization.
1571 */
1572 value = apic_read(APIC_SPIV);
1573 value &= ~APIC_SPIV_APIC_ENABLED;
1574 apic_write(APIC_SPIV, value);
1575
1576 #ifdef CONFIG_X86_32
1577 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1578 if (lapic_is_integrated() && apic->disable_esr) {
1579 apic_write(APIC_ESR, 0);
1580 apic_write(APIC_ESR, 0);
1581 apic_write(APIC_ESR, 0);
1582 apic_write(APIC_ESR, 0);
1583 }
1584 #endif
1585 /*
1586 * Double-check whether this APIC is really registered.
1587 * This is meaningless in clustered apic mode, so we skip it.
1588 */
1589 BUG_ON(!apic->apic_id_registered());
1590
1591 /*
1592 * Intel recommends to set DFR, LDR and TPR before enabling
1593 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1594 * document number 292116). So here it goes...
1595 */
1596 apic->init_apic_ldr();
1597
1598 #ifdef CONFIG_X86_32
1599 if (apic->dest_mode_logical) {
1600 int logical_apicid, ldr_apicid;
1601
1602 /*
1603 * APIC LDR is initialized. If logical_apicid mapping was
1604 * initialized during get_smp_config(), make sure it matches
1605 * the actual value.
1606 */
1607 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1608 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1609 if (logical_apicid != BAD_APICID)
1610 WARN_ON(logical_apicid != ldr_apicid);
1611 /* Always use the value from LDR. */
1612 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
1613 }
1614 #endif
1615
1616 /*
1617 * Set Task Priority to 'accept all except vectors 0-31'. An APIC
1618 * vector in the 16-31 range could be delivered if TPR == 0, but we
1619 * would think it's an exception and terrible things will happen. We
1620 * never change this later on.
1621 */
1622 value = apic_read(APIC_TASKPRI);
1623 value &= ~APIC_TPRI_MASK;
1624 value |= 0x10;
1625 apic_write(APIC_TASKPRI, value);
1626
1627 /* Clear eventually stale ISR/IRR bits */
1628 apic_pending_intr_clear();
1629
1630 /*
1631 * Now that we are all set up, enable the APIC
1632 */
1633 value = apic_read(APIC_SPIV);
1634 value &= ~APIC_VECTOR_MASK;
1635 /*
1636 * Enable APIC
1637 */
1638 value |= APIC_SPIV_APIC_ENABLED;
1639
1640 #ifdef CONFIG_X86_32
1641 /*
1642 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1643 * certain networking cards. If high frequency interrupts are
1644 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1645 * entry is masked/unmasked at a high rate as well then sooner or
1646 * later IOAPIC line gets 'stuck', no more interrupts are received
1647 * from the device. If focus CPU is disabled then the hang goes
1648 * away, oh well :-(
1649 *
1650 * [ This bug can be reproduced easily with a level-triggered
1651 * PCI Ne2000 networking cards and PII/PIII processors, dual
1652 * BX chipset. ]
1653 */
1654 /*
1655 * Actually disabling the focus CPU check just makes the hang less
1656 * frequent as it makes the interrupt distribution model be more
1657 * like LRU than MRU (the short-term load is more even across CPUs).
1658 */
1659
1660 /*
1661 * - enable focus processor (bit==0)
1662 * - 64bit mode always use processor focus
1663 * so no need to set it
1664 */
1665 value &= ~APIC_SPIV_FOCUS_DISABLED;
1666 #endif
1667
1668 /*
1669 * Set spurious IRQ vector
1670 */
1671 value |= SPURIOUS_APIC_VECTOR;
1672 apic_write(APIC_SPIV, value);
1673
1674 perf_events_lapic_init();
1675
1676 /*
1677 * Set up LVT0, LVT1:
1678 *
1679 * set up through-local-APIC on the boot CPU's LINT0. This is not
1680 * strictly necessary in pure symmetric-IO mode, but sometimes
1681 * we delegate interrupts to the 8259A.
1682 */
1683 /*
1684 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1685 */
1686 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1687 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
1688 value = APIC_DM_EXTINT;
1689 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1690 } else {
1691 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1692 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1693 }
1694 apic_write(APIC_LVT0, value);
1695
1696 /*
1697 * Only the BSP sees the LINT1 NMI signal by default. This can be
1698 * modified by apic_extnmi= boot option.
1699 */
1700 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1701 apic_extnmi == APIC_EXTNMI_ALL)
1702 value = APIC_DM_NMI;
1703 else
1704 value = APIC_DM_NMI | APIC_LVT_MASKED;
1705
1706 /* Is 82489DX ? */
1707 if (!lapic_is_integrated())
1708 value |= APIC_LVT_LEVEL_TRIGGER;
1709 apic_write(APIC_LVT1, value);
1710
1711 #ifdef CONFIG_X86_MCE_INTEL
1712 /* Recheck CMCI information after local APIC is up on CPU #0 */
1713 if (!cpu)
1714 cmci_recheck();
1715 #endif
1716 }
1717
end_local_APIC_setup(void)1718 static void end_local_APIC_setup(void)
1719 {
1720 lapic_setup_esr();
1721
1722 #ifdef CONFIG_X86_32
1723 {
1724 unsigned int value;
1725 /* Disable the local apic timer */
1726 value = apic_read(APIC_LVTT);
1727 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1728 apic_write(APIC_LVTT, value);
1729 }
1730 #endif
1731
1732 apic_pm_activate();
1733 }
1734
1735 /*
1736 * APIC setup function for application processors. Called from smpboot.c
1737 */
apic_ap_setup(void)1738 void apic_ap_setup(void)
1739 {
1740 setup_local_APIC();
1741 end_local_APIC_setup();
1742 }
1743
1744 #ifdef CONFIG_X86_X2APIC
1745 int x2apic_mode;
1746 EXPORT_SYMBOL_GPL(x2apic_mode);
1747
1748 enum {
1749 X2APIC_OFF,
1750 X2APIC_ON,
1751 X2APIC_DISABLED,
1752 };
1753 static int x2apic_state;
1754
__x2apic_disable(void)1755 static void __x2apic_disable(void)
1756 {
1757 u64 msr;
1758
1759 if (!boot_cpu_has(X86_FEATURE_APIC))
1760 return;
1761
1762 rdmsrl(MSR_IA32_APICBASE, msr);
1763 if (!(msr & X2APIC_ENABLE))
1764 return;
1765 /* Disable xapic and x2apic first and then reenable xapic mode */
1766 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1767 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1768 printk_once(KERN_INFO "x2apic disabled\n");
1769 }
1770
__x2apic_enable(void)1771 static void __x2apic_enable(void)
1772 {
1773 u64 msr;
1774
1775 rdmsrl(MSR_IA32_APICBASE, msr);
1776 if (msr & X2APIC_ENABLE)
1777 return;
1778 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1779 printk_once(KERN_INFO "x2apic enabled\n");
1780 }
1781
setup_nox2apic(char * str)1782 static int __init setup_nox2apic(char *str)
1783 {
1784 if (x2apic_enabled()) {
1785 int apicid = native_apic_msr_read(APIC_ID);
1786
1787 if (apicid >= 255) {
1788 pr_warn("Apicid: %08x, cannot enforce nox2apic\n",
1789 apicid);
1790 return 0;
1791 }
1792 pr_warn("x2apic already enabled.\n");
1793 __x2apic_disable();
1794 }
1795 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1796 x2apic_state = X2APIC_DISABLED;
1797 x2apic_mode = 0;
1798 return 0;
1799 }
1800 early_param("nox2apic", setup_nox2apic);
1801
1802 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
x2apic_setup(void)1803 void x2apic_setup(void)
1804 {
1805 /*
1806 * If x2apic is not in ON state, disable it if already enabled
1807 * from BIOS.
1808 */
1809 if (x2apic_state != X2APIC_ON) {
1810 __x2apic_disable();
1811 return;
1812 }
1813 __x2apic_enable();
1814 }
1815
x2apic_disable(void)1816 static __init void x2apic_disable(void)
1817 {
1818 u32 x2apic_id, state = x2apic_state;
1819
1820 x2apic_mode = 0;
1821 x2apic_state = X2APIC_DISABLED;
1822
1823 if (state != X2APIC_ON)
1824 return;
1825
1826 x2apic_id = read_apic_id();
1827 if (x2apic_id >= 255)
1828 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1829
1830 __x2apic_disable();
1831 register_lapic_address(mp_lapic_addr);
1832 }
1833
x2apic_enable(void)1834 static __init void x2apic_enable(void)
1835 {
1836 if (x2apic_state != X2APIC_OFF)
1837 return;
1838
1839 x2apic_mode = 1;
1840 x2apic_state = X2APIC_ON;
1841 __x2apic_enable();
1842 }
1843
try_to_enable_x2apic(int remap_mode)1844 static __init void try_to_enable_x2apic(int remap_mode)
1845 {
1846 if (x2apic_state == X2APIC_DISABLED)
1847 return;
1848
1849 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1850 u32 apic_limit = 255;
1851
1852 /*
1853 * Using X2APIC without IR is not architecturally supported
1854 * on bare metal but may be supported in guests.
1855 */
1856 if (!x86_init.hyper.x2apic_available()) {
1857 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1858 x2apic_disable();
1859 return;
1860 }
1861
1862 /*
1863 * If the hypervisor supports extended destination ID in
1864 * MSI, that increases the maximum APIC ID that can be
1865 * used for non-remapped IRQ domains.
1866 */
1867 if (x86_init.hyper.msi_ext_dest_id()) {
1868 virt_ext_dest_id = 1;
1869 apic_limit = 32767;
1870 }
1871
1872 /*
1873 * Without IR, all CPUs can be addressed by IOAPIC/MSI only
1874 * in physical mode, and CPUs with an APIC ID that cannot
1875 * be addressed must not be brought online.
1876 */
1877 x2apic_set_max_apicid(apic_limit);
1878 x2apic_phys = 1;
1879 }
1880 x2apic_enable();
1881 }
1882
check_x2apic(void)1883 void __init check_x2apic(void)
1884 {
1885 if (x2apic_enabled()) {
1886 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1887 x2apic_mode = 1;
1888 x2apic_state = X2APIC_ON;
1889 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1890 x2apic_state = X2APIC_DISABLED;
1891 }
1892 }
1893 #else /* CONFIG_X86_X2APIC */
validate_x2apic(void)1894 static int __init validate_x2apic(void)
1895 {
1896 if (!apic_is_x2apic_enabled())
1897 return 0;
1898 /*
1899 * Checkme: Can we simply turn off x2apic here instead of panic?
1900 */
1901 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1902 }
1903 early_initcall(validate_x2apic);
1904
try_to_enable_x2apic(int remap_mode)1905 static inline void try_to_enable_x2apic(int remap_mode) { }
__x2apic_enable(void)1906 static inline void __x2apic_enable(void) { }
1907 #endif /* !CONFIG_X86_X2APIC */
1908
enable_IR_x2apic(void)1909 void __init enable_IR_x2apic(void)
1910 {
1911 unsigned long flags;
1912 int ret, ir_stat;
1913
1914 if (skip_ioapic_setup) {
1915 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1916 return;
1917 }
1918
1919 ir_stat = irq_remapping_prepare();
1920 if (ir_stat < 0 && !x2apic_supported())
1921 return;
1922
1923 ret = save_ioapic_entries();
1924 if (ret) {
1925 pr_info("Saving IO-APIC state failed: %d\n", ret);
1926 return;
1927 }
1928
1929 local_irq_save(flags);
1930 legacy_pic->mask_all();
1931 mask_ioapic_entries();
1932
1933 /* If irq_remapping_prepare() succeeded, try to enable it */
1934 if (ir_stat >= 0)
1935 ir_stat = irq_remapping_enable();
1936 /* ir_stat contains the remap mode or an error code */
1937 try_to_enable_x2apic(ir_stat);
1938
1939 if (ir_stat < 0)
1940 restore_ioapic_entries();
1941 legacy_pic->restore_mask();
1942 local_irq_restore(flags);
1943 }
1944
1945 #ifdef CONFIG_X86_64
1946 /*
1947 * Detect and enable local APICs on non-SMP boards.
1948 * Original code written by Keir Fraser.
1949 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1950 * not correctly set up (usually the APIC timer won't work etc.)
1951 */
detect_init_APIC(void)1952 static int __init detect_init_APIC(void)
1953 {
1954 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1955 pr_info("No local APIC present\n");
1956 return -1;
1957 }
1958
1959 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1960 return 0;
1961 }
1962 #else
1963
apic_verify(void)1964 static int __init apic_verify(void)
1965 {
1966 u32 features, h, l;
1967
1968 /*
1969 * The APIC feature bit should now be enabled
1970 * in `cpuid'
1971 */
1972 features = cpuid_edx(1);
1973 if (!(features & (1 << X86_FEATURE_APIC))) {
1974 pr_warn("Could not enable APIC!\n");
1975 return -1;
1976 }
1977 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1978 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1979
1980 /* The BIOS may have set up the APIC at some other address */
1981 if (boot_cpu_data.x86 >= 6) {
1982 rdmsr(MSR_IA32_APICBASE, l, h);
1983 if (l & MSR_IA32_APICBASE_ENABLE)
1984 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1985 }
1986
1987 pr_info("Found and enabled local APIC!\n");
1988 return 0;
1989 }
1990
apic_force_enable(unsigned long addr)1991 int __init apic_force_enable(unsigned long addr)
1992 {
1993 u32 h, l;
1994
1995 if (disable_apic)
1996 return -1;
1997
1998 /*
1999 * Some BIOSes disable the local APIC in the APIC_BASE
2000 * MSR. This can only be done in software for Intel P6 or later
2001 * and AMD K7 (Model > 1) or later.
2002 */
2003 if (boot_cpu_data.x86 >= 6) {
2004 rdmsr(MSR_IA32_APICBASE, l, h);
2005 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
2006 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
2007 l &= ~MSR_IA32_APICBASE_BASE;
2008 l |= MSR_IA32_APICBASE_ENABLE | addr;
2009 wrmsr(MSR_IA32_APICBASE, l, h);
2010 enabled_via_apicbase = 1;
2011 }
2012 }
2013 return apic_verify();
2014 }
2015
2016 /*
2017 * Detect and initialize APIC
2018 */
detect_init_APIC(void)2019 static int __init detect_init_APIC(void)
2020 {
2021 /* Disabled by kernel option? */
2022 if (disable_apic)
2023 return -1;
2024
2025 switch (boot_cpu_data.x86_vendor) {
2026 case X86_VENDOR_AMD:
2027 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
2028 (boot_cpu_data.x86 >= 15))
2029 break;
2030 goto no_apic;
2031 case X86_VENDOR_HYGON:
2032 break;
2033 case X86_VENDOR_INTEL:
2034 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
2035 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
2036 break;
2037 goto no_apic;
2038 default:
2039 goto no_apic;
2040 }
2041
2042 if (!boot_cpu_has(X86_FEATURE_APIC)) {
2043 /*
2044 * Over-ride BIOS and try to enable the local APIC only if
2045 * "lapic" specified.
2046 */
2047 if (!force_enable_local_apic) {
2048 pr_info("Local APIC disabled by BIOS -- "
2049 "you can enable it with \"lapic\"\n");
2050 return -1;
2051 }
2052 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
2053 return -1;
2054 } else {
2055 if (apic_verify())
2056 return -1;
2057 }
2058
2059 apic_pm_activate();
2060
2061 return 0;
2062
2063 no_apic:
2064 pr_info("No local APIC present or hardware disabled\n");
2065 return -1;
2066 }
2067 #endif
2068
2069 /**
2070 * init_apic_mappings - initialize APIC mappings
2071 */
init_apic_mappings(void)2072 void __init init_apic_mappings(void)
2073 {
2074 unsigned int new_apicid;
2075
2076 if (apic_validate_deadline_timer())
2077 pr_info("TSC deadline timer available\n");
2078
2079 if (x2apic_mode) {
2080 boot_cpu_physical_apicid = read_apic_id();
2081 return;
2082 }
2083
2084 /* If no local APIC can be found return early */
2085 if (!smp_found_config && detect_init_APIC()) {
2086 /* lets NOP'ify apic operations */
2087 pr_info("APIC: disable apic facility\n");
2088 apic_disable();
2089 } else {
2090 apic_phys = mp_lapic_addr;
2091
2092 /*
2093 * If the system has ACPI MADT tables or MP info, the LAPIC
2094 * address is already registered.
2095 */
2096 if (!acpi_lapic && !smp_found_config)
2097 register_lapic_address(apic_phys);
2098 }
2099
2100 /*
2101 * Fetch the APIC ID of the BSP in case we have a
2102 * default configuration (or the MP table is broken).
2103 */
2104 new_apicid = read_apic_id();
2105 if (boot_cpu_physical_apicid != new_apicid) {
2106 boot_cpu_physical_apicid = new_apicid;
2107 /*
2108 * yeah -- we lie about apic_version
2109 * in case if apic was disabled via boot option
2110 * but it's not a problem for SMP compiled kernel
2111 * since apic_intr_mode_select is prepared for such
2112 * a case and disable smp mode
2113 */
2114 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2115 }
2116 }
2117
register_lapic_address(unsigned long address)2118 void __init register_lapic_address(unsigned long address)
2119 {
2120 mp_lapic_addr = address;
2121
2122 if (!x2apic_mode) {
2123 set_fixmap_nocache(FIX_APIC_BASE, address);
2124 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
2125 APIC_BASE, address);
2126 }
2127 if (boot_cpu_physical_apicid == -1U) {
2128 boot_cpu_physical_apicid = read_apic_id();
2129 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2130 }
2131 }
2132
2133 /*
2134 * Local APIC interrupts
2135 */
2136
2137 /*
2138 * Common handling code for spurious_interrupt and spurious_vector entry
2139 * points below. No point in allowing the compiler to inline it twice.
2140 */
handle_spurious_interrupt(u8 vector)2141 static noinline void handle_spurious_interrupt(u8 vector)
2142 {
2143 u32 v;
2144
2145 trace_spurious_apic_entry(vector);
2146
2147 inc_irq_stat(irq_spurious_count);
2148
2149 /*
2150 * If this is a spurious interrupt then do not acknowledge
2151 */
2152 if (vector == SPURIOUS_APIC_VECTOR) {
2153 /* See SDM vol 3 */
2154 pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n",
2155 smp_processor_id());
2156 goto out;
2157 }
2158
2159 /*
2160 * If it is a vectored one, verify it's set in the ISR. If set,
2161 * acknowledge it.
2162 */
2163 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
2164 if (v & (1 << (vector & 0x1f))) {
2165 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n",
2166 vector, smp_processor_id());
2167 ack_APIC_irq();
2168 } else {
2169 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n",
2170 vector, smp_processor_id());
2171 }
2172 out:
2173 trace_spurious_apic_exit(vector);
2174 }
2175
2176 /**
2177 * spurious_interrupt - Catch all for interrupts raised on unused vectors
2178 * @regs: Pointer to pt_regs on stack
2179 * @vector: The vector number
2180 *
2181 * This is invoked from ASM entry code to catch all interrupts which
2182 * trigger on an entry which is routed to the common_spurious idtentry
2183 * point.
2184 */
DEFINE_IDTENTRY_IRQ(spurious_interrupt)2185 DEFINE_IDTENTRY_IRQ(spurious_interrupt)
2186 {
2187 handle_spurious_interrupt(vector);
2188 }
2189
DEFINE_IDTENTRY_SYSVEC(sysvec_spurious_apic_interrupt)2190 DEFINE_IDTENTRY_SYSVEC(sysvec_spurious_apic_interrupt)
2191 {
2192 handle_spurious_interrupt(SPURIOUS_APIC_VECTOR);
2193 }
2194
2195 /*
2196 * This interrupt should never happen with our APIC/SMP architecture
2197 */
DEFINE_IDTENTRY_SYSVEC(sysvec_error_interrupt)2198 DEFINE_IDTENTRY_SYSVEC(sysvec_error_interrupt)
2199 {
2200 static const char * const error_interrupt_reason[] = {
2201 "Send CS error", /* APIC Error Bit 0 */
2202 "Receive CS error", /* APIC Error Bit 1 */
2203 "Send accept error", /* APIC Error Bit 2 */
2204 "Receive accept error", /* APIC Error Bit 3 */
2205 "Redirectable IPI", /* APIC Error Bit 4 */
2206 "Send illegal vector", /* APIC Error Bit 5 */
2207 "Received illegal vector", /* APIC Error Bit 6 */
2208 "Illegal register address", /* APIC Error Bit 7 */
2209 };
2210 u32 v, i = 0;
2211
2212 trace_error_apic_entry(ERROR_APIC_VECTOR);
2213
2214 /* First tickle the hardware, only then report what went on. -- REW */
2215 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
2216 apic_write(APIC_ESR, 0);
2217 v = apic_read(APIC_ESR);
2218 ack_APIC_irq();
2219 atomic_inc(&irq_err_count);
2220
2221 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
2222 smp_processor_id(), v);
2223
2224 v &= 0xff;
2225 while (v) {
2226 if (v & 0x1)
2227 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
2228 i++;
2229 v >>= 1;
2230 }
2231
2232 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2233
2234 trace_error_apic_exit(ERROR_APIC_VECTOR);
2235 }
2236
2237 /**
2238 * connect_bsp_APIC - attach the APIC to the interrupt system
2239 */
connect_bsp_APIC(void)2240 static void __init connect_bsp_APIC(void)
2241 {
2242 #ifdef CONFIG_X86_32
2243 if (pic_mode) {
2244 /*
2245 * Do not trust the local APIC being empty at bootup.
2246 */
2247 clear_local_APIC();
2248 /*
2249 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2250 * local APIC to INT and NMI lines.
2251 */
2252 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2253 "enabling APIC mode.\n");
2254 imcr_pic_to_apic();
2255 }
2256 #endif
2257 }
2258
2259 /**
2260 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2261 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2262 *
2263 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2264 * APIC is disabled.
2265 */
disconnect_bsp_APIC(int virt_wire_setup)2266 void disconnect_bsp_APIC(int virt_wire_setup)
2267 {
2268 unsigned int value;
2269
2270 #ifdef CONFIG_X86_32
2271 if (pic_mode) {
2272 /*
2273 * Put the board back into PIC mode (has an effect only on
2274 * certain older boards). Note that APIC interrupts, including
2275 * IPIs, won't work beyond this point! The only exception are
2276 * INIT IPIs.
2277 */
2278 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2279 "entering PIC mode.\n");
2280 imcr_apic_to_pic();
2281 return;
2282 }
2283 #endif
2284
2285 /* Go back to Virtual Wire compatibility mode */
2286
2287 /* For the spurious interrupt use vector F, and enable it */
2288 value = apic_read(APIC_SPIV);
2289 value &= ~APIC_VECTOR_MASK;
2290 value |= APIC_SPIV_APIC_ENABLED;
2291 value |= 0xf;
2292 apic_write(APIC_SPIV, value);
2293
2294 if (!virt_wire_setup) {
2295 /*
2296 * For LVT0 make it edge triggered, active high,
2297 * external and enabled
2298 */
2299 value = apic_read(APIC_LVT0);
2300 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2301 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2302 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2303 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2304 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2305 apic_write(APIC_LVT0, value);
2306 } else {
2307 /* Disable LVT0 */
2308 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2309 }
2310
2311 /*
2312 * For LVT1 make it edge triggered, active high,
2313 * nmi and enabled
2314 */
2315 value = apic_read(APIC_LVT1);
2316 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2317 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2318 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2319 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2320 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2321 apic_write(APIC_LVT1, value);
2322 }
2323
2324 /*
2325 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2326 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2327 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2328 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2329 *
2330 * NOTE: Reserve 0 for BSP.
2331 */
2332 static int nr_logical_cpuids = 1;
2333
2334 /*
2335 * Used to store mapping between logical CPU IDs and APIC IDs.
2336 */
2337 static int cpuid_to_apicid[] = {
2338 [0 ... NR_CPUS - 1] = -1,
2339 };
2340
arch_match_cpu_phys_id(int cpu,u64 phys_id)2341 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
2342 {
2343 return phys_id == cpuid_to_apicid[cpu];
2344 }
2345
2346 #ifdef CONFIG_SMP
2347 /**
2348 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread
2349 * @apicid: APIC ID to check
2350 */
apic_id_is_primary_thread(unsigned int apicid)2351 bool apic_id_is_primary_thread(unsigned int apicid)
2352 {
2353 u32 mask;
2354
2355 if (smp_num_siblings == 1)
2356 return true;
2357 /* Isolate the SMT bit(s) in the APICID and check for 0 */
2358 mask = (1U << (fls(smp_num_siblings) - 1)) - 1;
2359 return !(apicid & mask);
2360 }
2361 #endif
2362
2363 /*
2364 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2365 * and cpuid_to_apicid[] synchronized.
2366 */
allocate_logical_cpuid(int apicid)2367 static int allocate_logical_cpuid(int apicid)
2368 {
2369 int i;
2370
2371 /*
2372 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2373 * check if the kernel has allocated a cpuid for it.
2374 */
2375 for (i = 0; i < nr_logical_cpuids; i++) {
2376 if (cpuid_to_apicid[i] == apicid)
2377 return i;
2378 }
2379
2380 /* Allocate a new cpuid. */
2381 if (nr_logical_cpuids >= nr_cpu_ids) {
2382 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. "
2383 "Processor %d/0x%x and the rest are ignored.\n",
2384 nr_cpu_ids, nr_logical_cpuids, apicid);
2385 return -EINVAL;
2386 }
2387
2388 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2389 return nr_logical_cpuids++;
2390 }
2391
generic_processor_info(int apicid,int version)2392 int generic_processor_info(int apicid, int version)
2393 {
2394 int cpu, max = nr_cpu_ids;
2395 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2396 phys_cpu_present_map);
2397
2398 /*
2399 * boot_cpu_physical_apicid is designed to have the apicid
2400 * returned by read_apic_id(), i.e, the apicid of the
2401 * currently booting-up processor. However, on some platforms,
2402 * it is temporarily modified by the apicid reported as BSP
2403 * through MP table. Concretely:
2404 *
2405 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2406 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2407 *
2408 * This function is executed with the modified
2409 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2410 * parameter doesn't work to disable APs on kdump 2nd kernel.
2411 *
2412 * Since fixing handling of boot_cpu_physical_apicid requires
2413 * another discussion and tests on each platform, we leave it
2414 * for now and here we use read_apic_id() directly in this
2415 * function, generic_processor_info().
2416 */
2417 if (disabled_cpu_apicid != BAD_APICID &&
2418 disabled_cpu_apicid != read_apic_id() &&
2419 disabled_cpu_apicid == apicid) {
2420 int thiscpu = num_processors + disabled_cpus;
2421
2422 pr_warn("APIC: Disabling requested cpu."
2423 " Processor %d/0x%x ignored.\n", thiscpu, apicid);
2424
2425 disabled_cpus++;
2426 return -ENODEV;
2427 }
2428
2429 /*
2430 * If boot cpu has not been detected yet, then only allow upto
2431 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2432 */
2433 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2434 apicid != boot_cpu_physical_apicid) {
2435 int thiscpu = max + disabled_cpus - 1;
2436
2437 pr_warn("APIC: NR_CPUS/possible_cpus limit of %i almost"
2438 " reached. Keeping one slot for boot cpu."
2439 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2440
2441 disabled_cpus++;
2442 return -ENODEV;
2443 }
2444
2445 if (num_processors >= nr_cpu_ids) {
2446 int thiscpu = max + disabled_cpus;
2447
2448 pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. "
2449 "Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2450
2451 disabled_cpus++;
2452 return -EINVAL;
2453 }
2454
2455 if (apicid == boot_cpu_physical_apicid) {
2456 /*
2457 * x86_bios_cpu_apicid is required to have processors listed
2458 * in same order as logical cpu numbers. Hence the first
2459 * entry is BSP, and so on.
2460 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2461 * for BSP.
2462 */
2463 cpu = 0;
2464
2465 /* Logical cpuid 0 is reserved for BSP. */
2466 cpuid_to_apicid[0] = apicid;
2467 } else {
2468 cpu = allocate_logical_cpuid(apicid);
2469 if (cpu < 0) {
2470 disabled_cpus++;
2471 return -EINVAL;
2472 }
2473 }
2474
2475 /*
2476 * Validate version
2477 */
2478 if (version == 0x0) {
2479 pr_warn("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2480 cpu, apicid);
2481 version = 0x10;
2482 }
2483
2484 if (version != boot_cpu_apic_version) {
2485 pr_warn("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2486 boot_cpu_apic_version, cpu, version);
2487 }
2488
2489 if (apicid > max_physical_apicid)
2490 max_physical_apicid = apicid;
2491
2492 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2493 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2494 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2495 #endif
2496 #ifdef CONFIG_X86_32
2497 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2498 apic->x86_32_early_logical_apicid(cpu);
2499 #endif
2500 set_cpu_possible(cpu, true);
2501 physid_set(apicid, phys_cpu_present_map);
2502 set_cpu_present(cpu, true);
2503 num_processors++;
2504
2505 return cpu;
2506 }
2507
hard_smp_processor_id(void)2508 int hard_smp_processor_id(void)
2509 {
2510 return read_apic_id();
2511 }
2512
__irq_msi_compose_msg(struct irq_cfg * cfg,struct msi_msg * msg,bool dmar)2513 void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
2514 bool dmar)
2515 {
2516 memset(msg, 0, sizeof(*msg));
2517
2518 msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW;
2519 msg->arch_addr_lo.dest_mode_logical = apic->dest_mode_logical;
2520 msg->arch_addr_lo.destid_0_7 = cfg->dest_apicid & 0xFF;
2521
2522 msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_FIXED;
2523 msg->arch_data.vector = cfg->vector;
2524
2525 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
2526 /*
2527 * Only the IOMMU itself can use the trick of putting destination
2528 * APIC ID into the high bits of the address. Anything else would
2529 * just be writing to memory if it tried that, and needs IR to
2530 * address APICs which can't be addressed in the normal 32-bit
2531 * address range at 0xFFExxxxx. That is typically just 8 bits, but
2532 * some hypervisors allow the extended destination ID field in bits
2533 * 5-11 to be used, giving support for 15 bits of APIC IDs in total.
2534 */
2535 if (dmar)
2536 msg->arch_addr_hi.destid_8_31 = cfg->dest_apicid >> 8;
2537 else if (virt_ext_dest_id && cfg->dest_apicid < 0x8000)
2538 msg->arch_addr_lo.virt_destid_8_14 = cfg->dest_apicid >> 8;
2539 else
2540 WARN_ON_ONCE(cfg->dest_apicid > 0xFF);
2541 }
2542
x86_msi_msg_get_destid(struct msi_msg * msg,bool extid)2543 u32 x86_msi_msg_get_destid(struct msi_msg *msg, bool extid)
2544 {
2545 u32 dest = msg->arch_addr_lo.destid_0_7;
2546
2547 if (extid)
2548 dest |= msg->arch_addr_hi.destid_8_31 << 8;
2549 return dest;
2550 }
2551 EXPORT_SYMBOL_GPL(x86_msi_msg_get_destid);
2552
2553 /*
2554 * Override the generic EOI implementation with an optimized version.
2555 * Only called during early boot when only one CPU is active and with
2556 * interrupts disabled, so we know this does not race with actual APIC driver
2557 * use.
2558 */
apic_set_eoi_write(void (* eoi_write)(u32 reg,u32 v))2559 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2560 {
2561 struct apic **drv;
2562
2563 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2564 /* Should happen once for each apic */
2565 WARN_ON((*drv)->eoi_write == eoi_write);
2566 (*drv)->native_eoi_write = (*drv)->eoi_write;
2567 (*drv)->eoi_write = eoi_write;
2568 }
2569 }
2570
apic_bsp_up_setup(void)2571 static void __init apic_bsp_up_setup(void)
2572 {
2573 #ifdef CONFIG_X86_64
2574 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2575 #else
2576 /*
2577 * Hack: In case of kdump, after a crash, kernel might be booting
2578 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2579 * might be zero if read from MP tables. Get it from LAPIC.
2580 */
2581 # ifdef CONFIG_CRASH_DUMP
2582 boot_cpu_physical_apicid = read_apic_id();
2583 # endif
2584 #endif
2585 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2586 }
2587
2588 /**
2589 * apic_bsp_setup - Setup function for local apic and io-apic
2590 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2591 */
apic_bsp_setup(bool upmode)2592 static void __init apic_bsp_setup(bool upmode)
2593 {
2594 connect_bsp_APIC();
2595 if (upmode)
2596 apic_bsp_up_setup();
2597 setup_local_APIC();
2598
2599 enable_IO_APIC();
2600 end_local_APIC_setup();
2601 irq_remap_enable_fault_handling();
2602 setup_IO_APIC();
2603 lapic_update_legacy_vectors();
2604 }
2605
2606 #ifdef CONFIG_UP_LATE_INIT
up_late_init(void)2607 void __init up_late_init(void)
2608 {
2609 if (apic_intr_mode == APIC_PIC)
2610 return;
2611
2612 /* Setup local timer */
2613 x86_init.timers.setup_percpu_clockev();
2614 }
2615 #endif
2616
2617 /*
2618 * Power management
2619 */
2620 #ifdef CONFIG_PM
2621
2622 static struct {
2623 /*
2624 * 'active' is true if the local APIC was enabled by us and
2625 * not the BIOS; this signifies that we are also responsible
2626 * for disabling it before entering apm/acpi suspend
2627 */
2628 int active;
2629 /* r/w apic fields */
2630 unsigned int apic_id;
2631 unsigned int apic_taskpri;
2632 unsigned int apic_ldr;
2633 unsigned int apic_dfr;
2634 unsigned int apic_spiv;
2635 unsigned int apic_lvtt;
2636 unsigned int apic_lvtpc;
2637 unsigned int apic_lvt0;
2638 unsigned int apic_lvt1;
2639 unsigned int apic_lvterr;
2640 unsigned int apic_tmict;
2641 unsigned int apic_tdcr;
2642 unsigned int apic_thmr;
2643 unsigned int apic_cmci;
2644 } apic_pm_state;
2645
lapic_suspend(void)2646 static int lapic_suspend(void)
2647 {
2648 unsigned long flags;
2649 int maxlvt;
2650
2651 if (!apic_pm_state.active)
2652 return 0;
2653
2654 maxlvt = lapic_get_maxlvt();
2655
2656 apic_pm_state.apic_id = apic_read(APIC_ID);
2657 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2658 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2659 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2660 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2661 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2662 if (maxlvt >= 4)
2663 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2664 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2665 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2666 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2667 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2668 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2669 #ifdef CONFIG_X86_THERMAL_VECTOR
2670 if (maxlvt >= 5)
2671 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2672 #endif
2673 #ifdef CONFIG_X86_MCE_INTEL
2674 if (maxlvt >= 6)
2675 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2676 #endif
2677
2678 local_irq_save(flags);
2679
2680 /*
2681 * Mask IOAPIC before disabling the local APIC to prevent stale IRR
2682 * entries on some implementations.
2683 */
2684 mask_ioapic_entries();
2685
2686 disable_local_APIC();
2687
2688 irq_remapping_disable();
2689
2690 local_irq_restore(flags);
2691 return 0;
2692 }
2693
lapic_resume(void)2694 static void lapic_resume(void)
2695 {
2696 unsigned int l, h;
2697 unsigned long flags;
2698 int maxlvt;
2699
2700 if (!apic_pm_state.active)
2701 return;
2702
2703 local_irq_save(flags);
2704
2705 /*
2706 * IO-APIC and PIC have their own resume routines.
2707 * We just mask them here to make sure the interrupt
2708 * subsystem is completely quiet while we enable x2apic
2709 * and interrupt-remapping.
2710 */
2711 mask_ioapic_entries();
2712 legacy_pic->mask_all();
2713
2714 if (x2apic_mode) {
2715 __x2apic_enable();
2716 } else {
2717 /*
2718 * Make sure the APICBASE points to the right address
2719 *
2720 * FIXME! This will be wrong if we ever support suspend on
2721 * SMP! We'll need to do this as part of the CPU restore!
2722 */
2723 if (boot_cpu_data.x86 >= 6) {
2724 rdmsr(MSR_IA32_APICBASE, l, h);
2725 l &= ~MSR_IA32_APICBASE_BASE;
2726 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2727 wrmsr(MSR_IA32_APICBASE, l, h);
2728 }
2729 }
2730
2731 maxlvt = lapic_get_maxlvt();
2732 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2733 apic_write(APIC_ID, apic_pm_state.apic_id);
2734 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2735 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2736 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2737 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2738 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2739 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2740 #ifdef CONFIG_X86_THERMAL_VECTOR
2741 if (maxlvt >= 5)
2742 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2743 #endif
2744 #ifdef CONFIG_X86_MCE_INTEL
2745 if (maxlvt >= 6)
2746 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2747 #endif
2748 if (maxlvt >= 4)
2749 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2750 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2751 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2752 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2753 apic_write(APIC_ESR, 0);
2754 apic_read(APIC_ESR);
2755 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2756 apic_write(APIC_ESR, 0);
2757 apic_read(APIC_ESR);
2758
2759 irq_remapping_reenable(x2apic_mode);
2760
2761 local_irq_restore(flags);
2762 }
2763
2764 /*
2765 * This device has no shutdown method - fully functioning local APICs
2766 * are needed on every CPU up until machine_halt/restart/poweroff.
2767 */
2768
2769 static struct syscore_ops lapic_syscore_ops = {
2770 .resume = lapic_resume,
2771 .suspend = lapic_suspend,
2772 };
2773
apic_pm_activate(void)2774 static void apic_pm_activate(void)
2775 {
2776 apic_pm_state.active = 1;
2777 }
2778
init_lapic_sysfs(void)2779 static int __init init_lapic_sysfs(void)
2780 {
2781 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2782 if (boot_cpu_has(X86_FEATURE_APIC))
2783 register_syscore_ops(&lapic_syscore_ops);
2784
2785 return 0;
2786 }
2787
2788 /* local apic needs to resume before other devices access its registers. */
2789 core_initcall(init_lapic_sysfs);
2790
2791 #else /* CONFIG_PM */
2792
apic_pm_activate(void)2793 static void apic_pm_activate(void) { }
2794
2795 #endif /* CONFIG_PM */
2796
2797 #ifdef CONFIG_X86_64
2798
2799 static int multi_checked;
2800 static int multi;
2801
set_multi(const struct dmi_system_id * d)2802 static int set_multi(const struct dmi_system_id *d)
2803 {
2804 if (multi)
2805 return 0;
2806 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2807 multi = 1;
2808 return 0;
2809 }
2810
2811 static const struct dmi_system_id multi_dmi_table[] = {
2812 {
2813 .callback = set_multi,
2814 .ident = "IBM System Summit2",
2815 .matches = {
2816 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2817 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2818 },
2819 },
2820 {}
2821 };
2822
dmi_check_multi(void)2823 static void dmi_check_multi(void)
2824 {
2825 if (multi_checked)
2826 return;
2827
2828 dmi_check_system(multi_dmi_table);
2829 multi_checked = 1;
2830 }
2831
2832 /*
2833 * apic_is_clustered_box() -- Check if we can expect good TSC
2834 *
2835 * Thus far, the major user of this is IBM's Summit2 series:
2836 * Clustered boxes may have unsynced TSC problems if they are
2837 * multi-chassis.
2838 * Use DMI to check them
2839 */
apic_is_clustered_box(void)2840 int apic_is_clustered_box(void)
2841 {
2842 dmi_check_multi();
2843 return multi;
2844 }
2845 #endif
2846
2847 /*
2848 * APIC command line parameters
2849 */
setup_disableapic(char * arg)2850 static int __init setup_disableapic(char *arg)
2851 {
2852 disable_apic = 1;
2853 setup_clear_cpu_cap(X86_FEATURE_APIC);
2854 return 0;
2855 }
2856 early_param("disableapic", setup_disableapic);
2857
2858 /* same as disableapic, for compatibility */
setup_nolapic(char * arg)2859 static int __init setup_nolapic(char *arg)
2860 {
2861 return setup_disableapic(arg);
2862 }
2863 early_param("nolapic", setup_nolapic);
2864
parse_lapic_timer_c2_ok(char * arg)2865 static int __init parse_lapic_timer_c2_ok(char *arg)
2866 {
2867 local_apic_timer_c2_ok = 1;
2868 return 0;
2869 }
2870 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2871
parse_disable_apic_timer(char * arg)2872 static int __init parse_disable_apic_timer(char *arg)
2873 {
2874 disable_apic_timer = 1;
2875 return 0;
2876 }
2877 early_param("noapictimer", parse_disable_apic_timer);
2878
parse_nolapic_timer(char * arg)2879 static int __init parse_nolapic_timer(char *arg)
2880 {
2881 disable_apic_timer = 1;
2882 return 0;
2883 }
2884 early_param("nolapic_timer", parse_nolapic_timer);
2885
apic_set_verbosity(char * arg)2886 static int __init apic_set_verbosity(char *arg)
2887 {
2888 if (!arg) {
2889 #ifdef CONFIG_X86_64
2890 skip_ioapic_setup = 0;
2891 return 0;
2892 #endif
2893 return -EINVAL;
2894 }
2895
2896 if (strcmp("debug", arg) == 0)
2897 apic_verbosity = APIC_DEBUG;
2898 else if (strcmp("verbose", arg) == 0)
2899 apic_verbosity = APIC_VERBOSE;
2900 #ifdef CONFIG_X86_64
2901 else {
2902 pr_warn("APIC Verbosity level %s not recognised"
2903 " use apic=verbose or apic=debug\n", arg);
2904 return -EINVAL;
2905 }
2906 #endif
2907
2908 return 0;
2909 }
2910 early_param("apic", apic_set_verbosity);
2911
lapic_insert_resource(void)2912 static int __init lapic_insert_resource(void)
2913 {
2914 if (!apic_phys)
2915 return -1;
2916
2917 /* Put local APIC into the resource map. */
2918 lapic_resource.start = apic_phys;
2919 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2920 insert_resource(&iomem_resource, &lapic_resource);
2921
2922 return 0;
2923 }
2924
2925 /*
2926 * need call insert after e820__reserve_resources()
2927 * that is using request_resource
2928 */
2929 late_initcall(lapic_insert_resource);
2930
apic_set_disabled_cpu_apicid(char * arg)2931 static int __init apic_set_disabled_cpu_apicid(char *arg)
2932 {
2933 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2934 return -EINVAL;
2935
2936 return 0;
2937 }
2938 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2939
apic_set_extnmi(char * arg)2940 static int __init apic_set_extnmi(char *arg)
2941 {
2942 if (!arg)
2943 return -EINVAL;
2944
2945 if (!strncmp("all", arg, 3))
2946 apic_extnmi = APIC_EXTNMI_ALL;
2947 else if (!strncmp("none", arg, 4))
2948 apic_extnmi = APIC_EXTNMI_NONE;
2949 else if (!strncmp("bsp", arg, 3))
2950 apic_extnmi = APIC_EXTNMI_BSP;
2951 else {
2952 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2953 return -EINVAL;
2954 }
2955
2956 return 0;
2957 }
2958 early_param("apic_extnmi", apic_set_extnmi);
2959