1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * TI DA850/OMAP-L138 chip specific setup
4 *
5 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
6 *
7 * Derived from: arch/arm/mach-davinci/da830.c
8 * Original Copyrights follow:
9 *
10 * 2009 (c) MontaVista Software, Inc.
11 */
12
13 #include <linux/clk-provider.h>
14 #include <linux/clk/davinci.h>
15 #include <linux/clkdev.h>
16 #include <linux/cpufreq.h>
17 #include <linux/gpio.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/irqchip/irq-davinci-cp-intc.h>
21 #include <linux/mfd/da8xx-cfgchip.h>
22 #include <linux/platform_data/clk-da8xx-cfgchip.h>
23 #include <linux/platform_data/clk-davinci-pll.h>
24 #include <linux/platform_data/davinci-cpufreq.h>
25 #include <linux/platform_data/gpio-davinci.h>
26 #include <linux/platform_device.h>
27 #include <linux/regmap.h>
28 #include <linux/regulator/consumer.h>
29
30 #include <asm/mach/map.h>
31
32 #include <mach/common.h>
33 #include <mach/cputype.h>
34 #include <mach/da8xx.h>
35 #include <mach/pm.h>
36
37 #include <clocksource/timer-davinci.h>
38
39 #include "irqs.h"
40 #include "mux.h"
41
42 #define DA850_PLL1_BASE 0x01e1a000
43 #define DA850_TIMER64P2_BASE 0x01f0c000
44 #define DA850_TIMER64P3_BASE 0x01f0d000
45
46 #define DA850_REF_FREQ 24000000
47
48 /*
49 * Device specific mux setup
50 *
51 * soc description mux mode mode mux dbg
52 * reg offset mask mode
53 */
54 static const struct mux_config da850_pins[] = {
55 #ifdef CONFIG_DAVINCI_MUX
56 /* UART0 function */
57 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
58 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
59 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
60 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
61 /* UART1 function */
62 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
63 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
64 /* UART2 function */
65 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
66 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
67 /* I2C1 function */
68 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
69 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
70 /* I2C0 function */
71 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
72 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
73 /* EMAC function */
74 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
75 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
76 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
77 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
78 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
79 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
80 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
81 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
82 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
83 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
84 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
85 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
86 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
87 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
88 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
89 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
90 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
91 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
92 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
93 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
94 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
95 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
96 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
97 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
98 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
99 /* McASP function */
100 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
101 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
102 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
103 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
104 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
105 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
106 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
107 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
108 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
109 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
110 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
111 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
112 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
113 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
114 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
115 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
116 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
117 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
118 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
119 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
120 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
121 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
122 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
123 /* LCD function */
124 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
125 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
126 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
127 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
128 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
129 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
130 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
131 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
132 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
133 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
134 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
135 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
136 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
137 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
138 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
139 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
140 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
141 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
142 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
143 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
144 /* MMC/SD0 function */
145 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
146 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
147 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
148 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
149 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
150 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
151 /* MMC/SD1 function */
152 MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false)
153 MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false)
154 MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false)
155 MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false)
156 MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false)
157 MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false)
158 /* EMIF2.5/EMIFA function */
159 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
160 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
161 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
162 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
163 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
164 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
165 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
166 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
167 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
168 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
169 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
170 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
171 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
172 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
173 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
174 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
175 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
176 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
177 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
178 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
179 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
180 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
181 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
182 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
183 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
184 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
185 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
186 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
187 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
188 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
189 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
190 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
191 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
192 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
193 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
194 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
195 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
196 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
197 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
198 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
199 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
200 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
201 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
202 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
203 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
204 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
205 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
206 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
207 /* GPIO function */
208 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false)
209 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
210 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
211 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
212 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false)
213 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false)
214 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
215 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
216 MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false)
217 MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false)
218 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
219 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
220 /* VPIF Capture */
221 MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false)
222 MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false)
223 MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false)
224 MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false)
225 MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false)
226 MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false)
227 MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false)
228 MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false)
229 MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false)
230 MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false)
231 MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false)
232 MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false)
233 MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false)
234 MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false)
235 MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false)
236 MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false)
237 MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false)
238 MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false)
239 MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false)
240 MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false)
241 /* VPIF Display */
242 MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false)
243 MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false)
244 MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false)
245 MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false)
246 MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false)
247 MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false)
248 MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false)
249 MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false)
250 MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false)
251 MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false)
252 MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false)
253 MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false)
254 MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false)
255 MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false)
256 MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false)
257 MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false)
258 MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false)
259 MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false)
260 #endif
261 };
262
263 const short da850_i2c0_pins[] __initconst = {
264 DA850_I2C0_SDA, DA850_I2C0_SCL,
265 -1
266 };
267
268 const short da850_i2c1_pins[] __initconst = {
269 DA850_I2C1_SCL, DA850_I2C1_SDA,
270 -1
271 };
272
273 const short da850_lcdcntl_pins[] __initconst = {
274 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
275 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
276 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
277 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
278 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
279 -1
280 };
281
282 const short da850_vpif_capture_pins[] __initconst = {
283 DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
284 DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
285 DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
286 DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
287 DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
288 DA850_VPIF_CLKIN3,
289 -1
290 };
291
292 const short da850_vpif_display_pins[] __initconst = {
293 DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
294 DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
295 DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
296 DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
297 DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
298 DA850_VPIF_CLKO3,
299 -1
300 };
301
302 static struct map_desc da850_io_desc[] = {
303 {
304 .virtual = IO_VIRT,
305 .pfn = __phys_to_pfn(IO_PHYS),
306 .length = IO_SIZE,
307 .type = MT_DEVICE
308 },
309 {
310 .virtual = DA8XX_CP_INTC_VIRT,
311 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
312 .length = DA8XX_CP_INTC_SIZE,
313 .type = MT_DEVICE
314 },
315 };
316
317 /* Contents of JTAG ID register used to identify exact cpu type */
318 static struct davinci_id da850_ids[] = {
319 {
320 .variant = 0x0,
321 .part_no = 0xb7d1,
322 .manufacturer = 0x017, /* 0x02f >> 1 */
323 .cpu_id = DAVINCI_CPU_ID_DA850,
324 .name = "da850/omap-l138",
325 },
326 {
327 .variant = 0x1,
328 .part_no = 0xb7d1,
329 .manufacturer = 0x017, /* 0x02f >> 1 */
330 .cpu_id = DAVINCI_CPU_ID_DA850,
331 .name = "da850/omap-l138/am18x",
332 },
333 };
334
335 /*
336 * Bottom half of timer 0 is used for clock_event, top half for
337 * clocksource.
338 */
339 static const struct davinci_timer_cfg da850_timer_cfg = {
340 .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K),
341 .irq = {
342 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)),
343 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0)),
344 },
345 };
346
347 #ifdef CONFIG_CPU_FREQ
348 /*
349 * Notes:
350 * According to the TRM, minimum PLLM results in maximum power savings.
351 * The OPP definitions below should keep the PLLM as low as possible.
352 *
353 * The output of the PLLM must be between 300 to 600 MHz.
354 */
355 struct da850_opp {
356 unsigned int freq; /* in KHz */
357 unsigned int prediv;
358 unsigned int mult;
359 unsigned int postdiv;
360 unsigned int cvdd_min; /* in uV */
361 unsigned int cvdd_max; /* in uV */
362 };
363
364 static const struct da850_opp da850_opp_456 = {
365 .freq = 456000,
366 .prediv = 1,
367 .mult = 19,
368 .postdiv = 1,
369 .cvdd_min = 1300000,
370 .cvdd_max = 1350000,
371 };
372
373 static const struct da850_opp da850_opp_408 = {
374 .freq = 408000,
375 .prediv = 1,
376 .mult = 17,
377 .postdiv = 1,
378 .cvdd_min = 1300000,
379 .cvdd_max = 1350000,
380 };
381
382 static const struct da850_opp da850_opp_372 = {
383 .freq = 372000,
384 .prediv = 2,
385 .mult = 31,
386 .postdiv = 1,
387 .cvdd_min = 1200000,
388 .cvdd_max = 1320000,
389 };
390
391 static const struct da850_opp da850_opp_300 = {
392 .freq = 300000,
393 .prediv = 1,
394 .mult = 25,
395 .postdiv = 2,
396 .cvdd_min = 1200000,
397 .cvdd_max = 1320000,
398 };
399
400 static const struct da850_opp da850_opp_200 = {
401 .freq = 200000,
402 .prediv = 1,
403 .mult = 25,
404 .postdiv = 3,
405 .cvdd_min = 1100000,
406 .cvdd_max = 1160000,
407 };
408
409 static const struct da850_opp da850_opp_96 = {
410 .freq = 96000,
411 .prediv = 1,
412 .mult = 20,
413 .postdiv = 5,
414 .cvdd_min = 1000000,
415 .cvdd_max = 1050000,
416 };
417
418 #define OPP(freq) \
419 { \
420 .driver_data = (unsigned int) &da850_opp_##freq, \
421 .frequency = freq * 1000, \
422 }
423
424 static struct cpufreq_frequency_table da850_freq_table[] = {
425 OPP(456),
426 OPP(408),
427 OPP(372),
428 OPP(300),
429 OPP(200),
430 OPP(96),
431 {
432 .driver_data = 0,
433 .frequency = CPUFREQ_TABLE_END,
434 },
435 };
436
437 #ifdef CONFIG_REGULATOR
438 static int da850_set_voltage(unsigned int index);
439 static int da850_regulator_init(void);
440 #endif
441
442 static struct davinci_cpufreq_config cpufreq_info = {
443 .freq_table = da850_freq_table,
444 #ifdef CONFIG_REGULATOR
445 .init = da850_regulator_init,
446 .set_voltage = da850_set_voltage,
447 #endif
448 };
449
450 #ifdef CONFIG_REGULATOR
451 static struct regulator *cvdd;
452
da850_set_voltage(unsigned int index)453 static int da850_set_voltage(unsigned int index)
454 {
455 struct da850_opp *opp;
456
457 if (!cvdd)
458 return -ENODEV;
459
460 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
461
462 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
463 }
464
da850_regulator_init(void)465 static int da850_regulator_init(void)
466 {
467 cvdd = regulator_get(NULL, "cvdd");
468 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
469 " voltage scaling unsupported\n")) {
470 return PTR_ERR(cvdd);
471 }
472
473 return 0;
474 }
475 #endif
476
477 static struct platform_device da850_cpufreq_device = {
478 .name = "cpufreq-davinci",
479 .dev = {
480 .platform_data = &cpufreq_info,
481 },
482 .id = -1,
483 };
484
485 unsigned int da850_max_speed = 300000;
486
da850_register_cpufreq(char * async_clk)487 int da850_register_cpufreq(char *async_clk)
488 {
489 int i;
490
491 /* cpufreq driver can help keep an "async" clock constant */
492 if (async_clk)
493 clk_add_alias("async", da850_cpufreq_device.name,
494 async_clk, NULL);
495 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
496 if (da850_freq_table[i].frequency <= da850_max_speed) {
497 cpufreq_info.freq_table = &da850_freq_table[i];
498 break;
499 }
500 }
501
502 return platform_device_register(&da850_cpufreq_device);
503 }
504 #else
da850_register_cpufreq(char * async_clk)505 int __init da850_register_cpufreq(char *async_clk)
506 {
507 return 0;
508 }
509 #endif
510
511 /* VPIF resource, platform data */
512 static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
513
514 static struct resource da850_vpif_resource[] = {
515 {
516 .start = DA8XX_VPIF_BASE,
517 .end = DA8XX_VPIF_BASE + 0xfff,
518 .flags = IORESOURCE_MEM,
519 }
520 };
521
522 static struct platform_device da850_vpif_dev = {
523 .name = "vpif",
524 .id = -1,
525 .dev = {
526 .dma_mask = &da850_vpif_dma_mask,
527 .coherent_dma_mask = DMA_BIT_MASK(32),
528 },
529 .resource = da850_vpif_resource,
530 .num_resources = ARRAY_SIZE(da850_vpif_resource),
531 };
532
533 static struct resource da850_vpif_display_resource[] = {
534 {
535 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
536 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
537 .flags = IORESOURCE_IRQ,
538 },
539 };
540
541 static struct platform_device da850_vpif_display_dev = {
542 .name = "vpif_display",
543 .id = -1,
544 .dev = {
545 .dma_mask = &da850_vpif_dma_mask,
546 .coherent_dma_mask = DMA_BIT_MASK(32),
547 },
548 .resource = da850_vpif_display_resource,
549 .num_resources = ARRAY_SIZE(da850_vpif_display_resource),
550 };
551
552 static struct resource da850_vpif_capture_resource[] = {
553 {
554 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
555 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
556 .flags = IORESOURCE_IRQ,
557 },
558 {
559 .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
560 .end = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT),
561 .flags = IORESOURCE_IRQ,
562 },
563 };
564
565 static struct platform_device da850_vpif_capture_dev = {
566 .name = "vpif_capture",
567 .id = -1,
568 .dev = {
569 .dma_mask = &da850_vpif_dma_mask,
570 .coherent_dma_mask = DMA_BIT_MASK(32),
571 },
572 .resource = da850_vpif_capture_resource,
573 .num_resources = ARRAY_SIZE(da850_vpif_capture_resource),
574 };
575
da850_register_vpif(void)576 int __init da850_register_vpif(void)
577 {
578 return platform_device_register(&da850_vpif_dev);
579 }
580
da850_register_vpif_display(struct vpif_display_config * display_config)581 int __init da850_register_vpif_display(struct vpif_display_config
582 *display_config)
583 {
584 da850_vpif_display_dev.dev.platform_data = display_config;
585 return platform_device_register(&da850_vpif_display_dev);
586 }
587
da850_register_vpif_capture(struct vpif_capture_config * capture_config)588 int __init da850_register_vpif_capture(struct vpif_capture_config
589 *capture_config)
590 {
591 da850_vpif_capture_dev.dev.platform_data = capture_config;
592 return platform_device_register(&da850_vpif_capture_dev);
593 }
594
595 static struct davinci_gpio_platform_data da850_gpio_platform_data = {
596 .no_auto_base = true,
597 .base = 0,
598 .ngpio = 144,
599 };
600
da850_register_gpio(void)601 int __init da850_register_gpio(void)
602 {
603 return da8xx_register_gpio(&da850_gpio_platform_data);
604 }
605
606 static const struct davinci_soc_info davinci_soc_info_da850 = {
607 .io_desc = da850_io_desc,
608 .io_desc_num = ARRAY_SIZE(da850_io_desc),
609 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
610 .ids = da850_ids,
611 .ids_num = ARRAY_SIZE(da850_ids),
612 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
613 .pinmux_pins = da850_pins,
614 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
615 .emac_pdata = &da8xx_emac_pdata,
616 .sram_dma = DA8XX_SHARED_RAM_BASE,
617 .sram_len = SZ_128K,
618 };
619
da850_init(void)620 void __init da850_init(void)
621 {
622 davinci_common_init(&davinci_soc_info_da850);
623
624 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
625 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
626 return;
627
628 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
629 WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module");
630 }
631
632 static const struct davinci_cp_intc_config da850_cp_intc_config = {
633 .reg = {
634 .start = DA8XX_CP_INTC_BASE,
635 .end = DA8XX_CP_INTC_BASE + SZ_8K - 1,
636 .flags = IORESOURCE_MEM,
637 },
638 .num_irqs = DA850_N_CP_INTC_IRQ,
639 };
640
da850_init_irq(void)641 void __init da850_init_irq(void)
642 {
643 davinci_cp_intc_init(&da850_cp_intc_config);
644 }
645
da850_init_time(void)646 void __init da850_init_time(void)
647 {
648 void __iomem *pll0;
649 struct regmap *cfgchip;
650 struct clk *clk;
651 int rv;
652
653 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ);
654
655 pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K);
656 cfgchip = da8xx_get_cfgchip();
657
658 da850_pll0_init(NULL, pll0, cfgchip);
659
660 clk = clk_get(NULL, "timer0");
661 if (WARN_ON(IS_ERR(clk))) {
662 pr_err("Unable to get the timer clock\n");
663 return;
664 }
665
666 rv = davinci_timer_register(clk, &da850_timer_cfg);
667 WARN(rv, "Unable to register the timer: %d\n", rv);
668 }
669
670 static struct resource da850_pll1_resources[] = {
671 {
672 .start = DA850_PLL1_BASE,
673 .end = DA850_PLL1_BASE + SZ_4K - 1,
674 .flags = IORESOURCE_MEM,
675 },
676 };
677
678 static struct davinci_pll_platform_data da850_pll1_pdata;
679
680 static struct platform_device da850_pll1_device = {
681 .name = "da850-pll1",
682 .id = -1,
683 .resource = da850_pll1_resources,
684 .num_resources = ARRAY_SIZE(da850_pll1_resources),
685 .dev = {
686 .platform_data = &da850_pll1_pdata,
687 },
688 };
689
690 static struct resource da850_psc0_resources[] = {
691 {
692 .start = DA8XX_PSC0_BASE,
693 .end = DA8XX_PSC0_BASE + SZ_4K - 1,
694 .flags = IORESOURCE_MEM,
695 },
696 };
697
698 static struct platform_device da850_psc0_device = {
699 .name = "da850-psc0",
700 .id = -1,
701 .resource = da850_psc0_resources,
702 .num_resources = ARRAY_SIZE(da850_psc0_resources),
703 };
704
705 static struct resource da850_psc1_resources[] = {
706 {
707 .start = DA8XX_PSC1_BASE,
708 .end = DA8XX_PSC1_BASE + SZ_4K - 1,
709 .flags = IORESOURCE_MEM,
710 },
711 };
712
713 static struct platform_device da850_psc1_device = {
714 .name = "da850-psc1",
715 .id = -1,
716 .resource = da850_psc1_resources,
717 .num_resources = ARRAY_SIZE(da850_psc1_resources),
718 };
719
720 static struct da8xx_cfgchip_clk_platform_data da850_async1_pdata;
721
722 static struct platform_device da850_async1_clksrc_device = {
723 .name = "da850-async1-clksrc",
724 .id = -1,
725 .dev = {
726 .platform_data = &da850_async1_pdata,
727 },
728 };
729
730 static struct da8xx_cfgchip_clk_platform_data da850_async3_pdata;
731
732 static struct platform_device da850_async3_clksrc_device = {
733 .name = "da850-async3-clksrc",
734 .id = -1,
735 .dev = {
736 .platform_data = &da850_async3_pdata,
737 },
738 };
739
740 static struct da8xx_cfgchip_clk_platform_data da850_tbclksync_pdata;
741
742 static struct platform_device da850_tbclksync_device = {
743 .name = "da830-tbclksync",
744 .id = -1,
745 .dev = {
746 .platform_data = &da850_tbclksync_pdata,
747 },
748 };
749
da850_register_clocks(void)750 void __init da850_register_clocks(void)
751 {
752 /* PLL0 is registered in da850_init_time() */
753
754 da850_pll1_pdata.cfgchip = da8xx_get_cfgchip();
755 platform_device_register(&da850_pll1_device);
756
757 da850_async1_pdata.cfgchip = da8xx_get_cfgchip();
758 platform_device_register(&da850_async1_clksrc_device);
759
760 da850_async3_pdata.cfgchip = da8xx_get_cfgchip();
761 platform_device_register(&da850_async3_clksrc_device);
762
763 platform_device_register(&da850_psc0_device);
764
765 platform_device_register(&da850_psc1_device);
766
767 da850_tbclksync_pdata.cfgchip = da8xx_get_cfgchip();
768 platform_device_register(&da850_tbclksync_device);
769 }
770