1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * DBAu1000/1500/1100 PBAu1100/1500 board support
4 *
5 * Copyright 2000, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/gpio.h>
12 #include <linux/gpio/machine.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/leds.h>
16 #include <linux/mmc/host.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi_gpio.h>
21 #include <linux/spi/ads7846.h>
22 #include <asm/mach-au1x00/au1000.h>
23 #include <asm/mach-au1x00/gpio-au1000.h>
24 #include <asm/mach-au1x00/au1000_dma.h>
25 #include <asm/mach-au1x00/au1100_mmc.h>
26 #include <asm/mach-db1x00/bcsr.h>
27 #include <asm/reboot.h>
28 #include <prom.h>
29 #include "platform.h"
30
31 #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
32
33 const char *get_system_type(void);
34
db1000_board_setup(void)35 int __init db1000_board_setup(void)
36 {
37 /* initialize board register space */
38 bcsr_init(DB1000_BCSR_PHYS_ADDR,
39 DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
40
41 switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
42 case BCSR_WHOAMI_DB1000:
43 case BCSR_WHOAMI_DB1500:
44 case BCSR_WHOAMI_DB1100:
45 case BCSR_WHOAMI_PB1500:
46 case BCSR_WHOAMI_PB1500R2:
47 case BCSR_WHOAMI_PB1100:
48 pr_info("AMD Alchemy %s Board\n", get_system_type());
49 return 0;
50 }
51 return -ENODEV;
52 }
53
db1500_map_pci_irq(const struct pci_dev * d,u8 slot,u8 pin)54 static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
55 {
56 if ((slot < 12) || (slot > 13) || pin == 0)
57 return -1;
58 if (slot == 12)
59 return (pin == 1) ? AU1500_PCI_INTA : 0xff;
60 if (slot == 13) {
61 switch (pin) {
62 case 1: return AU1500_PCI_INTA;
63 case 2: return AU1500_PCI_INTB;
64 case 3: return AU1500_PCI_INTC;
65 case 4: return AU1500_PCI_INTD;
66 }
67 }
68 return -1;
69 }
70
71 static u64 au1xxx_all_dmamask = DMA_BIT_MASK(32);
72
73 static struct resource alchemy_pci_host_res[] = {
74 [0] = {
75 .start = AU1500_PCI_PHYS_ADDR,
76 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
77 .flags = IORESOURCE_MEM,
78 },
79 };
80
81 static struct alchemy_pci_platdata db1500_pci_pd = {
82 .board_map_irq = db1500_map_pci_irq,
83 };
84
85 static struct platform_device db1500_pci_host_dev = {
86 .dev.platform_data = &db1500_pci_pd,
87 .name = "alchemy-pci",
88 .id = 0,
89 .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
90 .resource = alchemy_pci_host_res,
91 };
92
db1500_pci_setup(void)93 int __init db1500_pci_setup(void)
94 {
95 return platform_device_register(&db1500_pci_host_dev);
96 }
97
98 static struct resource au1100_lcd_resources[] = {
99 [0] = {
100 .start = AU1100_LCD_PHYS_ADDR,
101 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
102 .flags = IORESOURCE_MEM,
103 },
104 [1] = {
105 .start = AU1100_LCD_INT,
106 .end = AU1100_LCD_INT,
107 .flags = IORESOURCE_IRQ,
108 }
109 };
110
111 static struct platform_device au1100_lcd_device = {
112 .name = "au1100-lcd",
113 .id = 0,
114 .dev = {
115 .dma_mask = &au1xxx_all_dmamask,
116 .coherent_dma_mask = DMA_BIT_MASK(32),
117 },
118 .num_resources = ARRAY_SIZE(au1100_lcd_resources),
119 .resource = au1100_lcd_resources,
120 };
121
122 static struct resource alchemy_ac97c_res[] = {
123 [0] = {
124 .start = AU1000_AC97_PHYS_ADDR,
125 .end = AU1000_AC97_PHYS_ADDR + 0xfff,
126 .flags = IORESOURCE_MEM,
127 },
128 [1] = {
129 .start = DMA_ID_AC97C_TX,
130 .end = DMA_ID_AC97C_TX,
131 .flags = IORESOURCE_DMA,
132 },
133 [2] = {
134 .start = DMA_ID_AC97C_RX,
135 .end = DMA_ID_AC97C_RX,
136 .flags = IORESOURCE_DMA,
137 },
138 };
139
140 static struct platform_device alchemy_ac97c_dev = {
141 .name = "alchemy-ac97c",
142 .id = -1,
143 .resource = alchemy_ac97c_res,
144 .num_resources = ARRAY_SIZE(alchemy_ac97c_res),
145 };
146
147 static struct platform_device alchemy_ac97c_dma_dev = {
148 .name = "alchemy-pcm-dma",
149 .id = 0,
150 };
151
152 static struct platform_device db1x00_codec_dev = {
153 .name = "ac97-codec",
154 .id = -1,
155 };
156
157 static struct platform_device db1x00_audio_dev = {
158 .name = "db1000-audio",
159 .dev = {
160 .dma_mask = &au1xxx_all_dmamask,
161 .coherent_dma_mask = DMA_BIT_MASK(32),
162 },
163 };
164
165 /******************************************************************************/
166
167 #ifdef CONFIG_MMC_AU1X
db1100_mmc_cd(int irq,void * ptr)168 static irqreturn_t db1100_mmc_cd(int irq, void *ptr)
169 {
170 mmc_detect_change(ptr, msecs_to_jiffies(500));
171 return IRQ_HANDLED;
172 }
173
db1100_mmc_cd_setup(void * mmc_host,int en)174 static int db1100_mmc_cd_setup(void *mmc_host, int en)
175 {
176 int ret = 0, irq;
177
178 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
179 irq = AU1100_GPIO19_INT;
180 else
181 irq = AU1100_GPIO14_INT; /* PB1100 SD0 CD# */
182
183 if (en) {
184 irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
185 ret = request_irq(irq, db1100_mmc_cd, 0,
186 "sd0_cd", mmc_host);
187 } else
188 free_irq(irq, mmc_host);
189 return ret;
190 }
191
db1100_mmc1_cd_setup(void * mmc_host,int en)192 static int db1100_mmc1_cd_setup(void *mmc_host, int en)
193 {
194 int ret = 0, irq;
195
196 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
197 irq = AU1100_GPIO20_INT;
198 else
199 irq = AU1100_GPIO15_INT; /* PB1100 SD1 CD# */
200
201 if (en) {
202 irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH);
203 ret = request_irq(irq, db1100_mmc_cd, 0,
204 "sd1_cd", mmc_host);
205 } else
206 free_irq(irq, mmc_host);
207 return ret;
208 }
209
db1100_mmc_card_readonly(void * mmc_host)210 static int db1100_mmc_card_readonly(void *mmc_host)
211 {
212 /* testing suggests that this bit is inverted */
213 return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 0 : 1;
214 }
215
db1100_mmc_card_inserted(void * mmc_host)216 static int db1100_mmc_card_inserted(void *mmc_host)
217 {
218 return !alchemy_gpio_get_value(19);
219 }
220
db1100_mmc_set_power(void * mmc_host,int state)221 static void db1100_mmc_set_power(void *mmc_host, int state)
222 {
223 int bit;
224
225 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
226 bit = BCSR_BOARD_SD0PWR;
227 else
228 bit = BCSR_BOARD_PB1100_SD0PWR;
229
230 if (state) {
231 bcsr_mod(BCSR_BOARD, 0, bit);
232 msleep(400); /* stabilization time */
233 } else
234 bcsr_mod(BCSR_BOARD, bit, 0);
235 }
236
db1100_mmcled_set(struct led_classdev * led,enum led_brightness b)237 static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b)
238 {
239 if (b != LED_OFF)
240 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
241 else
242 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
243 }
244
245 static struct led_classdev db1100_mmc_led = {
246 .brightness_set = db1100_mmcled_set,
247 };
248
db1100_mmc1_card_readonly(void * mmc_host)249 static int db1100_mmc1_card_readonly(void *mmc_host)
250 {
251 return (bcsr_read(BCSR_BOARD) & BCSR_BOARD_SD1WP) ? 1 : 0;
252 }
253
db1100_mmc1_card_inserted(void * mmc_host)254 static int db1100_mmc1_card_inserted(void *mmc_host)
255 {
256 return !alchemy_gpio_get_value(20);
257 }
258
db1100_mmc1_set_power(void * mmc_host,int state)259 static void db1100_mmc1_set_power(void *mmc_host, int state)
260 {
261 int bit;
262
263 if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100)
264 bit = BCSR_BOARD_SD1PWR;
265 else
266 bit = BCSR_BOARD_PB1100_SD1PWR;
267
268 if (state) {
269 bcsr_mod(BCSR_BOARD, 0, bit);
270 msleep(400); /* stabilization time */
271 } else
272 bcsr_mod(BCSR_BOARD, bit, 0);
273 }
274
db1100_mmc1led_set(struct led_classdev * led,enum led_brightness b)275 static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b)
276 {
277 if (b != LED_OFF)
278 bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0);
279 else
280 bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1);
281 }
282
283 static struct led_classdev db1100_mmc1_led = {
284 .brightness_set = db1100_mmc1led_set,
285 };
286
287 static struct au1xmmc_platform_data db1100_mmc_platdata[2] = {
288 [0] = {
289 .cd_setup = db1100_mmc_cd_setup,
290 .set_power = db1100_mmc_set_power,
291 .card_inserted = db1100_mmc_card_inserted,
292 .card_readonly = db1100_mmc_card_readonly,
293 .led = &db1100_mmc_led,
294 },
295 [1] = {
296 .cd_setup = db1100_mmc1_cd_setup,
297 .set_power = db1100_mmc1_set_power,
298 .card_inserted = db1100_mmc1_card_inserted,
299 .card_readonly = db1100_mmc1_card_readonly,
300 .led = &db1100_mmc1_led,
301 },
302 };
303
304 static struct resource au1100_mmc0_resources[] = {
305 [0] = {
306 .start = AU1100_SD0_PHYS_ADDR,
307 .end = AU1100_SD0_PHYS_ADDR + 0xfff,
308 .flags = IORESOURCE_MEM,
309 },
310 [1] = {
311 .start = AU1100_SD_INT,
312 .end = AU1100_SD_INT,
313 .flags = IORESOURCE_IRQ,
314 },
315 [2] = {
316 .start = DMA_ID_SD0_TX,
317 .end = DMA_ID_SD0_TX,
318 .flags = IORESOURCE_DMA,
319 },
320 [3] = {
321 .start = DMA_ID_SD0_RX,
322 .end = DMA_ID_SD0_RX,
323 .flags = IORESOURCE_DMA,
324 }
325 };
326
327 static struct platform_device db1100_mmc0_dev = {
328 .name = "au1xxx-mmc",
329 .id = 0,
330 .dev = {
331 .dma_mask = &au1xxx_all_dmamask,
332 .coherent_dma_mask = DMA_BIT_MASK(32),
333 .platform_data = &db1100_mmc_platdata[0],
334 },
335 .num_resources = ARRAY_SIZE(au1100_mmc0_resources),
336 .resource = au1100_mmc0_resources,
337 };
338
339 static struct resource au1100_mmc1_res[] = {
340 [0] = {
341 .start = AU1100_SD1_PHYS_ADDR,
342 .end = AU1100_SD1_PHYS_ADDR + 0xfff,
343 .flags = IORESOURCE_MEM,
344 },
345 [1] = {
346 .start = AU1100_SD_INT,
347 .end = AU1100_SD_INT,
348 .flags = IORESOURCE_IRQ,
349 },
350 [2] = {
351 .start = DMA_ID_SD1_TX,
352 .end = DMA_ID_SD1_TX,
353 .flags = IORESOURCE_DMA,
354 },
355 [3] = {
356 .start = DMA_ID_SD1_RX,
357 .end = DMA_ID_SD1_RX,
358 .flags = IORESOURCE_DMA,
359 }
360 };
361
362 static struct platform_device db1100_mmc1_dev = {
363 .name = "au1xxx-mmc",
364 .id = 1,
365 .dev = {
366 .dma_mask = &au1xxx_all_dmamask,
367 .coherent_dma_mask = DMA_BIT_MASK(32),
368 .platform_data = &db1100_mmc_platdata[1],
369 },
370 .num_resources = ARRAY_SIZE(au1100_mmc1_res),
371 .resource = au1100_mmc1_res,
372 };
373 #endif /* CONFIG_MMC_AU1X */
374
375 /******************************************************************************/
376
377 static struct ads7846_platform_data db1100_touch_pd = {
378 .model = 7846,
379 .vref_mv = 3300,
380 .gpio_pendown = 21,
381 };
382
383 static struct spi_gpio_platform_data db1100_spictl_pd = {
384 .num_chipselect = 1,
385 };
386
387 static struct spi_board_info db1100_spi_info[] __initdata = {
388 [0] = {
389 .modalias = "ads7846",
390 .max_speed_hz = 3250000,
391 .bus_num = 0,
392 .chip_select = 0,
393 .mode = 0,
394 .irq = AU1100_GPIO21_INT,
395 .platform_data = &db1100_touch_pd,
396 },
397 };
398
399 static struct platform_device db1100_spi_dev = {
400 .name = "spi_gpio",
401 .id = 0,
402 .dev = {
403 .platform_data = &db1100_spictl_pd,
404 .dma_mask = &au1xxx_all_dmamask,
405 .coherent_dma_mask = DMA_BIT_MASK(32),
406 },
407 };
408
409 /*
410 * Alchemy GPIO 2 has its base at 200 so the GPIO lines
411 * 207 thru 210 are GPIOs at offset 7 thru 10 at this chip.
412 */
413 static struct gpiod_lookup_table db1100_spi_gpiod_table = {
414 .dev_id = "spi_gpio",
415 .table = {
416 GPIO_LOOKUP("alchemy-gpio2", 9,
417 "sck", GPIO_ACTIVE_HIGH),
418 GPIO_LOOKUP("alchemy-gpio2", 8,
419 "mosi", GPIO_ACTIVE_HIGH),
420 GPIO_LOOKUP("alchemy-gpio2", 7,
421 "miso", GPIO_ACTIVE_HIGH),
422 GPIO_LOOKUP("alchemy-gpio2", 10,
423 "cs", GPIO_ACTIVE_HIGH),
424 { },
425 },
426 };
427
428 static struct platform_device *db1x00_devs[] = {
429 &db1x00_codec_dev,
430 &alchemy_ac97c_dma_dev,
431 &alchemy_ac97c_dev,
432 &db1x00_audio_dev,
433 };
434
435 static struct platform_device *db1100_devs[] = {
436 &au1100_lcd_device,
437 #ifdef CONFIG_MMC_AU1X
438 &db1100_mmc0_dev,
439 &db1100_mmc1_dev,
440 #endif
441 };
442
db1000_dev_setup(void)443 int __init db1000_dev_setup(void)
444 {
445 int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
446 int c0, c1, d0, d1, s0, s1, flashsize = 32, twosocks = 1;
447 unsigned long pfc;
448 struct clk *c, *p;
449
450 if (board == BCSR_WHOAMI_DB1500) {
451 c0 = AU1500_GPIO2_INT;
452 c1 = AU1500_GPIO5_INT;
453 d0 = 0; /* GPIO number, NOT irq! */
454 d1 = 3; /* GPIO number, NOT irq! */
455 s0 = AU1500_GPIO1_INT;
456 s1 = AU1500_GPIO4_INT;
457 } else if (board == BCSR_WHOAMI_DB1100) {
458 c0 = AU1100_GPIO2_INT;
459 c1 = AU1100_GPIO5_INT;
460 d0 = 0; /* GPIO number, NOT irq! */
461 d1 = 3; /* GPIO number, NOT irq! */
462 s0 = AU1100_GPIO1_INT;
463 s1 = AU1100_GPIO4_INT;
464
465 gpio_request(19, "sd0_cd");
466 gpio_request(20, "sd1_cd");
467 gpio_direction_input(19); /* sd0 cd# */
468 gpio_direction_input(20); /* sd1 cd# */
469
470 /* spi_gpio on SSI0 pins */
471 pfc = alchemy_rdsys(AU1000_SYS_PINFUNC);
472 pfc |= (1 << 0); /* SSI0 pins as GPIOs */
473 alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
474
475 spi_register_board_info(db1100_spi_info,
476 ARRAY_SIZE(db1100_spi_info));
477
478 /* link LCD clock to AUXPLL */
479 p = clk_get(NULL, "auxpll_clk");
480 c = clk_get(NULL, "lcd_intclk");
481 if (!IS_ERR(c) && !IS_ERR(p)) {
482 clk_set_parent(c, p);
483 clk_set_rate(c, clk_get_rate(p));
484 }
485 if (!IS_ERR(c))
486 clk_put(c);
487 if (!IS_ERR(p))
488 clk_put(p);
489
490 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
491 gpiod_add_lookup_table(&db1100_spi_gpiod_table);
492 platform_device_register(&db1100_spi_dev);
493 } else if (board == BCSR_WHOAMI_DB1000) {
494 c0 = AU1000_GPIO2_INT;
495 c1 = AU1000_GPIO5_INT;
496 d0 = 0; /* GPIO number, NOT irq! */
497 d1 = 3; /* GPIO number, NOT irq! */
498 s0 = AU1000_GPIO1_INT;
499 s1 = AU1000_GPIO4_INT;
500 } else if ((board == BCSR_WHOAMI_PB1500) ||
501 (board == BCSR_WHOAMI_PB1500R2)) {
502 c0 = AU1500_GPIO203_INT;
503 d0 = 1; /* GPIO number, NOT irq! */
504 s0 = AU1500_GPIO202_INT;
505 twosocks = 0;
506 flashsize = 64;
507 /* RTC and daughtercard irqs */
508 irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_LOW);
509 irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
510 /* EPSON S1D13806 0x1b000000
511 * SRAM 1MB/2MB 0x1a000000
512 * DS1693 RTC 0x0c000000
513 */
514 } else if (board == BCSR_WHOAMI_PB1100) {
515 c0 = AU1100_GPIO11_INT;
516 d0 = 9; /* GPIO number, NOT irq! */
517 s0 = AU1100_GPIO10_INT;
518 twosocks = 0;
519 flashsize = 64;
520 /* pendown, rtc, daughtercard irqs */
521 irq_set_irq_type(AU1100_GPIO8_INT, IRQ_TYPE_LEVEL_LOW);
522 irq_set_irq_type(AU1100_GPIO12_INT, IRQ_TYPE_LEVEL_LOW);
523 irq_set_irq_type(AU1100_GPIO13_INT, IRQ_TYPE_LEVEL_LOW);
524 /* EPSON S1D13806 0x1b000000
525 * SRAM 1MB/2MB 0x1a000000
526 * DiskOnChip 0x0d000000
527 * DS1693 RTC 0x0c000000
528 */
529 platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
530 } else
531 return 0; /* unknown board, no further dev setup to do */
532
533 irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW);
534 irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW);
535
536 db1x_register_pcmcia_socket(
537 AU1000_PCMCIA_ATTR_PHYS_ADDR,
538 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
539 AU1000_PCMCIA_MEM_PHYS_ADDR,
540 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
541 AU1000_PCMCIA_IO_PHYS_ADDR,
542 AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
543 c0, d0, /*s0*/0, 0, 0);
544
545 if (twosocks) {
546 irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW);
547 irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW);
548
549 db1x_register_pcmcia_socket(
550 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
551 AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
552 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
553 AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
554 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
555 AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
556 c1, d1, /*s1*/0, 0, 1);
557 }
558
559 platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs));
560 db1x_register_norflash(flashsize << 20, 4 /* 32bit */, F_SWAPPED);
561 return 0;
562 }
563