1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29
30
31 #include "dc_types.h"
32 #include "core_types.h"
33
34 #include "include/grph_object_id.h"
35 #include "include/logger_interface.h"
36
37 #include "dce_clock_source.h"
38 #include "clk_mgr.h"
39
40 #include "reg_helper.h"
41
42 #define REG(reg)\
43 (clk_src->regs->reg)
44
45 #define CTX \
46 clk_src->base.ctx
47
48 #define DC_LOGGER_INIT()
49
50 #undef FN
51 #define FN(reg_name, field_name) \
52 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
53
54 #define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6
55 #define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1
56 #define MAX_PLL_CALC_ERROR 0xFFFFFFFF
57
58 #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
59
get_ss_data_entry(struct dce110_clk_src * clk_src,enum signal_type signal,uint32_t pix_clk_khz)60 static const struct spread_spectrum_data *get_ss_data_entry(
61 struct dce110_clk_src *clk_src,
62 enum signal_type signal,
63 uint32_t pix_clk_khz)
64 {
65
66 uint32_t entrys_num;
67 uint32_t i;
68 struct spread_spectrum_data *ss_parm = NULL;
69 struct spread_spectrum_data *ret = NULL;
70
71 switch (signal) {
72 case SIGNAL_TYPE_DVI_SINGLE_LINK:
73 case SIGNAL_TYPE_DVI_DUAL_LINK:
74 ss_parm = clk_src->dvi_ss_params;
75 entrys_num = clk_src->dvi_ss_params_cnt;
76 break;
77
78 case SIGNAL_TYPE_HDMI_TYPE_A:
79 ss_parm = clk_src->hdmi_ss_params;
80 entrys_num = clk_src->hdmi_ss_params_cnt;
81 break;
82
83 case SIGNAL_TYPE_LVDS:
84 ss_parm = clk_src->lvds_ss_params;
85 entrys_num = clk_src->lvds_ss_params_cnt;
86 break;
87
88 case SIGNAL_TYPE_DISPLAY_PORT:
89 case SIGNAL_TYPE_DISPLAY_PORT_MST:
90 case SIGNAL_TYPE_EDP:
91 case SIGNAL_TYPE_VIRTUAL:
92 ss_parm = clk_src->dp_ss_params;
93 entrys_num = clk_src->dp_ss_params_cnt;
94 break;
95
96 default:
97 ss_parm = NULL;
98 entrys_num = 0;
99 break;
100 }
101
102 if (ss_parm == NULL)
103 return ret;
104
105 for (i = 0; i < entrys_num; ++i, ++ss_parm) {
106 if (ss_parm->freq_range_khz >= pix_clk_khz) {
107 ret = ss_parm;
108 break;
109 }
110 }
111
112 return ret;
113 }
114
115 /**
116 * calculate_fb_and_fractional_fb_divider - Calculates feedback and fractional
117 * feedback dividers values
118 *
119 * @calc_pll_cs: Pointer to clock source information
120 * @target_pix_clk_100hz: Desired frequency in 100 Hz
121 * @ref_divider: Reference divider (already known)
122 * @post_divider: Post Divider (already known)
123 * @feedback_divider_param: Pointer where to store
124 * calculated feedback divider value
125 * @fract_feedback_divider_param: Pointer where to store
126 * calculated fract feedback divider value
127 *
128 * return:
129 * It fills the locations pointed by feedback_divider_param
130 * and fract_feedback_divider_param
131 * It returns - true if feedback divider not 0
132 * - false should never happen)
133 */
calculate_fb_and_fractional_fb_divider(struct calc_pll_clock_source * calc_pll_cs,uint32_t target_pix_clk_100hz,uint32_t ref_divider,uint32_t post_divider,uint32_t * feedback_divider_param,uint32_t * fract_feedback_divider_param)134 static bool calculate_fb_and_fractional_fb_divider(
135 struct calc_pll_clock_source *calc_pll_cs,
136 uint32_t target_pix_clk_100hz,
137 uint32_t ref_divider,
138 uint32_t post_divider,
139 uint32_t *feedback_divider_param,
140 uint32_t *fract_feedback_divider_param)
141 {
142 uint64_t feedback_divider;
143
144 feedback_divider =
145 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider;
146 feedback_divider *= 10;
147 /* additional factor, since we divide by 10 afterwards */
148 feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor);
149 feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz * 10ull);
150
151 /*Round to the number of precision
152 * The following code replace the old code (ullfeedbackDivider + 5)/10
153 * for example if the difference between the number
154 * of fractional feedback decimal point and the fractional FB Divider precision
155 * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/
156
157 feedback_divider += 5ULL *
158 calc_pll_cs->fract_fb_divider_precision_factor;
159 feedback_divider =
160 div_u64(feedback_divider,
161 calc_pll_cs->fract_fb_divider_precision_factor * 10);
162 feedback_divider *= (uint64_t)
163 (calc_pll_cs->fract_fb_divider_precision_factor);
164
165 *feedback_divider_param =
166 div_u64_rem(
167 feedback_divider,
168 calc_pll_cs->fract_fb_divider_factor,
169 fract_feedback_divider_param);
170
171 if (*feedback_divider_param != 0)
172 return true;
173 return false;
174 }
175
176 /**
177 * calc_fb_divider_checking_tolerance - Calculates Feedback and
178 * Fractional Feedback divider values
179 * for passed Reference and Post divider,
180 * checking for tolerance.
181 * @calc_pll_cs: Pointer to clock source information
182 * @pll_settings: Pointer to PLL settings
183 * @ref_divider: Reference divider (already known)
184 * @post_divider: Post Divider (already known)
185 * @tolerance: Tolerance for Calculated Pixel Clock to be within
186 *
187 * return:
188 * It fills the PLLSettings structure with PLL Dividers values
189 * if calculated values are within required tolerance
190 * It returns - true if error is within tolerance
191 * - false if error is not within tolerance
192 */
calc_fb_divider_checking_tolerance(struct calc_pll_clock_source * calc_pll_cs,struct pll_settings * pll_settings,uint32_t ref_divider,uint32_t post_divider,uint32_t tolerance)193 static bool calc_fb_divider_checking_tolerance(
194 struct calc_pll_clock_source *calc_pll_cs,
195 struct pll_settings *pll_settings,
196 uint32_t ref_divider,
197 uint32_t post_divider,
198 uint32_t tolerance)
199 {
200 uint32_t feedback_divider;
201 uint32_t fract_feedback_divider;
202 uint32_t actual_calculated_clock_100hz;
203 uint32_t abs_err;
204 uint64_t actual_calc_clk_100hz;
205
206 calculate_fb_and_fractional_fb_divider(
207 calc_pll_cs,
208 pll_settings->adjusted_pix_clk_100hz,
209 ref_divider,
210 post_divider,
211 &feedback_divider,
212 &fract_feedback_divider);
213
214 /*Actual calculated value*/
215 actual_calc_clk_100hz = (uint64_t)feedback_divider *
216 calc_pll_cs->fract_fb_divider_factor +
217 fract_feedback_divider;
218 actual_calc_clk_100hz *= calc_pll_cs->ref_freq_khz * 10;
219 actual_calc_clk_100hz =
220 div_u64(actual_calc_clk_100hz,
221 ref_divider * post_divider *
222 calc_pll_cs->fract_fb_divider_factor);
223
224 actual_calculated_clock_100hz = (uint32_t)(actual_calc_clk_100hz);
225
226 abs_err = (actual_calculated_clock_100hz >
227 pll_settings->adjusted_pix_clk_100hz)
228 ? actual_calculated_clock_100hz -
229 pll_settings->adjusted_pix_clk_100hz
230 : pll_settings->adjusted_pix_clk_100hz -
231 actual_calculated_clock_100hz;
232
233 if (abs_err <= tolerance) {
234 /*found good values*/
235 pll_settings->reference_freq = calc_pll_cs->ref_freq_khz;
236 pll_settings->reference_divider = ref_divider;
237 pll_settings->feedback_divider = feedback_divider;
238 pll_settings->fract_feedback_divider = fract_feedback_divider;
239 pll_settings->pix_clk_post_divider = post_divider;
240 pll_settings->calculated_pix_clk_100hz =
241 actual_calculated_clock_100hz;
242 pll_settings->vco_freq =
243 div_u64((u64)actual_calculated_clock_100hz * post_divider, 10);
244 return true;
245 }
246 return false;
247 }
248
calc_pll_dividers_in_range(struct calc_pll_clock_source * calc_pll_cs,struct pll_settings * pll_settings,uint32_t min_ref_divider,uint32_t max_ref_divider,uint32_t min_post_divider,uint32_t max_post_divider,uint32_t err_tolerance)249 static bool calc_pll_dividers_in_range(
250 struct calc_pll_clock_source *calc_pll_cs,
251 struct pll_settings *pll_settings,
252 uint32_t min_ref_divider,
253 uint32_t max_ref_divider,
254 uint32_t min_post_divider,
255 uint32_t max_post_divider,
256 uint32_t err_tolerance)
257 {
258 uint32_t ref_divider;
259 uint32_t post_divider;
260 uint32_t tolerance;
261
262 /* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25%
263 * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/
264 tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) /
265 100000;
266 if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE)
267 tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE;
268
269 for (
270 post_divider = max_post_divider;
271 post_divider >= min_post_divider;
272 --post_divider) {
273 for (
274 ref_divider = min_ref_divider;
275 ref_divider <= max_ref_divider;
276 ++ref_divider) {
277 if (calc_fb_divider_checking_tolerance(
278 calc_pll_cs,
279 pll_settings,
280 ref_divider,
281 post_divider,
282 tolerance)) {
283 return true;
284 }
285 }
286 }
287
288 return false;
289 }
290
calculate_pixel_clock_pll_dividers(struct calc_pll_clock_source * calc_pll_cs,struct pll_settings * pll_settings)291 static uint32_t calculate_pixel_clock_pll_dividers(
292 struct calc_pll_clock_source *calc_pll_cs,
293 struct pll_settings *pll_settings)
294 {
295 uint32_t err_tolerance;
296 uint32_t min_post_divider;
297 uint32_t max_post_divider;
298 uint32_t min_ref_divider;
299 uint32_t max_ref_divider;
300
301 if (pll_settings->adjusted_pix_clk_100hz == 0) {
302 DC_LOG_ERROR(
303 "%s Bad requested pixel clock", __func__);
304 return MAX_PLL_CALC_ERROR;
305 }
306
307 /* 1) Find Post divider ranges */
308 if (pll_settings->pix_clk_post_divider) {
309 min_post_divider = pll_settings->pix_clk_post_divider;
310 max_post_divider = pll_settings->pix_clk_post_divider;
311 } else {
312 min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider;
313 if (min_post_divider * pll_settings->adjusted_pix_clk_100hz <
314 calc_pll_cs->min_vco_khz * 10) {
315 min_post_divider = calc_pll_cs->min_vco_khz * 10 /
316 pll_settings->adjusted_pix_clk_100hz;
317 if ((min_post_divider *
318 pll_settings->adjusted_pix_clk_100hz) <
319 calc_pll_cs->min_vco_khz * 10)
320 min_post_divider++;
321 }
322
323 max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider;
324 if (max_post_divider * pll_settings->adjusted_pix_clk_100hz
325 > calc_pll_cs->max_vco_khz * 10)
326 max_post_divider = calc_pll_cs->max_vco_khz * 10 /
327 pll_settings->adjusted_pix_clk_100hz;
328 }
329
330 /* 2) Find Reference divider ranges
331 * When SS is enabled, or for Display Port even without SS,
332 * pll_settings->referenceDivider is not zero.
333 * So calculate PPLL FB and fractional FB divider
334 * using the passed reference divider*/
335
336 if (pll_settings->reference_divider) {
337 min_ref_divider = pll_settings->reference_divider;
338 max_ref_divider = pll_settings->reference_divider;
339 } else {
340 min_ref_divider = ((calc_pll_cs->ref_freq_khz
341 / calc_pll_cs->max_pll_input_freq_khz)
342 > calc_pll_cs->min_pll_ref_divider)
343 ? calc_pll_cs->ref_freq_khz
344 / calc_pll_cs->max_pll_input_freq_khz
345 : calc_pll_cs->min_pll_ref_divider;
346
347 max_ref_divider = ((calc_pll_cs->ref_freq_khz
348 / calc_pll_cs->min_pll_input_freq_khz)
349 < calc_pll_cs->max_pll_ref_divider)
350 ? calc_pll_cs->ref_freq_khz /
351 calc_pll_cs->min_pll_input_freq_khz
352 : calc_pll_cs->max_pll_ref_divider;
353 }
354
355 /* If some parameters are invalid we could have scenario when "min">"max"
356 * which produced endless loop later.
357 * We should investigate why we get the wrong parameters.
358 * But to follow the similar logic when "adjustedPixelClock" is set to be 0
359 * it is better to return here than cause system hang/watchdog timeout later.
360 * ## SVS Wed 15 Jul 2009 */
361
362 if (min_post_divider > max_post_divider) {
363 DC_LOG_ERROR(
364 "%s Post divider range is invalid", __func__);
365 return MAX_PLL_CALC_ERROR;
366 }
367
368 if (min_ref_divider > max_ref_divider) {
369 DC_LOG_ERROR(
370 "%s Reference divider range is invalid", __func__);
371 return MAX_PLL_CALC_ERROR;
372 }
373
374 /* 3) Try to find PLL dividers given ranges
375 * starting with minimal error tolerance.
376 * Increase error tolerance until PLL dividers found*/
377 err_tolerance = MAX_PLL_CALC_ERROR;
378
379 while (!calc_pll_dividers_in_range(
380 calc_pll_cs,
381 pll_settings,
382 min_ref_divider,
383 max_ref_divider,
384 min_post_divider,
385 max_post_divider,
386 err_tolerance))
387 err_tolerance += (err_tolerance > 10)
388 ? (err_tolerance / 10)
389 : 1;
390
391 return err_tolerance;
392 }
393
pll_adjust_pix_clk(struct dce110_clk_src * clk_src,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)394 static bool pll_adjust_pix_clk(
395 struct dce110_clk_src *clk_src,
396 struct pixel_clk_params *pix_clk_params,
397 struct pll_settings *pll_settings)
398 {
399 uint32_t actual_pix_clk_100hz = 0;
400 uint32_t requested_clk_100hz = 0;
401 struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = {
402 0 };
403 enum bp_result bp_result;
404 switch (pix_clk_params->signal_type) {
405 case SIGNAL_TYPE_HDMI_TYPE_A: {
406 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
407 if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
408 switch (pix_clk_params->color_depth) {
409 case COLOR_DEPTH_101010:
410 requested_clk_100hz = (requested_clk_100hz * 5) >> 2;
411 break; /* x1.25*/
412 case COLOR_DEPTH_121212:
413 requested_clk_100hz = (requested_clk_100hz * 6) >> 2;
414 break; /* x1.5*/
415 case COLOR_DEPTH_161616:
416 requested_clk_100hz = requested_clk_100hz * 2;
417 break; /* x2.0*/
418 default:
419 break;
420 }
421 }
422 actual_pix_clk_100hz = requested_clk_100hz;
423 }
424 break;
425
426 case SIGNAL_TYPE_DISPLAY_PORT:
427 case SIGNAL_TYPE_DISPLAY_PORT_MST:
428 case SIGNAL_TYPE_EDP:
429 requested_clk_100hz = pix_clk_params->requested_sym_clk * 10;
430 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
431 break;
432
433 default:
434 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
435 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
436 break;
437 }
438
439 bp_adjust_pixel_clock_params.pixel_clock = requested_clk_100hz / 10;
440 bp_adjust_pixel_clock_params.
441 encoder_object_id = pix_clk_params->encoder_object_id;
442 bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
443 bp_adjust_pixel_clock_params.
444 ss_enable = pix_clk_params->flags.ENABLE_SS;
445 bp_result = clk_src->bios->funcs->adjust_pixel_clock(
446 clk_src->bios, &bp_adjust_pixel_clock_params);
447 if (bp_result == BP_RESULT_OK) {
448 pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz;
449 pll_settings->adjusted_pix_clk_100hz =
450 bp_adjust_pixel_clock_params.adjusted_pixel_clock * 10;
451 pll_settings->reference_divider =
452 bp_adjust_pixel_clock_params.reference_divider;
453 pll_settings->pix_clk_post_divider =
454 bp_adjust_pixel_clock_params.pixel_clock_post_divider;
455
456 return true;
457 }
458
459 return false;
460 }
461
462 /*
463 * Calculate PLL Dividers for given Clock Value.
464 * First will call VBIOS Adjust Exec table to check if requested Pixel clock
465 * will be Adjusted based on usage.
466 * Then it will calculate PLL Dividers for this Adjusted clock using preferred
467 * method (Maximum VCO frequency).
468 *
469 * \return
470 * Calculation error in units of 0.01%
471 */
472
dce110_get_pix_clk_dividers_helper(struct dce110_clk_src * clk_src,struct pll_settings * pll_settings,struct pixel_clk_params * pix_clk_params)473 static uint32_t dce110_get_pix_clk_dividers_helper (
474 struct dce110_clk_src *clk_src,
475 struct pll_settings *pll_settings,
476 struct pixel_clk_params *pix_clk_params)
477 {
478 uint32_t field = 0;
479 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
480 DC_LOGGER_INIT();
481 /* Check if reference clock is external (not pcie/xtalin)
482 * HW Dce80 spec:
483 * 00 - PCIE_REFCLK, 01 - XTALIN, 02 - GENERICA, 03 - GENERICB
484 * 04 - HSYNCA, 05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */
485 REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field);
486 pll_settings->use_external_clk = (field > 1);
487
488 /* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always
489 * (we do not care any more from SI for some older DP Sink which
490 * does not report SS support, no known issues) */
491 if ((pix_clk_params->flags.ENABLE_SS) ||
492 (dc_is_dp_signal(pix_clk_params->signal_type))) {
493
494 const struct spread_spectrum_data *ss_data = get_ss_data_entry(
495 clk_src,
496 pix_clk_params->signal_type,
497 pll_settings->adjusted_pix_clk_100hz / 10);
498
499 if (NULL != ss_data)
500 pll_settings->ss_percentage = ss_data->percentage;
501 }
502
503 /* Check VBIOS AdjustPixelClock Exec table */
504 if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {
505 /* Should never happen, ASSERT and fill up values to be able
506 * to continue. */
507 DC_LOG_ERROR(
508 "%s: Failed to adjust pixel clock!!", __func__);
509 pll_settings->actual_pix_clk_100hz =
510 pix_clk_params->requested_pix_clk_100hz;
511 pll_settings->adjusted_pix_clk_100hz =
512 pix_clk_params->requested_pix_clk_100hz;
513
514 if (dc_is_dp_signal(pix_clk_params->signal_type))
515 pll_settings->adjusted_pix_clk_100hz = 1000000;
516 }
517
518 /* Calculate Dividers */
519 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
520 /*Calculate Dividers by HDMI object, no SS case or SS case */
521 pll_calc_error =
522 calculate_pixel_clock_pll_dividers(
523 &clk_src->calc_pll_hdmi,
524 pll_settings);
525 else
526 /*Calculate Dividers by default object, no SS case or SS case */
527 pll_calc_error =
528 calculate_pixel_clock_pll_dividers(
529 &clk_src->calc_pll,
530 pll_settings);
531
532 return pll_calc_error;
533 }
534
dce112_get_pix_clk_dividers_helper(struct dce110_clk_src * clk_src,struct pll_settings * pll_settings,struct pixel_clk_params * pix_clk_params)535 static void dce112_get_pix_clk_dividers_helper (
536 struct dce110_clk_src *clk_src,
537 struct pll_settings *pll_settings,
538 struct pixel_clk_params *pix_clk_params)
539 {
540 uint32_t actual_pixel_clock_100hz;
541
542 actual_pixel_clock_100hz = pix_clk_params->requested_pix_clk_100hz;
543 /* Calculate Dividers */
544 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
545 switch (pix_clk_params->color_depth) {
546 case COLOR_DEPTH_101010:
547 actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2;
548 actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10;
549 break;
550 case COLOR_DEPTH_121212:
551 actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2;
552 actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10;
553 break;
554 case COLOR_DEPTH_161616:
555 actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2;
556 break;
557 default:
558 break;
559 }
560 }
561 pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz;
562 pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz;
563 pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
564 }
565
dce110_get_pix_clk_dividers(struct clock_source * cs,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)566 static uint32_t dce110_get_pix_clk_dividers(
567 struct clock_source *cs,
568 struct pixel_clk_params *pix_clk_params,
569 struct pll_settings *pll_settings)
570 {
571 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
572 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
573 DC_LOGGER_INIT();
574
575 if (pix_clk_params == NULL || pll_settings == NULL
576 || pix_clk_params->requested_pix_clk_100hz == 0) {
577 DC_LOG_ERROR(
578 "%s: Invalid parameters!!\n", __func__);
579 return pll_calc_error;
580 }
581
582 memset(pll_settings, 0, sizeof(*pll_settings));
583
584 if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
585 cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
586 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
587 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
588 pll_settings->actual_pix_clk_100hz =
589 pix_clk_params->requested_pix_clk_100hz;
590 return 0;
591 }
592
593 pll_calc_error = dce110_get_pix_clk_dividers_helper(clk_src,
594 pll_settings, pix_clk_params);
595
596 return pll_calc_error;
597 }
598
dce112_get_pix_clk_dividers(struct clock_source * cs,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)599 static uint32_t dce112_get_pix_clk_dividers(
600 struct clock_source *cs,
601 struct pixel_clk_params *pix_clk_params,
602 struct pll_settings *pll_settings)
603 {
604 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
605 DC_LOGGER_INIT();
606
607 if (pix_clk_params == NULL || pll_settings == NULL
608 || pix_clk_params->requested_pix_clk_100hz == 0) {
609 DC_LOG_ERROR(
610 "%s: Invalid parameters!!\n", __func__);
611 return -1;
612 }
613
614 memset(pll_settings, 0, sizeof(*pll_settings));
615
616 if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
617 cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
618 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10;
619 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10;
620 pll_settings->actual_pix_clk_100hz =
621 pix_clk_params->requested_pix_clk_100hz;
622 return -1;
623 }
624
625 dce112_get_pix_clk_dividers_helper(clk_src,
626 pll_settings, pix_clk_params);
627
628 return 0;
629 }
630
disable_spread_spectrum(struct dce110_clk_src * clk_src)631 static bool disable_spread_spectrum(struct dce110_clk_src *clk_src)
632 {
633 enum bp_result result;
634 struct bp_spread_spectrum_parameters bp_ss_params = {0};
635
636 bp_ss_params.pll_id = clk_src->base.id;
637
638 /*Call ASICControl to process ATOMBIOS Exec table*/
639 result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll(
640 clk_src->bios,
641 &bp_ss_params,
642 false);
643
644 return result == BP_RESULT_OK;
645 }
646
calculate_ss(const struct pll_settings * pll_settings,const struct spread_spectrum_data * ss_data,struct delta_sigma_data * ds_data)647 static bool calculate_ss(
648 const struct pll_settings *pll_settings,
649 const struct spread_spectrum_data *ss_data,
650 struct delta_sigma_data *ds_data)
651 {
652 struct fixed31_32 fb_div;
653 struct fixed31_32 ss_amount;
654 struct fixed31_32 ss_nslip_amount;
655 struct fixed31_32 ss_ds_frac_amount;
656 struct fixed31_32 ss_step_size;
657 struct fixed31_32 modulation_time;
658
659 if (ds_data == NULL)
660 return false;
661 if (ss_data == NULL)
662 return false;
663 if (ss_data->percentage == 0)
664 return false;
665 if (pll_settings == NULL)
666 return false;
667
668 memset(ds_data, 0, sizeof(struct delta_sigma_data));
669
670 /* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/
671 /* 6 decimal point support in fractional feedback divider */
672 fb_div = dc_fixpt_from_fraction(
673 pll_settings->fract_feedback_divider, 1000000);
674 fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider);
675
676 ds_data->ds_frac_amount = 0;
677 /*spreadSpectrumPercentage is in the unit of .01%,
678 * so have to divided by 100 * 100*/
679 ss_amount = dc_fixpt_mul(
680 fb_div, dc_fixpt_from_fraction(ss_data->percentage,
681 100 * ss_data->percentage_divider));
682 ds_data->feedback_amount = dc_fixpt_floor(ss_amount);
683
684 ss_nslip_amount = dc_fixpt_sub(ss_amount,
685 dc_fixpt_from_int(ds_data->feedback_amount));
686 ss_nslip_amount = dc_fixpt_mul_int(ss_nslip_amount, 10);
687 ds_data->nfrac_amount = dc_fixpt_floor(ss_nslip_amount);
688
689 ss_ds_frac_amount = dc_fixpt_sub(ss_nslip_amount,
690 dc_fixpt_from_int(ds_data->nfrac_amount));
691 ss_ds_frac_amount = dc_fixpt_mul_int(ss_ds_frac_amount, 65536);
692 ds_data->ds_frac_amount = dc_fixpt_floor(ss_ds_frac_amount);
693
694 /* compute SS_STEP_SIZE_DSFRAC */
695 modulation_time = dc_fixpt_from_fraction(
696 pll_settings->reference_freq * 1000,
697 pll_settings->reference_divider * ss_data->modulation_freq_hz);
698
699 if (ss_data->flags.CENTER_SPREAD)
700 modulation_time = dc_fixpt_div_int(modulation_time, 4);
701 else
702 modulation_time = dc_fixpt_div_int(modulation_time, 2);
703
704 ss_step_size = dc_fixpt_div(ss_amount, modulation_time);
705 /* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/
706 ss_step_size = dc_fixpt_mul_int(ss_step_size, 65536 * 10);
707 ds_data->ds_frac_size = dc_fixpt_floor(ss_step_size);
708
709 return true;
710 }
711
enable_spread_spectrum(struct dce110_clk_src * clk_src,enum signal_type signal,struct pll_settings * pll_settings)712 static bool enable_spread_spectrum(
713 struct dce110_clk_src *clk_src,
714 enum signal_type signal, struct pll_settings *pll_settings)
715 {
716 struct bp_spread_spectrum_parameters bp_params = {0};
717 struct delta_sigma_data d_s_data;
718 const struct spread_spectrum_data *ss_data = NULL;
719
720 ss_data = get_ss_data_entry(
721 clk_src,
722 signal,
723 pll_settings->calculated_pix_clk_100hz / 10);
724
725 /* Pixel clock PLL has been programmed to generate desired pixel clock,
726 * now enable SS on pixel clock */
727 /* TODO is it OK to return true not doing anything ??*/
728 if (ss_data != NULL && pll_settings->ss_percentage != 0) {
729 if (calculate_ss(pll_settings, ss_data, &d_s_data)) {
730 bp_params.ds.feedback_amount =
731 d_s_data.feedback_amount;
732 bp_params.ds.nfrac_amount =
733 d_s_data.nfrac_amount;
734 bp_params.ds.ds_frac_size = d_s_data.ds_frac_size;
735 bp_params.ds_frac_amount =
736 d_s_data.ds_frac_amount;
737 bp_params.flags.DS_TYPE = 1;
738 bp_params.pll_id = clk_src->base.id;
739 bp_params.percentage = ss_data->percentage;
740 if (ss_data->flags.CENTER_SPREAD)
741 bp_params.flags.CENTER_SPREAD = 1;
742 if (ss_data->flags.EXTERNAL_SS)
743 bp_params.flags.EXTERNAL_SS = 1;
744
745 if (BP_RESULT_OK !=
746 clk_src->bios->funcs->
747 enable_spread_spectrum_on_ppll(
748 clk_src->bios,
749 &bp_params,
750 true))
751 return false;
752 } else
753 return false;
754 }
755 return true;
756 }
757
dce110_program_pixel_clk_resync(struct dce110_clk_src * clk_src,enum signal_type signal_type,enum dc_color_depth colordepth)758 static void dce110_program_pixel_clk_resync(
759 struct dce110_clk_src *clk_src,
760 enum signal_type signal_type,
761 enum dc_color_depth colordepth)
762 {
763 REG_UPDATE(RESYNC_CNTL,
764 DCCG_DEEP_COLOR_CNTL1, 0);
765 /*
766 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1)
767 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
768 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2)
769 48 bit mode: TMDS clock = 2 x pixel clock (2:1)
770 */
771 if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
772 return;
773
774 switch (colordepth) {
775 case COLOR_DEPTH_888:
776 REG_UPDATE(RESYNC_CNTL,
777 DCCG_DEEP_COLOR_CNTL1, 0);
778 break;
779 case COLOR_DEPTH_101010:
780 REG_UPDATE(RESYNC_CNTL,
781 DCCG_DEEP_COLOR_CNTL1, 1);
782 break;
783 case COLOR_DEPTH_121212:
784 REG_UPDATE(RESYNC_CNTL,
785 DCCG_DEEP_COLOR_CNTL1, 2);
786 break;
787 case COLOR_DEPTH_161616:
788 REG_UPDATE(RESYNC_CNTL,
789 DCCG_DEEP_COLOR_CNTL1, 3);
790 break;
791 default:
792 break;
793 }
794 }
795
dce112_program_pixel_clk_resync(struct dce110_clk_src * clk_src,enum signal_type signal_type,enum dc_color_depth colordepth,bool enable_ycbcr420)796 static void dce112_program_pixel_clk_resync(
797 struct dce110_clk_src *clk_src,
798 enum signal_type signal_type,
799 enum dc_color_depth colordepth,
800 bool enable_ycbcr420)
801 {
802 uint32_t deep_color_cntl = 0;
803 uint32_t double_rate_enable = 0;
804
805 /*
806 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1)
807 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
808 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2)
809 48 bit mode: TMDS clock = 2 x pixel clock (2:1)
810 */
811 if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
812 double_rate_enable = enable_ycbcr420 ? 1 : 0;
813
814 switch (colordepth) {
815 case COLOR_DEPTH_888:
816 deep_color_cntl = 0;
817 break;
818 case COLOR_DEPTH_101010:
819 deep_color_cntl = 1;
820 break;
821 case COLOR_DEPTH_121212:
822 deep_color_cntl = 2;
823 break;
824 case COLOR_DEPTH_161616:
825 deep_color_cntl = 3;
826 break;
827 default:
828 break;
829 }
830 }
831
832 if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE)
833 REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
834 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl,
835 PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable);
836 else
837 REG_UPDATE(PIXCLK_RESYNC_CNTL,
838 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl);
839
840 }
841
dce110_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)842 static bool dce110_program_pix_clk(
843 struct clock_source *clock_source,
844 struct pixel_clk_params *pix_clk_params,
845 struct pll_settings *pll_settings)
846 {
847 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
848 struct bp_pixel_clock_parameters bp_pc_params = {0};
849
850 /* First disable SS
851 * ATOMBIOS will enable by default SS on PLL for DP,
852 * do not disable it here
853 */
854 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL &&
855 !dc_is_dp_signal(pix_clk_params->signal_type) &&
856 clock_source->ctx->dce_version <= DCE_VERSION_11_0)
857 disable_spread_spectrum(clk_src);
858
859 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
860 bp_pc_params.controller_id = pix_clk_params->controller_id;
861 bp_pc_params.pll_id = clock_source->id;
862 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
863 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
864 bp_pc_params.signal_type = pix_clk_params->signal_type;
865
866 bp_pc_params.reference_divider = pll_settings->reference_divider;
867 bp_pc_params.feedback_divider = pll_settings->feedback_divider;
868 bp_pc_params.fractional_feedback_divider =
869 pll_settings->fract_feedback_divider;
870 bp_pc_params.pixel_clock_post_divider =
871 pll_settings->pix_clk_post_divider;
872 bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =
873 pll_settings->use_external_clk;
874
875 switch (pix_clk_params->color_depth) {
876 case COLOR_DEPTH_101010:
877 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_30;
878 break;
879 case COLOR_DEPTH_121212:
880 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_36;
881 break;
882 case COLOR_DEPTH_161616:
883 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_48;
884 break;
885 default:
886 break;
887 }
888
889 if (clk_src->bios->funcs->set_pixel_clock(
890 clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
891 return false;
892 /* Enable SS
893 * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock),
894 * based on HW display PLL team, SS control settings should be programmed
895 * during PLL Reset, but they do not have effect
896 * until SS_EN is asserted.*/
897 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL
898 && !dc_is_dp_signal(pix_clk_params->signal_type)) {
899
900 if (pix_clk_params->flags.ENABLE_SS)
901 if (!enable_spread_spectrum(clk_src,
902 pix_clk_params->signal_type,
903 pll_settings))
904 return false;
905
906 /* Resync deep color DTO */
907 dce110_program_pixel_clk_resync(clk_src,
908 pix_clk_params->signal_type,
909 pix_clk_params->color_depth);
910 }
911
912 return true;
913 }
914
dce112_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)915 static bool dce112_program_pix_clk(
916 struct clock_source *clock_source,
917 struct pixel_clk_params *pix_clk_params,
918 struct pll_settings *pll_settings)
919 {
920 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
921 struct bp_pixel_clock_parameters bp_pc_params = {0};
922
923 #if defined(CONFIG_DRM_AMD_DC_DCN)
924 if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
925 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
926 unsigned dp_dto_ref_100hz = 7000000;
927 unsigned clock_100hz = pll_settings->actual_pix_clk_100hz;
928
929 /* Set DTO values: phase = target clock, modulo = reference clock */
930 REG_WRITE(PHASE[inst], clock_100hz);
931 REG_WRITE(MODULO[inst], dp_dto_ref_100hz);
932
933 /* Enable DTO */
934 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
935 return true;
936 }
937 #endif
938 /* First disable SS
939 * ATOMBIOS will enable by default SS on PLL for DP,
940 * do not disable it here
941 */
942 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL &&
943 !dc_is_dp_signal(pix_clk_params->signal_type) &&
944 clock_source->ctx->dce_version <= DCE_VERSION_11_0)
945 disable_spread_spectrum(clk_src);
946
947 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
948 bp_pc_params.controller_id = pix_clk_params->controller_id;
949 bp_pc_params.pll_id = clock_source->id;
950 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
951 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
952 bp_pc_params.signal_type = pix_clk_params->signal_type;
953
954 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
955 bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
956 pll_settings->use_external_clk;
957 bp_pc_params.flags.SET_XTALIN_REF_SRC =
958 !pll_settings->use_external_clk;
959 if (pix_clk_params->flags.SUPPORT_YCBCR420) {
960 bp_pc_params.flags.SUPPORT_YUV_420 = 1;
961 }
962 }
963 if (clk_src->bios->funcs->set_pixel_clock(
964 clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
965 return false;
966 /* Resync deep color DTO */
967 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO)
968 dce112_program_pixel_clk_resync(clk_src,
969 pix_clk_params->signal_type,
970 pix_clk_params->color_depth,
971 pix_clk_params->flags.SUPPORT_YCBCR420);
972
973 return true;
974 }
975
976
dce110_clock_source_power_down(struct clock_source * clk_src)977 static bool dce110_clock_source_power_down(
978 struct clock_source *clk_src)
979 {
980 struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src);
981 enum bp_result bp_result;
982 struct bp_pixel_clock_parameters bp_pixel_clock_params = {0};
983
984 if (clk_src->dp_clk_src)
985 return true;
986
987 /* If Pixel Clock is 0 it means Power Down Pll*/
988 bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED;
989 bp_pixel_clock_params.pll_id = clk_src->id;
990 bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;
991
992 /*Call ASICControl to process ATOMBIOS Exec table*/
993 bp_result = dce110_clk_src->bios->funcs->set_pixel_clock(
994 dce110_clk_src->bios,
995 &bp_pixel_clock_params);
996
997 return bp_result == BP_RESULT_OK;
998 }
999
get_pixel_clk_frequency_100hz(const struct clock_source * clock_source,unsigned int inst,unsigned int * pixel_clk_khz)1000 static bool get_pixel_clk_frequency_100hz(
1001 const struct clock_source *clock_source,
1002 unsigned int inst,
1003 unsigned int *pixel_clk_khz)
1004 {
1005 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1006 unsigned int clock_hz = 0;
1007 unsigned int modulo_hz = 0;
1008
1009 if (clock_source->id == CLOCK_SOURCE_ID_DP_DTO) {
1010 clock_hz = REG_READ(PHASE[inst]);
1011
1012 if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&
1013 clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {
1014 /* NOTE: In case VBLANK syncronization is enabled, MODULO may
1015 * not be programmed equal to DPREFCLK
1016 */
1017 modulo_hz = REG_READ(MODULO[inst]);
1018 if (modulo_hz)
1019 *pixel_clk_khz = div_u64((uint64_t)clock_hz*
1020 clock_source->ctx->dc->clk_mgr->dprefclk_khz*10,
1021 modulo_hz);
1022 else
1023 *pixel_clk_khz = 0;
1024 } else {
1025 /* NOTE: There is agreement with VBIOS here that MODULO is
1026 * programmed equal to DPREFCLK, in which case PHASE will be
1027 * equivalent to pixel clock.
1028 */
1029 *pixel_clk_khz = clock_hz / 100;
1030 }
1031 return true;
1032 }
1033
1034 return false;
1035 }
1036
1037 #if defined(CONFIG_DRM_AMD_DC_DCN)
1038 /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
1039 const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = {
1040 // /1.001 rates
1041 {25170, 25180, 25200, 1000, 1001}, //25.2MHz -> 25.17
1042 {59340, 59350, 59400, 1000, 1001}, //59.4Mhz -> 59.340
1043 {74170, 74180, 74250, 1000, 1001}, //74.25Mhz -> 74.1758
1044 {125870, 125880, 126000, 1000, 1001}, //126Mhz -> 125.87
1045 {148350, 148360, 148500, 1000, 1001}, //148.5Mhz -> 148.3516
1046 {167830, 167840, 168000, 1000, 1001}, //168Mhz -> 167.83
1047 {222520, 222530, 222750, 1000, 1001}, //222.75Mhz -> 222.527
1048 {257140, 257150, 257400, 1000, 1001}, //257.4Mhz -> 257.1429
1049 {296700, 296710, 297000, 1000, 1001}, //297Mhz -> 296.7033
1050 {342850, 342860, 343200, 1000, 1001}, //343.2Mhz -> 342.857
1051 {395600, 395610, 396000, 1000, 1001}, //396Mhz -> 395.6
1052 {409090, 409100, 409500, 1000, 1001}, //409.5Mhz -> 409.091
1053 {445050, 445060, 445500, 1000, 1001}, //445.5Mhz -> 445.055
1054 {467530, 467540, 468000, 1000, 1001}, //468Mhz -> 467.5325
1055 {519230, 519240, 519750, 1000, 1001}, //519.75Mhz -> 519.231
1056 {525970, 525980, 526500, 1000, 1001}, //526.5Mhz -> 525.974
1057 {545450, 545460, 546000, 1000, 1001}, //546Mhz -> 545.455
1058 {593400, 593410, 594000, 1000, 1001}, //594Mhz -> 593.4066
1059 {623370, 623380, 624000, 1000, 1001}, //624Mhz -> 623.377
1060 {692300, 692310, 693000, 1000, 1001}, //693Mhz -> 692.308
1061 {701290, 701300, 702000, 1000, 1001}, //702Mhz -> 701.2987
1062 {791200, 791210, 792000, 1000, 1001}, //792Mhz -> 791.209
1063 {890100, 890110, 891000, 1000, 1001}, //891Mhz -> 890.1099
1064 {1186810, 1186820, 1188000, 1000, 1001},//1188Mhz -> 1186.8131
1065
1066 // *1.001 rates
1067 {27020, 27030, 27000, 1001, 1000}, //27Mhz
1068 {54050, 54060, 54000, 1001, 1000}, //54Mhz
1069 {108100, 108110, 108000, 1001, 1000},//108Mhz
1070 };
1071
look_up_in_video_optimized_rate_tlb(unsigned int pixel_rate_khz)1072 const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb(
1073 unsigned int pixel_rate_khz)
1074 {
1075 int i;
1076
1077 for (i = 0; i < NUM_ELEMENTS(video_optimized_pixel_rates); i++) {
1078 const struct pixel_rate_range_table_entry *e = &video_optimized_pixel_rates[i];
1079
1080 if (e->range_min_khz <= pixel_rate_khz && pixel_rate_khz <= e->range_max_khz) {
1081 return e;
1082 }
1083 }
1084
1085 return NULL;
1086 }
1087 #endif
1088
dcn20_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)1089 static bool dcn20_program_pix_clk(
1090 struct clock_source *clock_source,
1091 struct pixel_clk_params *pix_clk_params,
1092 struct pll_settings *pll_settings)
1093 {
1094 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1095 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
1096
1097 dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings);
1098
1099 if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization &&
1100 clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) {
1101 /* NOTE: In case VBLANK syncronization is enabled,
1102 * we need to set modulo to default DPREFCLK first
1103 * dce112_program_pix_clk does not set default DPREFCLK
1104 */
1105 REG_WRITE(MODULO[inst],
1106 clock_source->ctx->dc->clk_mgr->dprefclk_khz*1000);
1107 }
1108 return true;
1109 }
1110
dcn20_override_dp_pix_clk(struct clock_source * clock_source,unsigned int inst,unsigned int pixel_clk,unsigned int ref_clk)1111 static bool dcn20_override_dp_pix_clk(
1112 struct clock_source *clock_source,
1113 unsigned int inst,
1114 unsigned int pixel_clk,
1115 unsigned int ref_clk)
1116 {
1117 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1118
1119 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 0);
1120 REG_WRITE(PHASE[inst], pixel_clk);
1121 REG_WRITE(MODULO[inst], ref_clk);
1122 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
1123 return true;
1124 }
1125
1126 static const struct clock_source_funcs dcn20_clk_src_funcs = {
1127 .cs_power_down = dce110_clock_source_power_down,
1128 .program_pix_clk = dcn20_program_pix_clk,
1129 .get_pix_clk_dividers = dce112_get_pix_clk_dividers,
1130 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz,
1131 .override_dp_pix_clk = dcn20_override_dp_pix_clk
1132 };
1133
1134 #if defined(CONFIG_DRM_AMD_DC_DCN)
dcn3_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)1135 static bool dcn3_program_pix_clk(
1136 struct clock_source *clock_source,
1137 struct pixel_clk_params *pix_clk_params,
1138 struct pll_settings *pll_settings)
1139 {
1140 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
1141 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
1142 unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz;
1143 const struct pixel_rate_range_table_entry *e =
1144 look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10);
1145
1146 // For these signal types Driver to program DP_DTO without calling VBIOS Command table
1147 if (dc_is_dp_signal(pix_clk_params->signal_type)) {
1148 if (e) {
1149 /* Set DTO values: phase = target clock, modulo = reference clock*/
1150 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor);
1151 REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor);
1152 } else {
1153 /* Set DTO values: phase = target clock, modulo = reference clock*/
1154 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100);
1155 REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000);
1156 }
1157 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
1158 } else
1159 // For other signal types(HDMI_TYPE_A, DVI) Driver still to call VBIOS Command table
1160 dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings);
1161
1162 return true;
1163 }
1164
dcn3_get_pix_clk_dividers(struct clock_source * cs,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)1165 static uint32_t dcn3_get_pix_clk_dividers(
1166 struct clock_source *cs,
1167 struct pixel_clk_params *pix_clk_params,
1168 struct pll_settings *pll_settings)
1169 {
1170 unsigned long long actual_pix_clk_100Hz = pix_clk_params->requested_pix_clk_100hz;
1171 struct dce110_clk_src *clk_src;
1172
1173 clk_src = TO_DCE110_CLK_SRC(cs);
1174 DC_LOGGER_INIT();
1175
1176 if (pix_clk_params == NULL || pll_settings == NULL
1177 || pix_clk_params->requested_pix_clk_100hz == 0) {
1178 DC_LOG_ERROR(
1179 "%s: Invalid parameters!!\n", __func__);
1180 return -1;
1181 }
1182
1183 memset(pll_settings, 0, sizeof(*pll_settings));
1184 /* Adjust for HDMI Type A deep color */
1185 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
1186 switch (pix_clk_params->color_depth) {
1187 case COLOR_DEPTH_101010:
1188 actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 5) >> 2;
1189 break;
1190 case COLOR_DEPTH_121212:
1191 actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 6) >> 2;
1192 break;
1193 case COLOR_DEPTH_161616:
1194 actual_pix_clk_100Hz = actual_pix_clk_100Hz * 2;
1195 break;
1196 default:
1197 break;
1198 }
1199 }
1200 pll_settings->actual_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1201 pll_settings->adjusted_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1202 pll_settings->calculated_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz;
1203
1204 return 0;
1205 }
1206
1207 static const struct clock_source_funcs dcn3_clk_src_funcs = {
1208 .cs_power_down = dce110_clock_source_power_down,
1209 .program_pix_clk = dcn3_program_pix_clk,
1210 .get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
1211 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1212 };
1213 #endif
1214 /*****************************************/
1215 /* Constructor */
1216 /*****************************************/
1217
1218 static const struct clock_source_funcs dce112_clk_src_funcs = {
1219 .cs_power_down = dce110_clock_source_power_down,
1220 .program_pix_clk = dce112_program_pix_clk,
1221 .get_pix_clk_dividers = dce112_get_pix_clk_dividers,
1222 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1223 };
1224 static const struct clock_source_funcs dce110_clk_src_funcs = {
1225 .cs_power_down = dce110_clock_source_power_down,
1226 .program_pix_clk = dce110_program_pix_clk,
1227 .get_pix_clk_dividers = dce110_get_pix_clk_dividers,
1228 .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
1229 };
1230
1231
get_ss_info_from_atombios(struct dce110_clk_src * clk_src,enum as_signal_type as_signal,struct spread_spectrum_data * spread_spectrum_data[],uint32_t * ss_entries_num)1232 static void get_ss_info_from_atombios(
1233 struct dce110_clk_src *clk_src,
1234 enum as_signal_type as_signal,
1235 struct spread_spectrum_data *spread_spectrum_data[],
1236 uint32_t *ss_entries_num)
1237 {
1238 enum bp_result bp_result = BP_RESULT_FAILURE;
1239 struct spread_spectrum_info *ss_info;
1240 struct spread_spectrum_data *ss_data;
1241 struct spread_spectrum_info *ss_info_cur;
1242 struct spread_spectrum_data *ss_data_cur;
1243 uint32_t i;
1244 DC_LOGGER_INIT();
1245 if (ss_entries_num == NULL) {
1246 DC_LOG_SYNC(
1247 "Invalid entry !!!\n");
1248 return;
1249 }
1250 if (spread_spectrum_data == NULL) {
1251 DC_LOG_SYNC(
1252 "Invalid array pointer!!!\n");
1253 return;
1254 }
1255
1256 spread_spectrum_data[0] = NULL;
1257 *ss_entries_num = 0;
1258
1259 *ss_entries_num = clk_src->bios->funcs->get_ss_entry_number(
1260 clk_src->bios,
1261 as_signal);
1262
1263 if (*ss_entries_num == 0)
1264 return;
1265
1266 ss_info = kcalloc(*ss_entries_num,
1267 sizeof(struct spread_spectrum_info),
1268 GFP_KERNEL);
1269 ss_info_cur = ss_info;
1270 if (ss_info == NULL)
1271 return;
1272
1273 ss_data = kcalloc(*ss_entries_num,
1274 sizeof(struct spread_spectrum_data),
1275 GFP_KERNEL);
1276 if (ss_data == NULL)
1277 goto out_free_info;
1278
1279 for (i = 0, ss_info_cur = ss_info;
1280 i < (*ss_entries_num);
1281 ++i, ++ss_info_cur) {
1282
1283 bp_result = clk_src->bios->funcs->get_spread_spectrum_info(
1284 clk_src->bios,
1285 as_signal,
1286 i,
1287 ss_info_cur);
1288
1289 if (bp_result != BP_RESULT_OK)
1290 goto out_free_data;
1291 }
1292
1293 for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data;
1294 i < (*ss_entries_num);
1295 ++i, ++ss_info_cur, ++ss_data_cur) {
1296
1297 if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) {
1298 DC_LOG_SYNC(
1299 "Invalid ATOMBIOS SS Table!!!\n");
1300 goto out_free_data;
1301 }
1302
1303 /* for HDMI check SS percentage,
1304 * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/
1305 if (as_signal == AS_SIGNAL_TYPE_HDMI
1306 && ss_info_cur->spread_spectrum_percentage > 6){
1307 /* invalid input, do nothing */
1308 DC_LOG_SYNC(
1309 "Invalid SS percentage ");
1310 DC_LOG_SYNC(
1311 "for HDMI in ATOMBIOS info Table!!!\n");
1312 continue;
1313 }
1314 if (ss_info_cur->spread_percentage_divider == 1000) {
1315 /* Keep previous precision from ATOMBIOS for these
1316 * in case new precision set by ATOMBIOS for these
1317 * (otherwise all code in DCE specific classes
1318 * for all previous ASICs would need
1319 * to be updated for SS calculations,
1320 * Audio SS compensation and DP DTO SS compensation
1321 * which assumes fixed SS percentage Divider = 100)*/
1322 ss_info_cur->spread_spectrum_percentage /= 10;
1323 ss_info_cur->spread_percentage_divider = 100;
1324 }
1325
1326 ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range;
1327 ss_data_cur->percentage =
1328 ss_info_cur->spread_spectrum_percentage;
1329 ss_data_cur->percentage_divider =
1330 ss_info_cur->spread_percentage_divider;
1331 ss_data_cur->modulation_freq_hz =
1332 ss_info_cur->spread_spectrum_range;
1333
1334 if (ss_info_cur->type.CENTER_MODE)
1335 ss_data_cur->flags.CENTER_SPREAD = 1;
1336
1337 if (ss_info_cur->type.EXTERNAL)
1338 ss_data_cur->flags.EXTERNAL_SS = 1;
1339
1340 }
1341
1342 *spread_spectrum_data = ss_data;
1343 kfree(ss_info);
1344 return;
1345
1346 out_free_data:
1347 kfree(ss_data);
1348 *ss_entries_num = 0;
1349 out_free_info:
1350 kfree(ss_info);
1351 }
1352
ss_info_from_atombios_create(struct dce110_clk_src * clk_src)1353 static void ss_info_from_atombios_create(
1354 struct dce110_clk_src *clk_src)
1355 {
1356 get_ss_info_from_atombios(
1357 clk_src,
1358 AS_SIGNAL_TYPE_DISPLAY_PORT,
1359 &clk_src->dp_ss_params,
1360 &clk_src->dp_ss_params_cnt);
1361 get_ss_info_from_atombios(
1362 clk_src,
1363 AS_SIGNAL_TYPE_HDMI,
1364 &clk_src->hdmi_ss_params,
1365 &clk_src->hdmi_ss_params_cnt);
1366 get_ss_info_from_atombios(
1367 clk_src,
1368 AS_SIGNAL_TYPE_DVI,
1369 &clk_src->dvi_ss_params,
1370 &clk_src->dvi_ss_params_cnt);
1371 get_ss_info_from_atombios(
1372 clk_src,
1373 AS_SIGNAL_TYPE_LVDS,
1374 &clk_src->lvds_ss_params,
1375 &clk_src->lvds_ss_params_cnt);
1376 }
1377
calc_pll_max_vco_construct(struct calc_pll_clock_source * calc_pll_cs,struct calc_pll_clock_source_init_data * init_data)1378 static bool calc_pll_max_vco_construct(
1379 struct calc_pll_clock_source *calc_pll_cs,
1380 struct calc_pll_clock_source_init_data *init_data)
1381 {
1382 uint32_t i;
1383 struct dc_firmware_info *fw_info;
1384 if (calc_pll_cs == NULL ||
1385 init_data == NULL ||
1386 init_data->bp == NULL)
1387 return false;
1388
1389 if (!init_data->bp->fw_info_valid)
1390 return false;
1391
1392 fw_info = &init_data->bp->fw_info;
1393 calc_pll_cs->ctx = init_data->ctx;
1394 calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency;
1395 calc_pll_cs->min_vco_khz =
1396 fw_info->pll_info.min_output_pxl_clk_pll_frequency;
1397 calc_pll_cs->max_vco_khz =
1398 fw_info->pll_info.max_output_pxl_clk_pll_frequency;
1399
1400 if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0)
1401 calc_pll_cs->max_pll_input_freq_khz =
1402 init_data->max_override_input_pxl_clk_pll_freq_khz;
1403 else
1404 calc_pll_cs->max_pll_input_freq_khz =
1405 fw_info->pll_info.max_input_pxl_clk_pll_frequency;
1406
1407 if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0)
1408 calc_pll_cs->min_pll_input_freq_khz =
1409 init_data->min_override_input_pxl_clk_pll_freq_khz;
1410 else
1411 calc_pll_cs->min_pll_input_freq_khz =
1412 fw_info->pll_info.min_input_pxl_clk_pll_frequency;
1413
1414 calc_pll_cs->min_pix_clock_pll_post_divider =
1415 init_data->min_pix_clk_pll_post_divider;
1416 calc_pll_cs->max_pix_clock_pll_post_divider =
1417 init_data->max_pix_clk_pll_post_divider;
1418 calc_pll_cs->min_pll_ref_divider =
1419 init_data->min_pll_ref_divider;
1420 calc_pll_cs->max_pll_ref_divider =
1421 init_data->max_pll_ref_divider;
1422
1423 if (init_data->num_fract_fb_divider_decimal_point == 0 ||
1424 init_data->num_fract_fb_divider_decimal_point_precision >
1425 init_data->num_fract_fb_divider_decimal_point) {
1426 DC_LOG_ERROR(
1427 "The dec point num or precision is incorrect!");
1428 return false;
1429 }
1430 if (init_data->num_fract_fb_divider_decimal_point_precision == 0) {
1431 DC_LOG_ERROR(
1432 "Incorrect fract feedback divider precision num!");
1433 return false;
1434 }
1435
1436 calc_pll_cs->fract_fb_divider_decimal_points_num =
1437 init_data->num_fract_fb_divider_decimal_point;
1438 calc_pll_cs->fract_fb_divider_precision =
1439 init_data->num_fract_fb_divider_decimal_point_precision;
1440 calc_pll_cs->fract_fb_divider_factor = 1;
1441 for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i)
1442 calc_pll_cs->fract_fb_divider_factor *= 10;
1443
1444 calc_pll_cs->fract_fb_divider_precision_factor = 1;
1445 for (
1446 i = 0;
1447 i < (calc_pll_cs->fract_fb_divider_decimal_points_num -
1448 calc_pll_cs->fract_fb_divider_precision);
1449 ++i)
1450 calc_pll_cs->fract_fb_divider_precision_factor *= 10;
1451
1452 return true;
1453 }
1454
dce110_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1455 bool dce110_clk_src_construct(
1456 struct dce110_clk_src *clk_src,
1457 struct dc_context *ctx,
1458 struct dc_bios *bios,
1459 enum clock_source_id id,
1460 const struct dce110_clk_src_regs *regs,
1461 const struct dce110_clk_src_shift *cs_shift,
1462 const struct dce110_clk_src_mask *cs_mask)
1463 {
1464 struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi;
1465 struct calc_pll_clock_source_init_data calc_pll_cs_init_data;
1466
1467 clk_src->base.ctx = ctx;
1468 clk_src->bios = bios;
1469 clk_src->base.id = id;
1470 clk_src->base.funcs = &dce110_clk_src_funcs;
1471
1472 clk_src->regs = regs;
1473 clk_src->cs_shift = cs_shift;
1474 clk_src->cs_mask = cs_mask;
1475
1476 if (!clk_src->bios->fw_info_valid) {
1477 ASSERT_CRITICAL(false);
1478 goto unexpected_failure;
1479 }
1480
1481 clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
1482
1483 /* structure normally used with PLL ranges from ATOMBIOS; DS on by default */
1484 calc_pll_cs_init_data.bp = bios;
1485 calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 1;
1486 calc_pll_cs_init_data.max_pix_clk_pll_post_divider =
1487 clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
1488 calc_pll_cs_init_data.min_pll_ref_divider = 1;
1489 calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV;
1490 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1491 calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz = 0;
1492 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1493 calc_pll_cs_init_data.max_override_input_pxl_clk_pll_freq_khz = 0;
1494 /*numberOfFractFBDividerDecimalPoints*/
1495 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point =
1496 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1497 /*number of decimal point to round off for fractional feedback divider value*/
1498 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point_precision =
1499 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1500 calc_pll_cs_init_data.ctx = ctx;
1501
1502 /*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */
1503 calc_pll_cs_init_data_hdmi.bp = bios;
1504 calc_pll_cs_init_data_hdmi.min_pix_clk_pll_post_divider = 1;
1505 calc_pll_cs_init_data_hdmi.max_pix_clk_pll_post_divider =
1506 clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
1507 calc_pll_cs_init_data_hdmi.min_pll_ref_divider = 1;
1508 calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV;
1509 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1510 calc_pll_cs_init_data_hdmi.min_override_input_pxl_clk_pll_freq_khz = 13500;
1511 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1512 calc_pll_cs_init_data_hdmi.max_override_input_pxl_clk_pll_freq_khz = 27000;
1513 /*numberOfFractFBDividerDecimalPoints*/
1514 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point =
1515 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1516 /*number of decimal point to round off for fractional feedback divider value*/
1517 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point_precision =
1518 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1519 calc_pll_cs_init_data_hdmi.ctx = ctx;
1520
1521 clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency;
1522
1523 if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL)
1524 return true;
1525
1526 /* PLL only from here on */
1527 ss_info_from_atombios_create(clk_src);
1528
1529 if (!calc_pll_max_vco_construct(
1530 &clk_src->calc_pll,
1531 &calc_pll_cs_init_data)) {
1532 ASSERT_CRITICAL(false);
1533 goto unexpected_failure;
1534 }
1535
1536
1537 calc_pll_cs_init_data_hdmi.
1538 min_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz/2;
1539 calc_pll_cs_init_data_hdmi.
1540 max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz;
1541
1542
1543 if (!calc_pll_max_vco_construct(
1544 &clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) {
1545 ASSERT_CRITICAL(false);
1546 goto unexpected_failure;
1547 }
1548
1549 return true;
1550
1551 unexpected_failure:
1552 return false;
1553 }
1554
dce112_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1555 bool dce112_clk_src_construct(
1556 struct dce110_clk_src *clk_src,
1557 struct dc_context *ctx,
1558 struct dc_bios *bios,
1559 enum clock_source_id id,
1560 const struct dce110_clk_src_regs *regs,
1561 const struct dce110_clk_src_shift *cs_shift,
1562 const struct dce110_clk_src_mask *cs_mask)
1563 {
1564 clk_src->base.ctx = ctx;
1565 clk_src->bios = bios;
1566 clk_src->base.id = id;
1567 clk_src->base.funcs = &dce112_clk_src_funcs;
1568
1569 clk_src->regs = regs;
1570 clk_src->cs_shift = cs_shift;
1571 clk_src->cs_mask = cs_mask;
1572
1573 if (!clk_src->bios->fw_info_valid) {
1574 ASSERT_CRITICAL(false);
1575 return false;
1576 }
1577
1578 clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp;
1579
1580 return true;
1581 }
1582
dcn20_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1583 bool dcn20_clk_src_construct(
1584 struct dce110_clk_src *clk_src,
1585 struct dc_context *ctx,
1586 struct dc_bios *bios,
1587 enum clock_source_id id,
1588 const struct dce110_clk_src_regs *regs,
1589 const struct dce110_clk_src_shift *cs_shift,
1590 const struct dce110_clk_src_mask *cs_mask)
1591 {
1592 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1593
1594 clk_src->base.funcs = &dcn20_clk_src_funcs;
1595
1596 return ret;
1597 }
1598
1599 #if defined(CONFIG_DRM_AMD_DC_DCN)
dcn3_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1600 bool dcn3_clk_src_construct(
1601 struct dce110_clk_src *clk_src,
1602 struct dc_context *ctx,
1603 struct dc_bios *bios,
1604 enum clock_source_id id,
1605 const struct dce110_clk_src_regs *regs,
1606 const struct dce110_clk_src_shift *cs_shift,
1607 const struct dce110_clk_src_mask *cs_mask)
1608 {
1609 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1610
1611 clk_src->base.funcs = &dcn3_clk_src_funcs;
1612
1613 return ret;
1614 }
1615 #endif
1616
1617 #if defined(CONFIG_DRM_AMD_DC_DCN)
dcn301_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1618 bool dcn301_clk_src_construct(
1619 struct dce110_clk_src *clk_src,
1620 struct dc_context *ctx,
1621 struct dc_bios *bios,
1622 enum clock_source_id id,
1623 const struct dce110_clk_src_regs *regs,
1624 const struct dce110_clk_src_shift *cs_shift,
1625 const struct dce110_clk_src_mask *cs_mask)
1626 {
1627 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
1628
1629 clk_src->base.funcs = &dcn3_clk_src_funcs;
1630
1631 return ret;
1632 }
1633 #endif
1634