1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27
28 #include "dccg.h"
29 #include "clk_mgr_internal.h"
30
31 // For dce12_get_dp_ref_freq_khz
32 #include "dce100/dce_clk_mgr.h"
33
34 // For dcn20_update_clocks_update_dpp_dto
35 #include "dcn20/dcn20_clk_mgr.h"
36
37
38
39 #include "dcn31_clk_mgr.h"
40
41 #include "reg_helper.h"
42 #include "core_types.h"
43 #include "dcn31_smu.h"
44 #include "dm_helpers.h"
45
46 /* TODO: remove this include once we ported over remaining clk mgr functions*/
47 #include "dcn30/dcn30_clk_mgr.h"
48
49 #include "dc_dmub_srv.h"
50
51 #include "yellow_carp_offset.h"
52
53 #define regCLK1_CLK_PLL_REQ 0x0237
54 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0
55
56 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
57 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
58 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
59 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
60 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
61 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
62
63 #define REG(reg_name) \
64 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
65
66 #define TO_CLK_MGR_DCN31(clk_mgr)\
67 container_of(clk_mgr, struct clk_mgr_dcn31, base)
68
dcn31_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context)69 int dcn31_get_active_display_cnt_wa(
70 struct dc *dc,
71 struct dc_state *context)
72 {
73 int i, display_count;
74 bool tmds_present = false;
75
76 display_count = 0;
77 for (i = 0; i < context->stream_count; i++) {
78 const struct dc_stream_state *stream = context->streams[i];
79
80 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
81 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
82 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
83 tmds_present = true;
84
85 /* Checking stream / link detection ensuring that PHY is active*/
86 if (dc_is_dp_signal(stream->signal) && !stream->dpms_off)
87 display_count++;
88
89 }
90
91 for (i = 0; i < dc->link_count; i++) {
92 const struct dc_link *link = dc->links[i];
93
94 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
95 if (link->link_enc->funcs->is_dig_enabled &&
96 link->link_enc->funcs->is_dig_enabled(link->link_enc))
97 display_count++;
98 }
99
100 /* WA for hang on HDMI after display off back back on*/
101 if (display_count == 0 && tmds_present)
102 display_count = 1;
103
104 return display_count;
105 }
106
dcn31_disable_otg_wa(struct clk_mgr * clk_mgr_base,bool disable)107 static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
108 {
109 struct dc *dc = clk_mgr_base->ctx->dc;
110 int i;
111
112 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
113 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
114
115 if (pipe->top_pipe || pipe->prev_odm_pipe)
116 continue;
117 if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
118 if (disable)
119 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
120 else
121 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
122 }
123 }
124 }
125
dcn31_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)126 static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
127 struct dc_state *context,
128 bool safe_to_lower)
129 {
130 union dmub_rb_cmd cmd;
131 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
132 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
133 struct dc *dc = clk_mgr_base->ctx->dc;
134 int display_count;
135 bool update_dppclk = false;
136 bool update_dispclk = false;
137 bool dpp_clock_lowered = false;
138
139 if (dc->work_arounds.skip_clock_update)
140 return;
141
142 /*
143 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
144 * also if safe to lower is false, we just go in the higher state
145 */
146 if (safe_to_lower) {
147 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_ALLOW &&
148 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
149 dcn31_smu_set_Z9_support(clk_mgr, true);
150 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
151 }
152
153 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
154 dcn31_smu_set_dtbclk(clk_mgr, false);
155 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
156 }
157 /* check that we're not already in lower */
158 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
159 display_count = dcn31_get_active_display_cnt_wa(dc, context);
160 /* if we can go lower, go lower */
161 if (display_count == 0) {
162 union display_idle_optimization_u idle_info = { 0 };
163 idle_info.idle_info.df_request_disabled = 1;
164 idle_info.idle_info.phy_ref_clk_off = 1;
165 idle_info.idle_info.s0i2_rdy = 1;
166 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
167 /* update power state */
168 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
169 }
170 }
171 } else {
172 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&
173 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
174 dcn31_smu_set_Z9_support(clk_mgr, false);
175 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
176 }
177
178 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
179 dcn31_smu_set_dtbclk(clk_mgr, true);
180 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
181 }
182
183 /* check that we're not already in D0 */
184 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
185 union display_idle_optimization_u idle_info = { 0 };
186 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
187 /* update power state */
188 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
189 }
190 }
191
192 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
193 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
194 dcn31_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
195 }
196
197 if (should_set_clock(safe_to_lower,
198 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
199 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
200 dcn31_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
201 }
202
203 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
204 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
205 if (new_clocks->dppclk_khz < 100000)
206 new_clocks->dppclk_khz = 100000;
207 }
208
209 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
210 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
211 dpp_clock_lowered = true;
212 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
213 update_dppclk = true;
214 }
215
216 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
217 dcn31_disable_otg_wa(clk_mgr_base, true);
218
219 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
220 dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
221 dcn31_disable_otg_wa(clk_mgr_base, false);
222
223 update_dispclk = true;
224 }
225
226 /* TODO: add back DTO programming when DPPCLK restore is fixed in FSDL*/
227 if (dpp_clock_lowered) {
228 // increase per DPP DTO before lowering global dppclk
229 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
230 } else {
231 // increase global DPPCLK before lowering per DPP DTO
232 if (update_dppclk || update_dispclk)
233 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
234 }
235
236 // notify DMCUB of latest clocks
237 memset(&cmd, 0, sizeof(cmd));
238 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
239 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
240 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
241 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
242 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
243 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
244 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
245
246 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
247 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
248 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
249 }
250
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)251 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
252 {
253 /* get FbMult value */
254 struct fixed31_32 pll_req;
255 unsigned int fbmult_frac_val = 0;
256 unsigned int fbmult_int_val = 0;
257
258 /*
259 * Register value of fbmult is in 8.16 format, we are converting to 31.32
260 * to leverage the fix point operations available in driver
261 */
262
263 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
264 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
265
266 pll_req = dc_fixpt_from_int(fbmult_int_val);
267
268 /*
269 * since fractional part is only 16 bit in register definition but is 32 bit
270 * in our fix point definiton, need to shift left by 16 to obtain correct value
271 */
272 pll_req.value |= fbmult_frac_val << 16;
273
274 /* multiply by REFCLK period */
275 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
276
277 /* integer part is now VCO frequency in kHz */
278 return dc_fixpt_floor(pll_req);
279 }
280
dcn31_enable_pme_wa(struct clk_mgr * clk_mgr_base)281 static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base)
282 {
283 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
284
285 dcn31_smu_enable_pme_wa(clk_mgr);
286 }
287
dcn31_init_clocks(struct clk_mgr * clk_mgr)288 static void dcn31_init_clocks(struct clk_mgr *clk_mgr)
289 {
290 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
291 // Assumption is that boot state always supports pstate
292 clk_mgr->clks.p_state_change_support = true;
293 clk_mgr->clks.prev_p_state_change_support = true;
294 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
295 clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
296 }
297
dcn31_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)298 static bool dcn31_are_clock_states_equal(struct dc_clocks *a,
299 struct dc_clocks *b)
300 {
301 if (a->dispclk_khz != b->dispclk_khz)
302 return false;
303 else if (a->dppclk_khz != b->dppclk_khz)
304 return false;
305 else if (a->dcfclk_khz != b->dcfclk_khz)
306 return false;
307 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
308 return false;
309 else if (a->zstate_support != b->zstate_support)
310 return false;
311 else if (a->dtbclk_en != b->dtbclk_en)
312 return false;
313
314 return true;
315 }
316
dcn31_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)317 static void dcn31_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
318 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
319 {
320 return;
321 }
322
323 static struct clk_bw_params dcn31_bw_params = {
324 .vram_type = Ddr4MemType,
325 .num_channels = 1,
326 .clk_table = {
327 .num_entries = 4,
328 },
329
330 };
331
332 static struct wm_table ddr5_wm_table = {
333 .entries = {
334 {
335 .wm_inst = WM_A,
336 .wm_type = WM_TYPE_PSTATE_CHG,
337 .pstate_latency_us = 11.72,
338 .sr_exit_time_us = 9,
339 .sr_enter_plus_exit_time_us = 11,
340 .valid = true,
341 },
342 {
343 .wm_inst = WM_B,
344 .wm_type = WM_TYPE_PSTATE_CHG,
345 .pstate_latency_us = 11.72,
346 .sr_exit_time_us = 9,
347 .sr_enter_plus_exit_time_us = 11,
348 .valid = true,
349 },
350 {
351 .wm_inst = WM_C,
352 .wm_type = WM_TYPE_PSTATE_CHG,
353 .pstate_latency_us = 11.72,
354 .sr_exit_time_us = 9,
355 .sr_enter_plus_exit_time_us = 11,
356 .valid = true,
357 },
358 {
359 .wm_inst = WM_D,
360 .wm_type = WM_TYPE_PSTATE_CHG,
361 .pstate_latency_us = 11.72,
362 .sr_exit_time_us = 9,
363 .sr_enter_plus_exit_time_us = 11,
364 .valid = true,
365 },
366 }
367 };
368
369 static struct wm_table lpddr5_wm_table = {
370 .entries = {
371 {
372 .wm_inst = WM_A,
373 .wm_type = WM_TYPE_PSTATE_CHG,
374 .pstate_latency_us = 11.65333,
375 .sr_exit_time_us = 11.5,
376 .sr_enter_plus_exit_time_us = 14.5,
377 .valid = true,
378 },
379 {
380 .wm_inst = WM_B,
381 .wm_type = WM_TYPE_PSTATE_CHG,
382 .pstate_latency_us = 11.65333,
383 .sr_exit_time_us = 11.5,
384 .sr_enter_plus_exit_time_us = 14.5,
385 .valid = true,
386 },
387 {
388 .wm_inst = WM_C,
389 .wm_type = WM_TYPE_PSTATE_CHG,
390 .pstate_latency_us = 11.65333,
391 .sr_exit_time_us = 11.5,
392 .sr_enter_plus_exit_time_us = 14.5,
393 .valid = true,
394 },
395 {
396 .wm_inst = WM_D,
397 .wm_type = WM_TYPE_PSTATE_CHG,
398 .pstate_latency_us = 11.65333,
399 .sr_exit_time_us = 11.5,
400 .sr_enter_plus_exit_time_us = 14.5,
401 .valid = true,
402 },
403 }
404 };
405
406 static DpmClocks_t dummy_clocks;
407
408 static struct dcn31_watermarks dummy_wms = { 0 };
409
dcn31_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn31_watermarks * table)410 static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table)
411 {
412 int i, num_valid_sets;
413
414 num_valid_sets = 0;
415
416 for (i = 0; i < WM_SET_COUNT; i++) {
417 /* skip empty entries, the smu array has no holes*/
418 if (!bw_params->wm_table.entries[i].valid)
419 continue;
420
421 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
422 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
423 /* We will not select WM based on fclk, so leave it as unconstrained */
424 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
425 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
426
427 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
428 if (i == 0)
429 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
430 else {
431 /* add 1 to make it non-overlapping with next lvl */
432 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
433 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
434 }
435 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
436 bw_params->clk_table.entries[i].dcfclk_mhz;
437
438 } else {
439 /* unconstrained for memory retraining */
440 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
441 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
442
443 /* Modify previous watermark range to cover up to max */
444 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
445 }
446 num_valid_sets++;
447 }
448
449 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
450
451 /* modify the min and max to make sure we cover the whole range*/
452 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
453 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
454 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
455 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
456
457 /* This is for writeback only, does not matter currently as no writeback support*/
458 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
459 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
460 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
461 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
462 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
463 }
464
dcn31_notify_wm_ranges(struct clk_mgr * clk_mgr_base)465 static void dcn31_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
466 {
467 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
468 struct clk_mgr_dcn31 *clk_mgr_dcn31 = TO_CLK_MGR_DCN31(clk_mgr);
469 struct dcn31_watermarks *table = clk_mgr_dcn31->smu_wm_set.wm_set;
470
471 if (!clk_mgr->smu_ver)
472 return;
473
474 if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0)
475 return;
476
477 memset(table, 0, sizeof(*table));
478
479 dcn31_build_watermark_ranges(clk_mgr_base->bw_params, table);
480
481 dcn31_smu_set_dram_addr_high(clk_mgr,
482 clk_mgr_dcn31->smu_wm_set.mc_address.high_part);
483 dcn31_smu_set_dram_addr_low(clk_mgr,
484 clk_mgr_dcn31->smu_wm_set.mc_address.low_part);
485 dcn31_smu_transfer_wm_table_dram_2_smu(clk_mgr);
486 }
487
dcn31_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn31_smu_dpm_clks * smu_dpm_clks)488 static void dcn31_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
489 struct dcn31_smu_dpm_clks *smu_dpm_clks)
490 {
491 DpmClocks_t *table = smu_dpm_clks->dpm_clks;
492
493 if (!clk_mgr->smu_ver)
494 return;
495
496 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
497 return;
498
499 memset(table, 0, sizeof(*table));
500
501 dcn31_smu_set_dram_addr_high(clk_mgr,
502 smu_dpm_clks->mc_address.high_part);
503 dcn31_smu_set_dram_addr_low(clk_mgr,
504 smu_dpm_clks->mc_address.low_part);
505 dcn31_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
506 }
507
find_max_clk_value(const uint32_t clocks[],uint32_t num_clocks)508 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
509 {
510 uint32_t max = 0;
511 int i;
512
513 for (i = 0; i < num_clocks; ++i) {
514 if (clocks[i] > max)
515 max = clocks[i];
516 }
517
518 return max;
519 }
520
find_clk_for_voltage(const DpmClocks_t * clock_table,const uint32_t clocks[],unsigned int voltage)521 static unsigned int find_clk_for_voltage(
522 const DpmClocks_t *clock_table,
523 const uint32_t clocks[],
524 unsigned int voltage)
525 {
526 int i;
527 int max_voltage = 0;
528 int clock = 0;
529
530 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
531 if (clock_table->SocVoltage[i] == voltage) {
532 return clocks[i];
533 } else if (clock_table->SocVoltage[i] >= max_voltage &&
534 clock_table->SocVoltage[i] < voltage) {
535 max_voltage = clock_table->SocVoltage[i];
536 clock = clocks[i];
537 }
538 }
539
540 ASSERT(clock);
541 return clock;
542 }
543
dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,const DpmClocks_t * clock_table)544 void dcn31_clk_mgr_helper_populate_bw_params(
545 struct clk_mgr_internal *clk_mgr,
546 struct integrated_info *bios_info,
547 const DpmClocks_t *clock_table)
548 {
549 int i, j;
550 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
551 uint32_t max_dispclk = 0, max_dppclk = 0;
552
553 j = -1;
554
555 ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL);
556
557 /* Find lowest DPM, FCLK is filled in reverse order*/
558
559 for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
560 if (clock_table->DfPstateTable[i].FClk != 0) {
561 j = i;
562 break;
563 }
564 }
565
566 if (j == -1) {
567 /* clock table is all 0s, just use our own hardcode */
568 ASSERT(0);
569 return;
570 }
571
572 bw_params->clk_table.num_entries = j + 1;
573
574 /* dispclk and dppclk can be max at any voltage, same number of levels for both */
575 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
576 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
577 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
578 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
579 } else {
580 ASSERT(0);
581 }
582
583 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
584 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
585 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
586 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
587 switch (clock_table->DfPstateTable[j].WckRatio) {
588 case WCK_RATIO_1_2:
589 bw_params->clk_table.entries[i].wck_ratio = 2;
590 break;
591 case WCK_RATIO_1_4:
592 bw_params->clk_table.entries[i].wck_ratio = 4;
593 break;
594 default:
595 bw_params->clk_table.entries[i].wck_ratio = 1;
596 }
597 bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
598 bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
599 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
600 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
601 }
602
603 bw_params->vram_type = bios_info->memory_type;
604 bw_params->num_channels = bios_info->ma_channel_number;
605
606 for (i = 0; i < WM_SET_COUNT; i++) {
607 bw_params->wm_table.entries[i].wm_inst = i;
608
609 if (i >= bw_params->clk_table.num_entries) {
610 bw_params->wm_table.entries[i].valid = false;
611 continue;
612 }
613
614 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
615 bw_params->wm_table.entries[i].valid = true;
616 }
617 }
618
619 static struct clk_mgr_funcs dcn31_funcs = {
620 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
621 .update_clocks = dcn31_update_clocks,
622 .init_clocks = dcn31_init_clocks,
623 .enable_pme_wa = dcn31_enable_pme_wa,
624 .are_clock_states_equal = dcn31_are_clock_states_equal,
625 .notify_wm_ranges = dcn31_notify_wm_ranges
626 };
627 extern struct clk_mgr_funcs dcn3_fpga_funcs;
628
dcn31_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn31 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)629 void dcn31_clk_mgr_construct(
630 struct dc_context *ctx,
631 struct clk_mgr_dcn31 *clk_mgr,
632 struct pp_smu_funcs *pp_smu,
633 struct dccg *dccg)
634 {
635 struct dcn31_smu_dpm_clks smu_dpm_clks = { 0 };
636
637 clk_mgr->base.base.ctx = ctx;
638 clk_mgr->base.base.funcs = &dcn31_funcs;
639
640 clk_mgr->base.pp_smu = pp_smu;
641
642 clk_mgr->base.dccg = dccg;
643 clk_mgr->base.dfs_bypass_disp_clk = 0;
644
645 clk_mgr->base.dprefclk_ss_percentage = 0;
646 clk_mgr->base.dprefclk_ss_divider = 1000;
647 clk_mgr->base.ss_on_dprefclk = false;
648 clk_mgr->base.dfs_ref_freq_khz = 48000;
649
650 clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem(
651 clk_mgr->base.base.ctx,
652 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
653 sizeof(struct dcn31_watermarks),
654 &clk_mgr->smu_wm_set.mc_address.quad_part);
655
656 if (clk_mgr->smu_wm_set.wm_set == 0) {
657 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
658 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
659 }
660 ASSERT(clk_mgr->smu_wm_set.wm_set);
661
662 smu_dpm_clks.dpm_clks = (DpmClocks_t *)dm_helpers_allocate_gpu_mem(
663 clk_mgr->base.base.ctx,
664 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
665 sizeof(DpmClocks_t),
666 &smu_dpm_clks.mc_address.quad_part);
667
668 if (smu_dpm_clks.dpm_clks == NULL) {
669 smu_dpm_clks.dpm_clks = &dummy_clocks;
670 smu_dpm_clks.mc_address.quad_part = 0;
671 }
672
673 ASSERT(smu_dpm_clks.dpm_clks);
674
675 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
676 clk_mgr->base.base.funcs = &dcn3_fpga_funcs;
677 } else {
678 struct clk_log_info log_info = {0};
679
680 clk_mgr->base.smu_ver = dcn31_smu_get_smu_version(&clk_mgr->base);
681
682 if (clk_mgr->base.smu_ver)
683 clk_mgr->base.smu_present = true;
684
685 /* TODO: Check we get what we expect during bringup */
686 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
687
688 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
689 dcn31_bw_params.wm_table = lpddr5_wm_table;
690 } else {
691 dcn31_bw_params.wm_table = ddr5_wm_table;
692 }
693 /* Saved clocks configured at boot for debug purposes */
694 dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
695
696 }
697
698 clk_mgr->base.base.dprefclk_khz = 600000;
699 clk_mgr->base.dccg->ref_dtbclk_khz = 600000;
700 dce_clock_read_ss_info(&clk_mgr->base);
701
702 clk_mgr->base.base.bw_params = &dcn31_bw_params;
703
704 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
705 dcn31_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
706
707 if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
708 dcn31_clk_mgr_helper_populate_bw_params(
709 &clk_mgr->base,
710 ctx->dc_bios->integrated_info,
711 smu_dpm_clks.dpm_clks);
712 }
713 }
714
715 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
716 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
717 smu_dpm_clks.dpm_clks);
718 }
719
dcn31_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)720 void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
721 {
722 struct clk_mgr_dcn31 *clk_mgr = TO_CLK_MGR_DCN31(clk_mgr_int);
723
724 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
725 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
726 clk_mgr->smu_wm_set.wm_set);
727 }
728