1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 #ifndef ADF_ACCEL_DEVICES_H_
4 #define ADF_ACCEL_DEVICES_H_
5 #include <linux/interrupt.h>
6 #include <linux/module.h>
7 #include <linux/list.h>
8 #include <linux/io.h>
9 #include <linux/ratelimit.h>
10 #include "adf_cfg_common.h"
11
12 #define ADF_DH895XCC_DEVICE_NAME "dh895xcc"
13 #define ADF_DH895XCCVF_DEVICE_NAME "dh895xccvf"
14 #define ADF_C62X_DEVICE_NAME "c6xx"
15 #define ADF_C62XVF_DEVICE_NAME "c6xxvf"
16 #define ADF_C3XXX_DEVICE_NAME "c3xxx"
17 #define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf"
18 #define ADF_4XXX_DEVICE_NAME "4xxx"
19 #define ADF_4XXX_PCI_DEVICE_ID 0x4940
20 #define ADF_4XXXIOV_PCI_DEVICE_ID 0x4941
21 #define ADF_DEVICE_FUSECTL_OFFSET 0x40
22 #define ADF_DEVICE_LEGFUSE_OFFSET 0x4C
23 #define ADF_DEVICE_FUSECTL_MASK 0x80000000
24 #define ADF_PCI_MAX_BARS 3
25 #define ADF_DEVICE_NAME_LENGTH 32
26 #define ADF_ETR_MAX_RINGS_PER_BANK 16
27 #define ADF_MAX_MSIX_VECTOR_NAME 48
28 #define ADF_DEVICE_NAME_PREFIX "qat_"
29
30 enum adf_accel_capabilities {
31 ADF_ACCEL_CAPABILITIES_NULL = 0,
32 ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 1,
33 ADF_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = 2,
34 ADF_ACCEL_CAPABILITIES_CIPHER = 4,
35 ADF_ACCEL_CAPABILITIES_AUTHENTICATION = 8,
36 ADF_ACCEL_CAPABILITIES_COMPRESSION = 32,
37 ADF_ACCEL_CAPABILITIES_LZS_COMPRESSION = 64,
38 ADF_ACCEL_CAPABILITIES_RANDOM_NUMBER = 128
39 };
40
41 struct adf_bar {
42 resource_size_t base_addr;
43 void __iomem *virt_addr;
44 resource_size_t size;
45 } __packed;
46
47 struct adf_accel_msix {
48 struct msix_entry *entries;
49 char **names;
50 u32 num_entries;
51 } __packed;
52
53 struct adf_accel_pci {
54 struct pci_dev *pci_dev;
55 struct adf_accel_msix msix_entries;
56 struct adf_bar pci_bars[ADF_PCI_MAX_BARS];
57 u8 revid;
58 u8 sku;
59 } __packed;
60
61 enum dev_state {
62 DEV_DOWN = 0,
63 DEV_UP
64 };
65
66 enum dev_sku_info {
67 DEV_SKU_1 = 0,
68 DEV_SKU_2,
69 DEV_SKU_3,
70 DEV_SKU_4,
71 DEV_SKU_VF,
72 DEV_SKU_UNKNOWN,
73 };
74
get_sku_info(enum dev_sku_info info)75 static inline const char *get_sku_info(enum dev_sku_info info)
76 {
77 switch (info) {
78 case DEV_SKU_1:
79 return "SKU1";
80 case DEV_SKU_2:
81 return "SKU2";
82 case DEV_SKU_3:
83 return "SKU3";
84 case DEV_SKU_4:
85 return "SKU4";
86 case DEV_SKU_VF:
87 return "SKUVF";
88 case DEV_SKU_UNKNOWN:
89 default:
90 break;
91 }
92 return "Unknown SKU";
93 }
94
95 struct adf_hw_device_class {
96 const char *name;
97 const enum adf_device_type type;
98 u32 instances;
99 } __packed;
100
101 struct arb_info {
102 u32 arb_cfg;
103 u32 arb_offset;
104 u32 wt2sam_offset;
105 };
106
107 struct admin_info {
108 u32 admin_msg_ur;
109 u32 admin_msg_lr;
110 u32 mailbox_offset;
111 };
112
113 struct adf_hw_csr_ops {
114 u64 (*build_csr_ring_base_addr)(dma_addr_t addr, u32 size);
115 u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
116 u32 ring);
117 void (*write_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
118 u32 ring, u32 value);
119 u32 (*read_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
120 u32 ring);
121 void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
122 u32 ring, u32 value);
123 u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);
124 void (*write_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
125 u32 ring, u32 value);
126 void (*write_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
127 u32 ring, dma_addr_t addr);
128 void (*write_csr_int_flag)(void __iomem *csr_base_addr, u32 bank,
129 u32 value);
130 void (*write_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
131 void (*write_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank,
132 u32 value);
133 void (*write_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank,
134 u32 value);
135 void (*write_csr_int_flag_and_col)(void __iomem *csr_base_addr,
136 u32 bank, u32 value);
137 void (*write_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank,
138 u32 value);
139 };
140
141 struct adf_cfg_device_data;
142 struct adf_accel_dev;
143 struct adf_etr_data;
144 struct adf_etr_ring_data;
145
146 struct adf_hw_device_data {
147 struct adf_hw_device_class *dev_class;
148 u32 (*get_accel_mask)(struct adf_hw_device_data *self);
149 u32 (*get_ae_mask)(struct adf_hw_device_data *self);
150 u32 (*get_accel_cap)(struct adf_accel_dev *accel_dev);
151 u32 (*get_sram_bar_id)(struct adf_hw_device_data *self);
152 u32 (*get_misc_bar_id)(struct adf_hw_device_data *self);
153 u32 (*get_etr_bar_id)(struct adf_hw_device_data *self);
154 u32 (*get_num_aes)(struct adf_hw_device_data *self);
155 u32 (*get_num_accels)(struct adf_hw_device_data *self);
156 u32 (*get_pf2vf_offset)(u32 i);
157 void (*get_arb_info)(struct arb_info *arb_csrs_info);
158 void (*get_admin_info)(struct admin_info *admin_csrs_info);
159 enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self);
160 int (*alloc_irq)(struct adf_accel_dev *accel_dev);
161 void (*free_irq)(struct adf_accel_dev *accel_dev);
162 void (*enable_error_correction)(struct adf_accel_dev *accel_dev);
163 int (*init_admin_comms)(struct adf_accel_dev *accel_dev);
164 void (*exit_admin_comms)(struct adf_accel_dev *accel_dev);
165 int (*send_admin_init)(struct adf_accel_dev *accel_dev);
166 int (*init_arb)(struct adf_accel_dev *accel_dev);
167 void (*exit_arb)(struct adf_accel_dev *accel_dev);
168 const u32 *(*get_arb_mapping)(void);
169 int (*init_device)(struct adf_accel_dev *accel_dev);
170 void (*disable_iov)(struct adf_accel_dev *accel_dev);
171 void (*configure_iov_threads)(struct adf_accel_dev *accel_dev,
172 bool enable);
173 void (*enable_ints)(struct adf_accel_dev *accel_dev);
174 void (*set_ssm_wdtimer)(struct adf_accel_dev *accel_dev);
175 int (*enable_pfvf_comms)(struct adf_accel_dev *accel_dev);
176 void (*reset_device)(struct adf_accel_dev *accel_dev);
177 void (*set_msix_rttable)(struct adf_accel_dev *accel_dev);
178 char *(*uof_get_name)(u32 obj_num);
179 u32 (*uof_get_num_objs)(void);
180 u32 (*uof_get_ae_mask)(u32 obj_num);
181 struct adf_hw_csr_ops csr_ops;
182 const char *fw_name;
183 const char *fw_mmp_name;
184 u32 fuses;
185 u32 straps;
186 u32 accel_capabilities_mask;
187 u32 instance_id;
188 u16 accel_mask;
189 u32 ae_mask;
190 u32 admin_ae_mask;
191 u16 tx_rings_mask;
192 u8 tx_rx_gap;
193 u8 num_banks;
194 u8 num_rings_per_bank;
195 u8 num_accel;
196 u8 num_logical_accel;
197 u8 num_engines;
198 u8 min_iov_compat_ver;
199 } __packed;
200
201 /* CSR write macro */
202 #define ADF_CSR_WR(csr_base, csr_offset, val) \
203 __raw_writel(val, csr_base + csr_offset)
204
205 /* CSR read macro */
206 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset)
207
208 #define GET_DEV(accel_dev) ((accel_dev)->accel_pci_dev.pci_dev->dev)
209 #define GET_BARS(accel_dev) ((accel_dev)->accel_pci_dev.pci_bars)
210 #define GET_HW_DATA(accel_dev) (accel_dev->hw_device)
211 #define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks)
212 #define GET_NUM_RINGS_PER_BANK(accel_dev) \
213 GET_HW_DATA(accel_dev)->num_rings_per_bank
214 #define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
215 #define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_ops)
216 #define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev
217
218 struct adf_admin_comms;
219 struct icp_qat_fw_loader_handle;
220 struct adf_fw_loader_data {
221 struct icp_qat_fw_loader_handle *fw_loader;
222 const struct firmware *uof_fw;
223 const struct firmware *mmp_fw;
224 };
225
226 struct adf_accel_vf_info {
227 struct adf_accel_dev *accel_dev;
228 struct mutex pf2vf_lock; /* protect CSR access for PF2VF messages */
229 struct ratelimit_state vf2pf_ratelimit;
230 u32 vf_nr;
231 bool init;
232 };
233
234 struct adf_accel_dev {
235 struct adf_etr_data *transport;
236 struct adf_hw_device_data *hw_device;
237 struct adf_cfg_device_data *cfg;
238 struct adf_fw_loader_data *fw_loader;
239 struct adf_admin_comms *admin;
240 struct list_head crypto_list;
241 unsigned long status;
242 atomic_t ref_count;
243 struct dentry *debugfs_dir;
244 struct list_head list;
245 struct module *owner;
246 struct adf_accel_pci accel_pci_dev;
247 union {
248 struct {
249 /* protects VF2PF interrupts access */
250 spinlock_t vf2pf_ints_lock;
251 /* vf_info is non-zero when SR-IOV is init'ed */
252 struct adf_accel_vf_info *vf_info;
253 } pf;
254 struct {
255 char *irq_name;
256 struct tasklet_struct pf2vf_bh_tasklet;
257 struct mutex vf2pf_lock; /* protect CSR access */
258 struct completion iov_msg_completion;
259 u8 compatible;
260 u8 pf_version;
261 } vf;
262 };
263 bool is_vf;
264 u32 accel_id;
265 } __packed;
266 #endif
267